Pin Diagram of 80286 Microprocessor

Architecture of 80286 Microprocessor

the architectural representation of 80286 microprocessor:

As
we have already mentioned earlier that it is a 16-bit microprocessor thus holds a 16-bit data bus
and 24-bit address bus. Also, unlike the 8086 microprocessor, it offers non-multiplexed address
and data bus, which increases the operating speed of the system.

80286 is composed of nearly around 125K transistors and the pin configuration has a total of 68
pins.

The CPU, central processing unit of 80286 microprocessor, consists of 4 functional block:

 Address Unit
 Bus Unit
 Instruction Unit
 Execution Unit

ORGANIZATION AND ADRESSING MODES OF 80286:

The interrupt vector table of 80286 is organized in the same way as that of 8086. Some of
the interrupt types are reserved for exceptions, single-stepping and processor extension segment
overrun, etc. When the 80286 is reset, it always starts the execution in real address mode.
Addressing Modes of 80286 Microprocessor:

The 80286 has eight addressing modes for instructions to access operands from memory. The
eight different Addressing Modes of 80286 Microprocessor are as follows:

 Register operand mode

 Immediate operand
 Direct mode
 Register indirect mode
 Based mode
 Indexed mode
 Based indexed mode
 Based indexed mode with displacement
The first two operating modes are related with the register and immediate operands. The
remaining six modes are provided to specify the location of an operand in a memory segment. A
memory operand address consists of two 16-bit components, namely, segment selector and
offset. The segment selector is supplied by a segment register either implicitly chosen by a
segment override prefixes. The offset is determined by summing any combination of the
following three address elements.

 The displacement (8- or 16-bit immediate value)

 The base (content of the BX or BP)
 Any carry out from the 16-bit addition is ignored; eight-bit displacements are sign
extended to 16-bit values
Combinations of these three address elements define the six memory addressing modes. All
above Addressing Modes of 80286 Microprocessor are explained in this section.

Register Operand Mode In this mode, the operand is located in one of the 8- or 16-bit general-
purpose registers.

Immediate Operand Mode In immediate operand mode, the operand is included in the
instruction itself.

Direct Mode In direct addressing mode, the operand’s offset is containing in the instruction as
an 8- or 16-bit immediate displacement.

Register Indirect Mode In register indirect addressing mode, the operand’s offset is stored in
one of the general-purpose registers or in SI, DI, BX or BP.
Based Mode In this mode, the operand’s offset is computed after adding an 8- or 16-hit
displacement with the contents of a base register (BX or BP).

Indexed Mode In index addressing mode, the offset is determined by adding a displacement
with the contents of an index register (SI or DI).

Based Indexed Mode In this mode, the operand’s offset is calculated by the sum of the contents
of a base register and an index register.

Based Indexed Mode With Displacement In based indexed with displacement addressing
mode, the operands offset is obtained by adding an 8-bit or 16-bit immediate displacement with
contents of a base register and an index register.

PINOUT DIAGARAM OF 80386

ARCHITECTURE OF 80386

Architecture of 80386 Microprocessor

The figure below shows the architectural representation of 80386 microprocessor:

 Ba
sically, it has 6 functional units which are as follows:

1. Bus Interface Unit

2. Code Fetch Unit
3. Instruction Decode Unit
4. Execution Unit
5. Memory Management Unit
As we have already discussed that the 80386 possesses the ability of 3 stages pipelining thus
performs fetching, decoding, and execution simultaneously along with memory management and
bus accessing. Thus all these units operate parallelly. This pipelining technique leads to a
reduction in overall processing time thereby increasing the performance of the overall system.

Let us now move further and understand the operation of each unit in detail.

1. Bus Interface Unit

The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as a 32-bit address
bus. Whenever a need for instruction or a data fetch is generated by the system then the BIU
generates signals (according to the priority) for activating the data and address bus in order to
fetch the data from the desired address.

The BIU connects the peripheral devices through the memory unit and also controls the
interfacing of external buses with the coprocessors.
2. Code Prefetch Unit

This unit fetches the instructions stored in the memory by making use of system buses.
Whenever the system generates a need for instruction then the code prefetch unit fetches that
instruction from the memory and stores it in a 16-byte prefetch queue. So to speed up the
operation this unit fetches the instructions in advance and the queue stores these instructions. The
sequence in which the instructions are fetched and gets stored in the queue depends on the order
they exist in the memory.
As this unit fetches one double word in a single access. So, in such a case, it is not necessary that
each time only a single instruction will be fetched, as the fetched instruction can be parts of two
different instructions.

It is to be noted here that, code prefetching holds lower priority than data transferring. As
whenever a need for data transfer is generated by the system then immediately the code
prefetcher leaves control over the buses. So that the BIU can transfer the required data. But
prefetching of instruction and storing it in the queue reduces the wait for the upcoming
instruction to almost zero.

3. Instruction Decode Unit

We know that instructions in the memory are stored in the form of bits. So, this unit decodes the
instructions stored in the prefetch queue. Basically the decoder changes the machine language
code into assembly language and transfers it to the processor for further execution.

4. Execution Unit

The decoded instructions are stored in the decoded instruction queue. So, these instructions are
provided to the execution unit in order to execute the instructions. The execution unit controls
the execution of the decoded instructions. This unit has a 32-bit ALU, that performs the
operation over 32-bit data in one cycle. Also, it consists of 8 general purpose as well as 8 special
purpose registers. These are used for data handling and calculation of offset address.

5. Memory Management Unit

This unit has two separate units within it. These are

1. Segmentation Unit and

2. Paging Unit
Segmentation unit: The segmentation unit plays a vital role in the 80836 microprocessor. It
offers a protection mechanism in order to protect the code or data present in the memory from
application programs. It gives 4 level protection to the data or code present in the memory. Every
information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the
highest priority and PL3 holds the lowest priority.
Suppose a file (either data or code) is needed to be accessed is stored in the memory at PL0.
Then only those programs which are working at PL0 would be able to access that file. While
other programs will not be able to access the same. Also, if a file is present at PL1, then
programs of PL0 and PL1 both can access it. As PL0 has a higher priority than PL1. So, for
protection purposes, the main part of the OS is stored in PL0 while PL3 holds the user programs.
Providing protection to the data or code inside the system is the most advantageous factor that
was first given by the 80386 microprocessor.

Paging Unit: The paging unit operates only in protected mode and it changes the linear address
into a physical address. As the programmer only provides the virtual address and not the physical
address. The segmentation unit controls the action of the paging unit, as the segmentation unit
has the ability to convert the logical address into the linear address at the time of executing an
instruction. Basically, it changes the overall task map into pages and each page has a size of 4K.
This allows the handling of tasks in the form of pages rather than segments.
The paging unit supports multitasking. This is so because the physical memory is not required to
hold the whole segment of any task. Despite this, only that part of the segment which is needed
to be currently executed must be stored in that memory whose physical address is calculated by
the paging unit. This resultantly reduces the memory requirement and hence this frees the
memory for other tasks. Thus by this we get an effective way for managing the memory to
support multitasking.

ORGANIZATION OF 80386

The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX, EBP, ESP,
ESI, and EDI. These registers are used interchangeably to contain the operands of logical and
arithmetic operations.

ADDRESSING MODES OF 80386

Addressing Modes of 80386 Microprocessor:

The 80386 can operate in all the addressing modes which were available with the 80286
processor. The 80386 processor can also operate in all addressing modes of 80286 with 32-bit
immediate or 32-bit register operands or displacements. Besides all addressing modes of 80286,
the 80386 has a family of scaled modes. In the scaled modes, the index register values will be
multiplied by a valid scale factor to get the final displacement. The valid scale factors are 1, 2, 4
and 8. In this section, all scaled modes are briefly explained.

Scaled Indexed Mode The content of an index register is multiplied by a scale factor 1, 2, 4 or 8
and subsequently the computed value will be added to get the final operand offset. For example,
Based Scaled Indexed Mode The based scaled indexed mode instruction is the content of an
index register is multiplied by a scale factor and the computed value is added with the base
register to find the offset.

Based Scaled indexed Mode with Displacement The based scaled indexed mode with
displacement instruction is the content of an index register multiplied by a scaling factor and the
computed value is added with the content of base register and a displacement to obtain the
address of an operand.

PIN OUT DIAGRAM OF 80486

Architecture of 80486 Microprocessor:

The 80486DX is a 32-bit processor. Figure 11.46 shows the simplified block diagram of 80486
and the internal architecture of 80486 Microprocessor is depicted in Fig. 11.47.

The architecture of Intel’s 80486 can be divided into three different sections such as

 Bus interface unit (BIU),

 Execution and control unit (EU), and
 Floating-point unit (FU).
Bus Interface Unit (BIU) The bus interface unit is used to organize all the bus activities of the
processor. The address driver is connected with the internal 32-bit address output of the cache
and the system bus. The data bus transreceivers are interconnected between the internal 32-bit
data bus and system bus. The write data buffer is a queue of four 80-bit registers and is able to
hold the 80-bit data which will he written to the memory. Due to pipelined execution of the write
operation, data must be available in advance. To control the bus access and operations, the
following bus control and request sequencer signals A̅ D̅ S̅ , W/R̅ , D/C̅ , M/I̅ O̅ , PCD, PWT, R̅ D̅ Y̅ ,
L̅ O̅ C̅ K̅ , P̅ L̅ O̅ C̅ K̅ , B̅ O̅ F̅ F̅ , A̅ 2̅0̅M̅ , BREQ, HOLD, HLDA, RESET, INTR, NMI, F̅ E̅ R̅ R̅ and
I̅ G̅ N̅ N̅ E̅ are used.

Execution Unit (EU) and Control Unit (CU) The burst control signal updates the processor
that the burst is ready. This signal works as a ready signal in the burst cycle. The B̅ L̅ A̅ S̅ T̅ output
shows that the previous burst cycle is over. The bus size control signals B̅ S̅ 1̅6̅ and B̅ S̅ 8̅ indicates
dynamic bus sizing. The cache control signals K̅ E̅ N̅ , FLUSH, AHOLD and E̅ A̅ D̅ S̅ are used to
control the cache control unit.
The parity generation and control unit generates the parity and carries out the checking during
the processor operation. The boundary scan control unit of the processor performs boundary scan
tests operation to ensure the correct operation of all components of the circuit on the mother
board.

The prefetcher unit fetches the codes from the memory and arranges them in a 32-byte code
queue. The function of the instruction decoder is to receive the code from the code queue and
then decodes the instruction code sequentially. The output of the decoder is fed to the control
unit to derive the control signals, which are used for execution of the decoded instructions.
Before execution, the protection unit should check all protection norms. If there is in any
violation, an appropriate exception is generated.

The control ROM stores a microprogram to generate control signals for execution of instructions.
The register hank and ALU are used for their usual operation just like they perform in 80286.
The barrel shifter is used to perform the shift and rotate algorithms. The segmentation unit,
descriptor registers, paging unit, translation look aside buffer and limit and attribute PLA are
worked together for the virtual memory management. These units also provide protection to the
op-codes or operand in the physical memory.

Floating–point Unit (FPU) The floating-point unit and register banks or FPU communicate with
the bus interface unit (BIU) under the control of memory management unit (MMU), through a
64-bit internal data bus. Generally, the FPU is used for mathematical data processing at very
high speed as compared to the ALU.

ORGANZATION OF 80486

Bus Interface Unit (BIU) The bus interface unit is used to organize all the bus activities of the
processor. The address driver is connected with the internal 32-bit address output of the cache
and the system bus. The data bus transreceivers are interconnected between the internal 32-bit
data bus and system bus

INTRODUCTION TO MICRO CONTROLLERS:

Introduction to Microcontroller

A microcontroller is an electronic device belonging to the microcomputer family. These are

fabricated using the VLSI technology on a single chip. There are microcontrollers available in
the present market with different word length starting from 4 bit, 8 bit, 64 bit to 128 bit.
Microcontroller

In a broader sense, the components which constitute a microcontroller are the memory,
peripherals and most crucially a processor. Microcontrollers are present in devices where the
user has to exert a degree of control. They are designed and implemented to execute a specific
function such as displaying integers or characters on an LCD display module of a home
appliance. Application of microcontrollers is myriad. In simpler terms, any gadget or equipment
which has to deal with the functions such as measuring, controlling, displaying and calculating
the values consist of a microcontroller chip inside it. They are present in almost all the present
day home appliances, toys, traffic lights, office instruments and various day-to-day appliances.

Microcontroller Architecture

The most important part of a microcontroller is a central processing unit with a word length
ranging from 4-bit to 64-bit and in some modern microcontrollers the word length goes even
beyond the limit of 64-bit. A timer is one other constituent of a microcontroller. There is a
watchdog timer. Memory spaces such as RAM, ROM, EEPROM, EPROM are there to store data
and programs. For data storage, volatile memory RAM is used while for the program and
operating parameter storage ROM and other memory spaces are used.

CPU: Being regarded as the brain of the microcontroller, central processing unit fetches, decodes
and executes the instructions. It coordinates various activities taking place in the microcontroller.
I/O ports: There are several parallel input/output ports in a microcontroller. They are used to
interface various peripherals such as printers, external memories, LEDs and LCDs to the
microcontroller. Apart from parallel ports, there are serial ports to interface serially connected
peripherals with the microcontroller.

Memory: As in the case of a microprocessor, a microcontroller has spaces for memories such as
RAM, ROM including EEROM and EPROM. It also allocates a certain amount of flash memory
to store program source code.

Timers and counters: These are the fascinating constituent parts of a microcontroller. Timers
and counters are used in operations which include modulation, clock functions, frequency
generation and measuring and pulse generation.

Analog to digital converters (ADCs): Such converters are useful while converting the output of
a sensor which would be in analog form.

Digital to analog converter (DAC): The working of a DAC is just the reverse of an analog to
digital converter. As it is obvious, the output will be an analog signal which can be used to
control the analog peripherals such a motor.