A Reconfigurable Arbiter PUF Based

on VGSOT MTJ

Kunal Kranti Das1(B) , Aditya Japa2 , and Deepika Gupta1

1 Department of Electronics and Communication Engineering, Dr. Shyama Prasad Mukherjee
International Institute of Information Technology, Naya Raipur, Chhattisgarh, India
kunalkrantidas@gmail.com
2 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education

Foundation, Hyderabad, Telangana, India

Abstract. With the serious scaling limitations of complementary metal-oxide-

semiconductor technology, emerging spintronic devices have attracted recent
attention for next-generation energy-efficient and secure systems. Voltage-Gated
Spin-Orbit Torque (VGSOT) based Magnetic Tunnelling Junction (MTJ) device
is proved to show lower energy consumptions with stochastic switching, process
variations, and chaotic magnetization. Exploiting these intrinsic variations, this
paper for the first time presents a reconfigurable arbiter physically unclonable
function (PUF). Further, the PUF functionality is validated considering VGSOT
MTJ and 45nm CMOS technology. Considering the state of VGSOT devices, the
proposed PUF is observed to be fully reconfigurable. Considering the abilities of
VGSOT, PUF shows higher uniqueness of 50.2% at a supply voltage of 0.8V. Addi-
tionally, PUF achieves high reliability of 95.8% considering supply voltage and
temperature variations. Moreover, at a supply voltage of 0.8V, the proposed PUF
achieves lower energy consumption of 24fJ/bit.

Keywords: Spintronics · Voltage-Gated Spin-Orbit Torque (VGSOT) ·

Magnetic Tunnelling Junction (MTJ) · Hardware Security · Physically
Unclonable Function (PUF)

1 Introduction
With complementary metal oxide semiconductor (CMOS) technology scaling, increased
leakage current has become a key barrier for modern CMOS-based integrated circuits
[1–3]. Furthermore, CMOS-based memories have shown increased write and read energy
consumption with degraded performance. To address these issues, researchers have
proposed several emerging magnetic devices to replace traditional CMOS technology.
Because of its promising characteristics like nonvolatility, 3-D incorporation, and scala-
bility, spintronic devices have attracted recent attention [4, 5]. Spintronic memories have
the ability to outperform CMOS-based Static Random Access Memory (SRAM) or
Dynamic Random Access Memory (DRAM) due to their zero static power consump-
tion, and nonvolatility [6]. Despite the promising nature of perpendicular magnetic tunnel

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022

A. P. Shah et al. (Eds.): VDAT 2022, CCIS 1687, pp. 320–330, 2022.
https://doi.org/10.1007/978-3-031-21514-8_27
 A Reconfigurable Arbiter PUF Based on VGSOT MTJ 321

junction (p-MTJ) based on spin-transfer torque (STT) MTJ devices, it still suffers from
many issues, including a long incubation time, high switching current densities, and
read current disturbance. Recent experiments have shown that a three terminal p-MTJ
based on a ferromagnetic (FM)/antiferromagnetic (AFM)/oxide structure shows field-
free spin orbit torque (SOT) switching. This is because the AFM is not only able to
create the SOT but also offer an exchange bias (HEX ) to substitute the external field [7,
8]. However, the HEX given by these structures is insufficient to perform a full switch,
leading to low dependability and a high critical switching current. To address these
challenges, researchers developed a novel switching mechanism based on the VGSOT
effect, which employs the voltage-controlled magnetic anisotropy (VCMA) to aid the
SOT. The energy barrier of MTJ between parallel (P) and anti-parallel (AP) is lowered
due to the VCMA effect, while the bias voltage supplied to the oxide layer of the MTJ
is positive [9]. As a consequence of adding the VCMA effect in the p-MTJ based on the
FM/AFM/oxide structure, the crucial critical SOT current reduces, resulting in improved
switching reliability and lower switching energy consumption [10].
Apart from this, VGSOT MTJ shows large process variations that can be explored
to design hardware security primitives like physically unclonable function (PUF). PUF
is a function that generates on-the-fly security keys by exploring process variations [11,
12]. Also, the actual manufacturer cannot perfectly clone or replicate two indistinguish-
able PUFs since manufacturing process variances are intrinsically unpredictable. PUF’s
challenge-response method is used to verify the identity of devices and systems [13].
PUFs of many varieties have been proposed in recent years, including delay PUFs [14],
memory PUF (MPUF) [15], flash PUFs [16], and flip-flop PUFs [17]. These PUFs show
a huge area overhead due to the enormous number of components in their memory cells
whereas a typical PUF employs many kilobits of memory cells. Designing a CMOS-
based PUF with a lower footprint, and low energy consumption with higher reliability
is always a challenge. To avoid this, a unique VGSOT MTJ-based reconfigurable arbiter
PUF is designed. Importantly, the reported design is evaluated for reliability, unique-
ness, and uniformity characteristics. The design has been examined by exploring 45nm
CMOS technology and the VGSOT MTJ model. The remainder of the paper is laid
out in the following manner. Section 2 presents the device structure, models explored,
and characteristics of VGSOT MTJ. Further, the VGSOT-based proposed PUF design is
introduced in Sect. 3. Apart from this, the proposed PUF is analyzed and several perfor-
mance parameters including uniqueness, uniformity, and reliability have been calculated
in Sect. 4. Further, the performance of the proposed PUF is compared with other latest
PUF designs in the literature. Finally, conclusions are offered in Sect. 5.

2 VGSOT MTJ Device and Characteristics

The VGSOT MTJ is a three-terminal device that comprises two ferromagnetic layers
(CoFeB) placed on top of the AFM layer (IrMn) and divided by an extreme-thin oxide
layer (MgO) as shown in Fig. 1(a). This thin oxide layer works as a barrier for cur-
rents. The two FM layers are called as a fixed layer and a free layer. The fixed layer
magnetization is often static in one direction, whereas the magnetization of the free
layer is changeable. If the ferromagnetic directions of both the layers are the same
322 K. K. Das et al.

Fig. 1. (a) VGSOT device structure with the symbol (b) Switching characteristics demonstrating
anti-parallel and parallel states.

then the MTJ enters into a parallel state and shows lower resistance (RP ). Otherwise (if
the ferromagnetic directions of both the layers are opposite), MTJ enters into an anti-
parallel state and shows higher resistance (RAP ). When a current (ISOT ) travels through
the anti-ferromagnetic metal, the spin-orbit coupling formed by the spin-hall effects
(SHE)occurs. Due to SHE, a vertically spin current will be induced on the free layer’s
magnetization. Further, AFM metal provides in-plane exchange bias (HEX ) due to which
no outer magnetic field is required for the switching of the MTJ. Upon supplying a posi-
tive voltage (Vb ) across the p-MTJ, its energy barrier can be reduced temporarily during
the switching according to the VCMA effect.
This paper explores a VGOST MTJ Verilog-A model with perpendicular magnetic
anisotropy [9]. This model captures complete switching behaviour with process variation
effects. The important parameters of VGOST MTJ have been summarized in Table 1.
More details of the VGSOT MTJ Verilog-A model, device parameters, and characteristics
can be found in [9, 10]. Figure 1(b) shows the switching characteristics of VGSOT MTJ
whereas MTJ shows both parallel and antiparallel states. When current flows through
 A Reconfigurable Arbiter PUF Based on VGSOT MTJ 323

Table 1. VGSOT MTJ device parameters

Parameter Description Unit Default Value

tsl Free layer thickness nm 1.1
tox MgO barrier thickness nm 1.4
TMR TMR ratio under zero bias voltage % 100
a, b, r MTJ surface length, width, radius nm 50, 50, 25
d, w, l AFM strip thickness, width, length nm 3, 50, 60
rho AFM strip resistivity -m 278e-8
shape MTJ surface shape - Circle

the AFM layer from T2 to T3 , MTJ enters into an anti-parallel state. In contrast, if the
current flow through the AFM layer from T3 to T2 , MTJ enters into a parallel state. The
actual thickness of the oxide layer and free layer cannot be kept at one constant amount
as a result of natural fabrication process variations. As a result, MTJ exhibits significant
variation in switching resistance. The range of parallel MTJ resistance and anti-parallel
MTJ resistance can be observed from the complete stochastic switching operation from
parallel to anti-parallel and from anti-parallel to parallel respectively [18]. These changes
in the value of the resistance cause the change in device current as shown in Fig. 1(b).
Due to the above process-dependent characteristics, the VGSOT device can be explored
to construct a resilient PUF design. Exploiting VGSOT MTJ device process variations,
this paper proposes arbiter MPUF which is explained in the next sections. The Verilog-A
based VGSOT model has been plugged into the Cadence virtuoso environment to design
and analyze the VGSOT MTJ based PUF.

3 Proposed PUF Design and Operation

The proposed design of the arbiter MPUF is shown in Fig. 2. It consists of two delay
paths (delay path1 and delay path2) that are designed using emerging VGSOT devices.
Each delay path is controlled using source lines (SLs are S0 , S1 …, Sn-1 ) and bit lines
(BLs are B0 , B1 , … Bn-1 ) as shown in Fig. 2. Moreover, the selection of SL and BL
signals decides the state of VGSOT. Further, each delay path consists of control signals
(C0 , C1 , … Cn-1 ) that operate access transistors and act as challenges to PUF. The
pre-charge sense amplifier (PCSA) circuit [19] used in the proposed MPUF compares
current discharge speeds to obtain an output response (Qm ). The signal propagation
delays are compared for traditional arbiter PUFs to produce the output response. This
makes MPUF a more suitable security application for high-speed circuits. Interestingly,
the proposed MPUF exploits the intrinsic randomness of the VGSOT MTJ device to
produce a difference in delays of two paths and hence, obtain the output response. This
delay difference makes MPUF produce a unique1-bit response, upon applying different
challenges. To get a larger bit response we can repeat the same circuit multiple times.
Figure 3(a) shows an arbiter MPUF circuit with 4 VGSOT MTJ devices to demon-
strate the functionality of the proposed PUF. There are two delay paths, each with four
324 K. K. Das et al.

Fig. 2. VGSOT MTJ-based proposed arbiter MPUF architecture.

Fig. 3. Proposed arbiter MPUF architecture (a) With similar challenges for both delay paths (b)
With dissimilar challenges for both delay paths.

VGSOT MTJ cells. The proposed PUF design is explained in two different phases. These
are the writing phase and followed by the read phase. In the writing phase of operation,
read enable (RWL) is low and all RWL driven transistors are turned off. On the other
hand, the write enables (WWL) and all challenges (C0 -C3 and C 0 -C 3 ) of PUF become
logic high. All SLs and BLs can be used to set each VGSOT cell into the parallel (P) or
anti-parallel (AP) state separately. When BL is high and SL is low, the VGSOT switches
from P to AP. In contrast, when SL is high and the BL line is low, VGSOT is switched
from AP to P. The antiparallel VGSOT state denotes logic 1, while the parallel VGSOT
state denotes logic 0. The proposed PUF can act as a reconfigurable design that is highly
suitable for encryption applications. This is due to the fact that in the write phase all
VGSOT devices have been set into either P or AP state that can be reconfigured every
time. Thus, the PUF achieves a unique response by setting the VGSOT states.
During the read phase, RWL is high and all RWL-controlled transistors are switched
ON. As a result, all the VGSOT devices form a delay path that produces a fixed prop-
agation delay depending on the challenges applied. When all of the challenges are low
for two delay paths, VGSOT devices form a unique delay path as shown in Fig. 3(a)
(red line). Further, output Qm is produced by exploiting the different propagation delays
caused by the process variations of VGSOT devices and their respective states. Follow-
ing another method, upon applying different challenges to delay paths, MPUF produces
 A Reconfigurable Arbiter PUF Based on VGSOT MTJ 325

Fig. 4. Transient characteristics of proposed PUF design for 10 samples.

a unique equivalent propagation delay as shown in Fig. 3(b). Figure 4 shows the tran-
sient characteristics of the proposed PUF for 10 different samples considering process
variations at a supply voltage of 0.8V. It can be observed that out of 10 samples, 5 PUFs
produce 0V (logic ‘0’), and the other 5 produce 0.8V (logic ‘1’). The proposed MPUF
consists of two delay paths and each delay path has “m” number of MRAM cells. Each
MRAM cell state (P or AP) indicates a challenge value. For example, consider “m”
VGSOT cells that show a 2m number of distinct potential configurations. Furthermore,
each delay path does not need to have the same challenge value. For example, if delay
path 1 has an “m” MRAM cells and delay path 2 has “n” MRAM cells, there might be
2m × 2n potential challenge response pairs (CRPs). Further, if “p” and “q” distinct BL
access transistor challenge values are used for delay path 1 and delay path 2, the number
of CRPs can be increased. Therefore, the proposed arbiter MPUF shows a large CRPs
of 2m × 2n × p × q number. The large number of CRP becomes the exclusive property
of MPUF.

4 Results and Discussion

In this paper, arbiter MPUF is proposed that explore a compact VGSOT MTJ model
with 45 nm CMOS technology [9]. Significantly, MPUFs are simulated and analyzed
to obtain three important performance parameters i.e. uniqueness, uniformity, and relia-
bility. Specifically, the uniqueness of the PUF has resulted from their ability to generate
output differently when the same challenge is applied. The presented arbiter MPUF
is analyzed to obtain several different performance parameters including uniqueness,
uniformity, and reliability. To model the process variations and mismatch, monte carlo
simulations were run on the design for 25 separate PUF instances with 200 challenges.
326 K. K. Das et al.

The simulation is run at a supply voltage of 0.8V and a nominal temperature of 270
C. The inter-hamming distance (inter-HD) or uniqueness [21] of the proposed MPUF
is found to be 50.21%, as shown in Fig. 5. As a result, the proposed MPUF can produce
distinct CRPs to identify various chips.
Uniformity is used to estimate the unpredictability of the response of the PUFs even
if one has the previous circuit information. The uniformity of the proposed MPUF is
found to be 50.75% as shown in Fig. 6. It means that the response contains almost
an equal number of 1’s and 0’s. The result shows that our proposed MPUF is highly
unpredictable and random.

Fig. 5. Distribution of normalized Inter HD of proposed PUF.

To calculate the reliability, the proposed PUF is simulated at a supply voltage of 0.8V
with a nominal operating temperature of 27 °C, and the response is recorded as “Ri ”.
Further, the same procedure is repeated on the chip under various operating conditions
for the same challenge and noted in the response termed “R i ”. Then, the average intra-
hamming (intra-HD) distance of several samples of “R i ” at varying temperatures (-20 °C
to 70 °C) and voltages (0.8V to 1.2V) has been calculated. The intra-HD of the proposed
PUF is 0.043 and the average reliability is found to be 95.7% as shown in Fig. 7. Thus,
the proposed PUF is proved to be robust against environmental variations.
At a supply voltage of 0.8V, the proposed MPUF shows read and write power
consumption of 16.12 nW and 1.189 µW. Further, the propagation delays of the pro-
posed PUF for reading and writing operations resulted in 5ns and 10ns respectively.
Table 2 compares the performance of the proposed arbiter PUF with recent literature.
It can be observed that the proposed arbiter MPUF has shown higher reliability and
 A Reconfigurable Arbiter PUF Based on VGSOT MTJ 327

Fig. 6. Distribution of normalized Hamming Weight of proposed PUF.

Fig. 7. Distribution of normalized Intra HD of proposed PUF.

uniqueness. The proposed PUF exploits the characteristics and strong process variations
of VGSOT MTJ which enable the PUF to enhance its performance. Further, exploiting
the characteristics of VGSOT MTJ, the proposed PUF achieved a large amount of CRP
328 K. K. Das et al.

Table 2. Performance comparison of proposed PUF with recent literature

Parameters [21] [23] [24] Proposed Work

Technology (nm) 65 180 40 45
Type of PUF Voltage array CMOS Arbiter STT-MRAM VGSOT MTJ arbiter
Possible CRPs 1.15 × 1018 2m – 2m × 2n × p × q
Energy 0.3pJ – 6.60 pJ 24 fJ
consumption/bit
Voltage range (V) 0.8–1 1.75–1.85 0.9–1.1 0.8–1.2
Temperature 0–50 20–70 -45 to 100 0–50
range (°C)
Uniqueness (%) 50.26 40 50.1 50.2
Reliability (%) 95.34 96.5 96.73 95.7
Unifomity (%) – – 51 50.75

space compared to other designs. The proposed PUF has achieved a lower energy con-
sumption of 24fJ/bit at a supply voltage of 0.8V. This shows that it can be used in low
power and lightweight security for digital devices.

5 Conclusion

This paper proposed a novel ultra-low power arbiter PUF with high-quality metrics.
The proposed arbiter MPUF explores the innate process variations of VGSOT MTJ.
Furthermore, in comparison to traditional arbiter PUFs, the proposed PUF is reconfig-
urable and can generate a large amount of CRP space. The proposed PUF has shown
higher uniqueness of 50.2% at a supply voltage of 0.8V. Moreover, PUF has shown
high reliability of 95.7% considering supply voltage and temperature variations. At a
supply voltage of 0.8V, the proposed PUF has shown a lower energy consumption of
24fJ/bit. The proposed arbiter PUF based on VGSOT MTJ is highly suitable for device
authentication and key generation for low-power devices.

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