ESD: Module 1

Module-1
Introduction to embedded systems
1.1 WHAT IS AN EMBEDDED SYSTEM?

An embedded system is an electronic/electro-mechanical system designed to perform a specific

function and is a combination of both hardware and firmware (software).
Every embedded system is unique, and the hardware as well as the firmware is highly specialized
to the application domain.
Example: Telecommunications, medical equipment, industrial control, consumer products, etc.
1.2 EMBEDDED SYSTEMS vs. GENERAL COMPUTING SYSTEM

General Purpose System Embedded System

A system which is a combination of A system which is a combination of special

generic hardware and General Purpose purpose hardware and embedded OS for
Operating System for executing a variety executing a specific set of applications
of applications
Contain a General Purpose Operating May or may not contain an operating
System (GPOS) system for functioning

Applications are alterable (programmable) The firmware of the embedded system is

by user (It is possible for the end user to pre-programmed and it is non-alterable by
re-install the Operating System, and add or end-user (There may be exceptions for
remove user applications) systems supporting OS kernel image
flashing through special hardware settings)

Performance is the key deciding factor on Application specific requirements (like

the selection of the system. Always ‘Faster performance, power requirements, memory
is Better’ usage etc) are the key deciding factors
Less/not at all tailored towards reduced Highly tailored to take advantage of the
operating power requirements, options for power saving modes supported by hardware
different levels of power management. and Operating System
Response requirements are not time For certain category of embedded systems
critical like mission critical systems, the response
time requirement is highly critical
Need not be deterministic in execution Execution behavior is deterministic for
behavior certain type of embedded systems like
‘Hard Real Time’ systems

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1.3 HISTORY OF EMBEDDED SYSTEMS

• Embedded systems were in existence even before the IT revolution. In the olden days
embedded systems were built around the old vacuum tube and transistor technologies and
the embedded algorithm was developed in low level languages. In the olden days
embedded systems were built around the old vacuum tube and transistor technologies and
the embedded algorithm was developed in low level languages.

• Advances in semiconductor and nano-technology and IT revolution gave way to the

development of miniature embedded systems.

• The first recognized modem embedded system is the Apollo Guidance Computer (AGC)
developed by the MIT Instrumentation Laboratory for the lunar expedition.

• MIT's original design was based on 4K words of fixed memory (Read Only Memory) and
256 words of erasable memory (Random Access Memory).

• By June 1963, the figures reached 10K of fixed and 1K of erasable memory. The final
configuration was 36K words of fixed memory and 2K words of erasable memory.

• The first mass-produced embedded system was the guidance computer for the
Minuteman-1 missile in 1961.

1.4 CLASSIFICATION OF EMBEDDED SYSTEMS

It is possible to have a multitude of classifications for embedded systems, based on different

criteria. Some of the criteria used in the classification of embedded systems are:
1. Based on generation
2. Complexity and performance requirements
3. Based on deterministic behaviour
4. Based on triggering.
The classification based on deterministic system behaviour is applicable for 'Real Time' systems.
The application/task execution behaviour for an embedded system can be cither deterministic or
non- deterministic. Based on the execution behaviour, Real Time embedded systems arc
classified into Hard and Soft. We will discuss about hard and soft real time systems in a later
chapter. Embedded Systems which are 'Reactive' in nature (Like process control systems in
industrial control applications) can be classified based on the trigger. Reactive systems can be
either event triggered or time triggered.

1.4.1 CLASSIFICATION BASED ON GENERATION

This classification is based on the order in which the embedded processing systems evolved from
the first version to where they are today. As per this criterion, embedded systems can be classified
into:

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1.4.1.1 First Generation The early embedded systems were built around 8bit microprocessors
like 8085 and Z80, and 4bit microcontrollers. Simple in hardware circuits with firmware
developed in Assembly code. Digital telephone keypads, stepper motor control units etc. are
examples of this.
1.4.1.2 Second Generation These are embedded systems built around 16bit microprocessors
and 8 or 16 bit microcontrollers, following the first generation embedded systems. The instruction
set for the second generation processors/controllers were much more complex and powerful than
the first generation processors/controllers. Some of the second generation embedded systems
contained embedded operating systems for their operation. Data Acquisition Systems. SCADA
systems, etc. are examples of second generation embedded systems.
1.4.1.3 Third Generation With advances in processor technology, embedded system
developers started making use of powerful 32bit processors and I6bit microcontrollers for their
design. A new concept of application and domain specific processors/controllers like Digital
Signal Processors (DSP) and Application Specific Integrated Circuits (ASICs) came into the
picture. The instruction set of processors became more complex and powerful and the concept of
instruction pipelining also evolved. The processor market was flooded with different types of
processors from different vendors. Processors like Intel Pentium, Motorola 68K, etc, gained
attention in high performance embedded requirements. Dedicated embedded real time and general
purpose operating systems entered into the embedded market. Embedded systems spread its
ground to areas like robotics, media, industrial process control, networking, etc.

1.4.1.4 Fourth Generation The advent of System on Chips (SoC), reconfigurable processors
and multicore processors are bringing high performance, tight integration and miniaturisation into
the em- bedded device market. The SoC technique implements a total system on a chip by
integrating different functionalities with a processor core on an integrated circuit. We will discuss
about SoC’s in a later chapter. The fourth generation embedded systems are making use of high
performance real time embedded operating systems for their functioning. Smart phone devices,
mobile internet devices (MIDs), etc. are examples of fourth generation embedded systems.

1.4.2 CLASSIFICATION BASED ON COMPLEXITY AND PERFORMANCE

This classification is based on the complexity and system performance requirements. According
to this classification, embedded systems can be grouped into:
1.4.2.1 Small-Scale Embedded Systems Embedded systems which arc simple in application
needs and where the performance requirements are not time critical fall under this category. An
electronic toy is a typical example of a small-scale embedded system. Small-scale embedded
systems are usually built around low performance and low cost 8 or 16 bit
microprocessors/microcontrollers. A small-scale embedded system may or may not contain an
operating system for its functioning.

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1.4.2.2 Medium-Scale Embedded Systems Embedded systems which arc slightly complex in
hardware and firmware (software) requirements fall under this category. Medium-scale embedded
systems are usually built around medium performance, low cost 16 or 32 bit
microprocessors/microcontrollers or digital signal processors. They usually contain an embedded
operating system (cither general purpose or real time operating system) for functioning.
1.4.2.3 Large-Scale Embedded Systems/Complex Systems Embedded systems which involve
highly complex hardware and firmware requirements fall under this category. They are employed
in mission critical applications demanding high performance. Such systems are commonly built
around high performance 32 or 64 bit RISC processors/controllers or Reconfigurable System on
Chip (RSoC) or multi-core processors and programmable logic devices. They may contain
multiple processors/controllers and co-units/hardware accelerators for offloading the processing
requirements from the main processor of the system. Decoding/encoding of media, cryptographic
function implementation, etc. are examples for processing requirements which can be
implemented using a co-processor/hardware accelerator. Complex embedded systems usually
contain a high performance Real Time Operating System (RTOS) fur task scheduling,
prioritization and management.

1.5 MAJOR APPLICATION AREAS OF EMBEDDED SYSTEMS

The application areas and the products in the embedded domain arc countless. A few of the
important domains and products are listed below:

1. Consumer electronics: Camcorders, cameras, etc.

2. Household appliances: Television, DVD players, washing machine, fridge, microwave

oven. etc.
3. Home automation and security systems: Air conditioners, sprinklers, intruder detection
alarms, closed circuit television cameras, fire alarms, etc.
4. Automotive industry: Anti-lock breaking systems (ABS), engine control, ignition systems,
automatic navigation systems, etc.
5. Telecom: Cellular telephones, telephone switches, handset multimedia applications, etc.
6. Computer peripherals: Printers, scanners, fax machines, etc.
7. Computer networking systems: Network routers, switches, hubs, firewalls, etc.
8. Healthcare: Different kinds of scanners, EEG, ECG machines etc.
9. Measurement & Instrumentation: Digital multi meters, digital CROs, logic analyzers
PLC systems, etc.
10. Banking & Retail: Automatic teller machines (ATM) and currency counters, point of sales
(POS)
11. Card Readers: Barcode, smart card readers, hand held devices, etc.

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1.6 PURPOSE OF EMBEDDED SYSTEMS

Each embedded system is designed to serve the purpose of any one or a combination of the
following tasks:
1. Data collection/Storage/Representation
2. Data communication
3. Data (signal) processing
4. Monitoring
5. Control
6. Application specific user interface

DATA COLLECTION / STORAGE / REPRESENTATION

• An embedded system designed for the purpose of data collection performs acquisition of
data from the external world. Data collection is usually done for storage, analysis,
manipulation and transmission.
• The term "data" refers all kinds of information, viz. text, voice, image, video, electrical
signals and any other measurable quantities.
• Data can be either analog (continuous) or digital (discrete).
• The collected data may be stored directly in the system or may be transmitted to some
other systems or it may be processed by the system or it may be deleted instantly after
giving a meaningful representation.
• Some embedded systems store the collected data for processing and analysis. Such
systems incorporate a built-in/plug-in storage memory for storing the captured data. Some
of them give the user a meaningful representation of the collected data by visual
(graphical/quantitative) or audible means using display units [Liquid Crystal Display
(LCD), Light Emitting Diode (LED), etc.] buzzers, alarms, etc. Examples are: measuring
instruments with storage memory and monitoring instruments with storage memory used
in medical applications. Certain embedded systems store the data and will not give a
representation of the same to the user, whereas the data is used for internal processing.
• A digital camera is a typical example of an embedded system with data collection/storage/
representation of data. Images are captured and the captured image may be stored within
the memory of the camera. The captured image can also be presented to the user through
a graphic LCD unit.

DATA COMMUNICATION
• Embedded data communication systems are deployed in applications ranging from
complex satellite communication systems to simple home networking systems.
• Embedded Data communication systems are dedicated for data communication
• The data collecting embedded terminal itself can incorporate data communication units

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like wireless modules (Bluetooth, ZigBee, Wi-Fi, EDGE, GPRS, etc.) or wire-line
modules (RS-232C, USB, TCP/IP, PS2, etc.).

DATA (signal) processing

• Embedded systems with Signal processing functionalities are employed in

applications demanding signal processing like Speech coding, synthesis,
audio video codec, transmission applications etc
• A digital hearing aid is a typical example of an embedded system employing
data processing. Digital hearing aid improves the hearing capacity of hearing
impaired persons.

MONITORING

• Embedded systems coming under this category are specifically designed for monitoring
purpose.
• They are used for determining the state of some variables using input sensors
• They cannot impose control over variables.
• Electro Cardiogram (ECG) machine for monitoring the heart beat of a patient is a typical
example for this
• The sensors used in ECG are the different Electrodes connected to the patient’s body
• Measuring instruments like Digital CRO, Digital Multi meter, Logic Analyzer etc used in
Control & Instrumentation applications are also examples of embedded systems for
monitoring purpose
•
CONTROL

• Embedded systems with control functionalities are used for imposing control over some
variables according to the changes in input variables
• Embedded system with control functionality contains both sensors and actuators
• Sensors are connected to the input port for capturing the changes in environmental variable
or measuring variable
• The actuators connected to the output port are controlled according to the changes in input
variable to put an impact on the controlling variable to bring the controlled variable to the
specified range
• Air conditioner for controlling room temperature is a typical example for embedded system
with ‘Control’ functionality
• Air conditioner contains a room temperature sensing element (sensor) which may be a
thermistor and a handheld unit for setting up (feeding) the desired temperature

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• The air compressor unit acts as the actuator. The compressor is controlled according to the
current room temperature and the desired temperature set by the end user

APPLICATION SPECIFIC USER INTERFACE

These are embedded systems with application-specific user interfaces like buttons, switches,
keypad, lights, bells, display units, etc. Mobile phone is an example for this. In mobile phone the
user interface is provided through the keypad, graphic LCD module, system speaker, vibration
alert, etc

'SMART'RUNNING SHOES FROM ADIDAS—THE INNOVATIVE

BONDING OF LIFESTYLE WITH EMBEDDED TECHNOLOGY

• After three years of extensive research work, Adidas launched the "Smart" running shoes
in the market in April 2005.

• The shoe constantly adapts its shock-absorbing characteristics to customize its value to the
individual runner, depending on the running style, pace, body weight, and running surface.
The shoe uses a magnetic sensing system to measure cushioning level, which is adjusted
via a digital signal processing unit that controls a motor-driven cable system.

• A hall effect sensor is positioned at the top of the "cushioning element", and the magnet
is placed at the bottom of the element. As the cushioning compresses on each impact, the
sensor measures the distance from top to bottom of mid-sole (accurate to 0.1 mm).
• About 1000 readings per second are taken and relayed to the shoe's microprocessor. The
Microprocessor (MPU) is positioned under the arch of the shoe. It runs an algorithm that
compares the compression messages received from the sensor to a preset range of proper
cushioning levels, so it understands if the shoe is too soft or too firm. Then the MPU sends
a command to a micro motor, housed in the mid-foot. The micro motor turns a lead screw
to lengthen or shorten a cable secured to the walls of a plastic-cushioning element. When
the cable is shortened, the cushioning element is pulled taut and compresses very little. A
longer cable allows for a more cushioned feel. A replaceable 3V battery powers the motor
and lasts for about 100 hours of running.

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The Typical Embedded System

FPGA/ASIC/DSP/SoC
Microprocessor/controller Embedded
Firmware

Memory

Communication Interface

System
I/p Ports Core O/p Ports
(Sensors)
(Actuators)

Other supporting
Integrated Circuits &
subsystems

Embedded System

Real World

Fig: Elements of an Embedded System

A typical embedded system contains a single chip controller, which acts as the master brain
of the system. The controller can be a Microprocessor (e.g. Intel 8085) or a microcontroller (e.g.
Atmel AT89C51) or a Field Programmable Gate Array (FPGA) device (e.g. Xilinx Spartan) or a
Digital Signal Processor (DSP) (e.g. Blackfin® Processors from Analog Devices) or an
Application Specific

Integrated Circuit (ASIC)/Application Specific Standard Product (ASSP) (e.g. ADE7760

Single Phase Energy Metering IC from) Analog Devices for energy metering applications).

Embedded hardware/software systems are basically designed to regulate a physical

variable or to manipulate the state of some devices by sending some control signals to the Actuators
or devices connected to the O/p ports of the system, in response to the input signals provided by
the end users or Sensors which are connected to the input ports. Hence an embedded system can
be viewed as a reactive system. The control is achieved by processing the information coming

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from the sensors and user interfaces, and controlling some actuators that regulate the physical
variable.

Key boards, push button switches, etc. are examples for common user interface input
devices whereas LEDs, liquid crystal displays, piezoelectric buzzers, etc. are examples for
common user interface output devices for a typical embedded system.

The Memory of the system is responsible for holding the control algorithm and other important
configuration details. For most of embedded systems, the memory for storing the algorithm or
configuration data is of fixed type, which is a kind of Read Only Memory (ROM).The most
common types of memories used in embedded systems for control algorithm storage are OTP,
PROM, UVEPROM, EEPROM and FLASH. Depending on the control application, the memory
size may vary from a few bytes to megabytes. Sometimes the system requires temporary memory
for performing arithmetic operations or control algorithm execution and this type of memory is
known as “working memory”. Random Access Memory (RAM) is used in most of the systems as
the working memory. Various types of RAM like SRAM, DRAM and NVRAM are used for this
purpose. The size of the RAM also varies from a few bytes to kilobytes or megabytes depending
on the application.

CORE OF THE EMBEDDED SYSTEM

Embedded systems are domain and application specific and are built around a central core.
The core of the embedded system falls into any one of the following categories:

1. General Purpose and Domain Specific Processor

1.1 Microprocessors
1.2 Microcontrollers
1.3 Digital Signal Processors
2. Application Specific Integrated Circuits (ASICs)

3. Programmable Logic Devices (PLDs)

4. Commercial off-the-shelf Components (COTS)

1. General Purpose and Domain Specific Processors

Almost 80% of the embedded systems are processor/controller based. The processor may
be a microprocessor or a microcontroller or a digital signal processor, depending on the domain
and application Most of the embedded systems in the industrial control and monitoring
applications make use of the commonly available microprocessors or microcontrollers whereas
domains which require signal processing such as speech coding, speech recognition, etc. make use

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of special kind of digital signal processors supplied by manufacturers like, Analog Devices, Texas
Instruments, etc.

Microprocessors

✓ The CPU contains the Arithmetic and Logic Unit (ALU), Control Unit and Working
registers

✓ Microprocessor is a dependent unit and it requires the combination of other hardware like
Memory, Timer Unit, and Interrupt Controller etc for proper functioning.

✓ Intel claims the credit for developing the first Microprocessor unit Intel 4004, a 4 bit
processor which was released in Nov 1971

General Purpose Processor (GPP) vs. Application-Specific Instruction Set Processor

(ASIP)

✓ General Purpose Processor or GPP is a processor designed for general computational tasks

✓ GPPs are produced in large volumes and targeting the general market. Due to the high
volume production, the per unit cost for a chip is low compared to ASIC or other specific
ICs

✓ A typical general purpose processor contains an Arithmetic and Logic Unit (ALU) and
Control Unit (CU)

✓ Application Specific Instruction Set processors (ASIPs) are processors with architecture
and instruction set optimized to specific domain/application requirements like Network
processing, Automotive, Telecom, media applications, digital signal processing, control
applications etc.

Microcontrollers

✓ A highly integrated silicon chip containing a CPU, scratch pad RAM, Special and General
purpose Register Arrays, On Chip ROM/FLASH memory for program storage, Timer and
Interrupt control units and dedicated I/O ports

✓ Microcontrollers can be considered as a super set of Microprocessors

✓ Microcontroller can be general purpose (like Intel 8051, designed for generic applications
and domains) or application specific (automotive applications)

✓ Since a microcontroller contains all the necessary functional blocks for independent
working, they found greater place in the embedded domain in place of microprocessors

✓ Microcontrollers are cheap, cost effective and are readily available in the market

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✓ Texas Instruments TMS 1000 is considered as the world’s first microcontroller

Microprocessor vs Microcontroller

The following table summarizes the differences between a microcontroller and microprocessor.

Microprocessor Microcontroller
A silicon chip representing a Central A microcontroller is a highly integrated chip
Processing Unit (CPU), which is capable of that contains a CPU, scratch pad RAM, Special
performing arithmetic as well as logical and General purpose Register Arrays, On Chip
operations according to a pre-defined set of ROM/FLASH memory for program storage,
Instructions Timer and Interrupt control units and dedicated
I/O ports
It is a dependent unit. It requires the It is a self-contained unit and it doesn’t require
combination of other chips like Timers, external Interrupt Controller, Timer, UART
Program and data memory chips, Interrupt etc. for its functioning
controllers etc. for functioning

Most of the time general purpose in design Mostly application oriented or domain specific
and operation

Doesn’t contain a built in I/O port. The I/O Most of the processors contain multiple built-
Port functionality needs to be implemented in I/O ports which can be operated as a single
with the help of external Programmable 8 or 16 or 32 bit Port or as individual port pins
Peripheral Interface Chips like 8255

Targeted for high end market where Targeted for embedded market where
performance is important performance is not so critical (At present this
demarcation is invalid)
Limited power saving options compared to Includes lot of power saving features
microcontrollers

RISC vs. CISC Processors/Controllers

The term RISC stands for Reduced Instruction Set Computing. As the name implies, all
RISC processors/controllers possess lesser number of instructions, typically in the range of 30 to
40. CISC stands for Complex Instruction Set Computing. From the definition itself it is clear that
the instruction set is complex and instructions are high in number. From a programmers point of
View RISC processors are comfortable since s/he needs to learn only a few instructions, whereas
for a CISC processor s/he needs to learn more number of instructions and should understand the
context of usage of each instruction (This scenario is explained on the basis of a programmer

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following Assembly Language coding. For a programmer following C coding it doesn’t matter
since the cross-compiler is responsible for the conversion of the high level language instructions
to machine dependent code). Atmel AVR microcontroller is an example for a RISC processorand
its instruction set contain only 32 instructions. The original version of 8051 microcontroller (e.g.
AT89C51) is a CISC controller and its instruction set contains 255 instructions. There are some
other factors like pipelining features, instruction set type, etc. for determining the RISC/CISC
criteria. Some of the important criteria are listed below:

RISC CISC
Lesser number of instruction Greater number of Instruction
Instruction pipelining and increased execution
Generally no instruction pipelining feature
speed
Non-orthogonal instruction set (All
Orthogonal instruction set (Allows each
instructions are not allowed to operate on any
instruction to operate on any register and use
register and use any addressing mode. It is
any addressing mode)
instruction-specific)
Operations are performed on registers only, Operations are performed on registers or
the only memory operations are load and memorydepending on the instruction
store
A large number of registers are available Limited number of general purpose registers
Instructions are like macros in C language.
Aprogrammer can achieve the desired
Programmer needs to write more code to
functionality with a single instruction which
execute a task since the instructions are
in tum provides the effect of using more
simpler ones
simpler single instructions in RISC

Single, fixed length instructions Variable length instructions

More silicon usage since more additional
Less silicon usage and pin count decoder logic is required to implement the
complex instruction decoding.
Can be Harvard or Von-Neumann
With Harvard Architecture
Architecture

Harvard vs. Von-Neumann Processor/Controller Architecture

The terms Harvard and Von-Neumann refers to the processor architecture design.
Microprocessors/controllers based on the Von-Neumann architecture shares a single common bus
for fetching both instructions and data. Program instructions and data are stored in a common main
memory. Von-Neumann architecture based processors/controllers first fetch an instruction and
then fetch the data to support the instruction from code memory. The two separate fetches slows

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down the controller‘s operation. Von-Neumann architecture is also referred as Princeton

architecture, since it was developed by the Princeton University.

I/O CPU Memory

Program
CPU Data Memory
Memory

Single shared Bus

Von-Neumann Architecture Harvard Architecture

Microprocessors/controllers based on the Harvard architecture will have separate data bus
and instruction bus. This allows the data transfer and program fetching to occur simultaneously on
both buses. With Harvard architecture. The data memory can be read and written while the
program memory is being accessed. These separated data memory and code memory buses allow
one instruction to execute while the next instruction is fetched (“pre-fetching”).

The pre-fetch theoretically allows much faster execution than Von-Neumann architecture.
Since some additional hardware logic is required for the generation of control signals for this type
of operation it adds silicon complexity to the system. Figure explains the Harvard and Von-
Neumann architecture concept.

The following table highlights the differences between Harvard and Von-Neumann architecture.

Harvard Architecture Von-Neumann Architecture

Separate buses for instruction and data fetching Single shared bus for instruction and data
fetching
Easier to pipeline, so high performance can be Low performance compared to Harvard
achieved architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self-modifying codes

Since data memory and program memory are Since data memory and program memory
stored physically in different locations, no are stored physically in the same chip,
chances for accidental corruption of program chances for accidental corruption of
memory program memory

Big-Endian vs. Little-Endian Processors/Controllers

Endianness specifies the order in which the data is stored in the memory by processor
operations in a multi byte system (Processorswhose word size is greater than one byte). Suppose
the word length is two byte then data can be stored in memory in two different ways:

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1. Higher order of data byte at the higher memory and lower order of data byte at location just
below the higher memory.

2. Lower order of data byte at the higher memory and higher order of data byte at location just
below the higher memory.

Little-endian means the lower-order byte of the data is stored in memory at the lowest
address, and the higher-order byte at the highest address. (The little end comes first.) For example,
a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as shown below:

Base Address + 0 Byte 0 Byte 0 0x20000 (Base Address)

Base Address + 1 Byte 1 Byte 1 0x20001 (Base Address + 1)

Base Address + 2 Byte 2 Byte 2 0x20002 (Base Address + 2)

Base Address + 3 Byte 3 Byte 3 0x20003 (Base Address + 3)

Little-endian Operation

Base Address + 0 Byte 3 Byte 3 0x20000 (Base Address)

Base Address + 1 Byte 2 Byte 2 0x20001 (Base Address + 1)

Base Address + 2 Byte 1 Byte 1 0x20002 (Base Address + 2)

Base Address + 3 Byte 0 Byte 0 0x20003 (Base Address + 3)

Big-endian Operation

Load Store Operation and Instruction Pipelining

As mentioned earlier, the RISC processor instruction set is orthogonal, meaning it operates
on registers. The memory access related operations are. Performed by the special instructions load
and store. If the operand is specified as memory location, the content of it is loaded to a register
using the load instruction. The instruction store stores data from a specified register to a specified
memory location. The concept of Load Store Architecture is illustrated with the following
example:

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R1 R2 R3
1 3 3 1
load R1, x
load R2, y 2
x 00 add R3, R1, R2 3
y 7F ALU 3
store R3, z 4
z 23

4
Load Store Operation

Suppose x, y and z are memory locations and we want to add the contents of x and y and
store the result in location 2. Under the load store architecture the same is achieved with 4
instructions as shown in Figure.

The first instruction load R. X loads the register R1 with the content of memory location x,
the second instruction load R2, y loads the register R2 with the content of memory location y. The
instruction add R3. R1, R2 adds the content of registers R1 and R2 and stores the result in register
R3. The next instruction store R3.z stones the content of register R3 in memory location z.

The conventional instruction execution by the processor follows the fetch-decode-execute

sequence. Where the ‘fetch’ part fetches the instruction from program memory or code memory
and the decode part decodes the instruction to generate the necessary control signals. The execute
stage reads the operands, perform ALU operations and stores the result. In conventional program
execution, the fetch and decode operations are performed in sequence. For simplicity let’s consider
decode and execution together. During the decode operation the memory address bus is available
and if it is possible to effectively utilize it for an instruction fetch, the processing speed can be
increased. In its simplest form instruction Pipelining refers to the overlapped execution of
instruction. Under normal program execution how it is meaningful to fetch the next instruction to
execute, while decoding and execution of the current instruction is in progress.

Depending on the stages involved in an instruction (fetch, read register and decode. execute
instruction, access an operand in data memory, write back the result to register, etc.), there can be
multiple levels of instruction pipelining. Figure illustrates the concept of Instruction pipelining for
single stage pipelining.

Clock Pulses Clock Pulses Clock Pulses

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Machine Cycle 1 Machine Cycle 2 Machine Cycle 3
Fetch (PC)
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The Single stage pipelining concept

Application Specific Integrated Circuits (ASICs)

• Application Specific Integrated Circuit (ASIC) is a microchip designed to perform a

specific or unique application. It is used as replacement to conventional general purpose
logic chips.
• It integrates several functions into a single chip and there by reduces the system
development cost.
• As a single chip, ASIC consumes a very small area in the total system and there by helps
in the design of smaller systems with high capabilities/functionalities.
• ASICs can be pre-fabricated for a special application or it can be custom fabricated by
using the components from a re-usable ‘building block’ library of components for a
particular customer application.
• ASIC based systems are profitable only for large volume commercial productions.
Fabrication of ASICs requires a non-refundable initial investment for the process
technology and configuration expenses. This investment is known as Non-Recurring
Engineering Charge (NRE) and it is a one-time investment.
• If the Non-Recurring Engineering Charges (NRE) is borne by a third party and the
Application Specific Integrated Circuit (ASIC) is made openly available in the market, the
ASIC is referred as Application Specific Standard Product (ASSP).

Programmable Logic Devices

• Logic devices provide specific functions, including device-to-device interfacing, data

communication, signal processing, data display, timing and control operations, and almost
every other function a system must perform.
• Logic devices can be classified into two broad categories fixed and programmable. As the
name indicates, the circuits in a fixed logic device are permanent, they perform one
function or set of functions-once manufactured, they cannot be changed.

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• On the other hand, Programmable Logic Devices (PLDs) offer customers a wide range of
logic capacity, features, speed, and voltage characteristics-and these devices can be re-
configured to perform any number of functions at any time.

Advantages of PLD:

Programmable logic devices offer a number of important advantages over fixed logic devices,
including:

➢ PLDs offer customers much more flexibility during the design cycle because design
iterations are simply a matter of changing the programming file, and the results of design
changes can be seen immediately in working parts.
➢ PLDs do not require long lead times for prototypes or production parts-the PLDs are
already on a distributor’s shelf and ready for shipment.
➢ PLDs do not require customers to pay for large NRE costs and purchase expensive mask
sets+PLD suppliers incur those costs when they design their programmable devices and
are able to amortize those costs over the multi-year lifespan of a given line of PLDs.
➢ PLDs allow customers to order just the number of parts they need, when they need them,
allowing them to control inventory! Customers who use fixed logic devices often end up
with excess inventory which must be scrapped, or if demand for their product surges, they
may be caught short of parts and face production delays.
➢ PLDs can be reprogrammed even after a piece of equipment is shipped to a customer In
fact, thanks to programmable log1c devices, a number of equipment manufacturers now
tout the ability to add new features or upgrade products that already are in the field. To do
this, they simply upload a new programming file to the PLD, via the Internet, creating new
hardware logic in the system.
CPLDS and FPGAs

• The two major types of programmable logic devices are Field Programmable Gate Arrays
(FPGAS) and Complex Programmable Logic Devices (CPLDS).
• Of the two, FPGAS offer the highest amount of logic density, the most features, and the
highest performance.
• The largest FPGA now shipping, part of the Xilinx VirtexTM line of devices, provides eight
million “system gates” (the relative density of logic). These advanced devices also offer
features such as built-in hardwired processors (such as the IBM power PC), substantial
amounts of memory, clock management systems, and support for many of the latest, very
fast device-to-device signaling technologies.
• FPGAs are used in a wide variety of applications ranging from data processing and storage,
to instrumentation, telecommunications, and digital signal processing.
• CPLDs, by contrast, offer much smaller amounts of logic-up to about 10, 000 gates But
CPLDs offer very predictable timing characteristics and are therefore ideal or critical
control application CPLDs such as Xilinx CoolRunnerTM series also require extremely low

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amounts of power and are very inexpensive, making them ideal for cost-sensitive, battery-
operated, portable applications such as mobile phones and digital handheld assistants.

Commercial Off-the-Shelf Components (COTS)

• A Commercial Off-the-Shelf (COTS) product is one which is used ‘as-is’.

• COTS products are designed in such a way to provide easy integration and interoperability
with existing system components.
• The COTS component itself may be developed around a general purpose or domain
specific processor or an Application Specific Integrated circuit or a programmable logic
device.
• Typical examples of COTS hardware unit are remote controlled toy car control units
including the circuitry part, high performance, high frequency microwave electronics (2-
200 GHz), high bandwidth analog-to-digital converters, devices and components for
operation at very high temperatures, electro-optic IR imaging arrays, UV/IR detectors, etc.
The major advantage of using COTS is that they are readily available in the market, are
cheap and adeveloper can cut down his/her development time to a great extent. This in turn
reduces the time to market your embedded systems.”
• The TCP/IP plug-in module available from various 1% manufactures like ‘WIZnet’,
‘Freescale’, ‘Dynalog’, etc. \é;., are very good examples of COTS product. The major
drawback of using COTS components in embedded design is that the manufacturer of the
COTS component may withdraw the product or discontinue the production of the COTS
at any time if a rapid change in technology occurs, and this will adversely affect a
commercial manufacturer of the embedded system which makes use of the specific COTS
product.

2.2 MEMORY

Memory is an important part of a processor/controller based embedded systems. Some of the

processors/controllers contain built in memory and this memory is referred as on-chip memory.
Others do not contain any memory inside the chip and requires external memory to be connected
with the controller/processor to store the control algorithm. It is called off-chip memory.

2.2.1 Program Storage Memory (ROM)

The program memory or code storage of an embedded system stores the program instructions
and it can be classified into different types as per the block diagram representation given in Fig.

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FLASH Code Memory NVRAM

(ROM)

PROM Masked ROM

EPROM EEPROM
(OTP) (MROM)

Classification of Program Memory (ROM)

The code memory retains its contents even after the power to it is turned off. It is generally
known as non-volatile storage memory. Depending on the fabrication, erasing and programming
techniques they are classified into the following types.

1.Masked ROM (MROM)

• Masked ROM is a one-time programmable device.

• Masked ROM makes use of the hardwired technology for storing data.
• The device is factory programmed by masking and metallization process at the time of
production itself, according to the data provided by the end user.
• The primary advantage of this is low cost for high volume production. They are the least
expensive type of solid state memory.
• Different mechanisms are used for the masking process of the ROM, like:

1. Creation of an enhancement or depletion mode transistor through channel implant.

2. By creating the memory cell either using a standard transistor or a high threshold transistor.
In the high threshold mode, the supply voltage required to turn ON the transistor is above the
normal ROM IC operating voltage. This ensures that the transistor is always off and the memory
cell stores always logic0.

2. Programmable Read Only Memory (PROM) / (OTP)

• Unlike Masked ROM Memory, One Time Programmable Memory (OTP) or PROM is not
pre-programmed by the manufacturer. The end user is responsible for programming these
devices.
• This memory has nichrome or polysilicon wires arranged in a matrix. These wires can be
functionally viewed as fuses.

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• It is programmed by a PROM programmer which selectively bums the fuses according to

the bit pattern to be stored. Fuses which are not blown/burned represents a logic “1”
whereas fuses which are blown/burned represents a logic “0”. The default state is logic “1”.
• OTPs cannot be reprogrammed.

3.Erasable Programmable Read Only Memory (EPROM)

• Erasable Programmable Read Only Memory (EPROM) gives the flexibility to re-program
the same chip. EPROM stores the bit information by charging the floating gate of an FET.
• Bit information is stored using an EPROM programmer, which applies high voltage to
charge the floating gate.
• EPROM contains a quartz crystal window for erasing the stored information. If the window
is exposed to ultraviolet rays for a fixed duration, the entire memory will be erased.
• Even though the EPROM chip is flexible in terms of re-programmability, it needs to be
taken out of the circuit board and put in a UV eraser device for 20 to 30 minutes. So it is a
tedious and time-consuming process.

4. Electrically Erasable Programmable Read Only Memory (EEPROM)

• As the name indicates, the information contained in the EEPROM memory can be altered
by using electrical signals at the register/Byte level. They can be erased and reprogrammed
in-circuit.
• These chips include a chip erase mode and in this mode they can be erased in a few
milliseconds. It provides greater flexibility for system design.
• The only limitation is their capacity is limited when compared with the standard R019 (A
few kilobytes).

5. FLASH

• FLASH is the latest ROM technology and is the most popular ROM technology used in
today’s embedded designs.
• It combines the re-programmability of EEPROM and the high capacity of standard ROM.
• FLASH memory is organized as sectors (blocks) or pages. FLASH memory stores
information in an array of floating gate MOSFET transistors.
• The erasing of memory can be done at sector level or page level without affecting the other
sectors or pages. Each sector/page should be erased before re-programming.

6. NVRAM

• Non-volatile RAM is a random access memory with battery backup.

• It contains static RAM based memory and a minute battery for providing supply to the
memory in the absence of external power supply.
• The memory and battery are packed together in a single package.
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• The life span of NVRAM is expected to be around 10 years”) DS-644 from Maxim/Dallas
is an example of 32KB NVRAM.

2.2.2 Read-Write Memory/ Random Access Memory (RAM)

• RAM is the data memory or working memory of the controller/processor.

• Controller/processor can read from it and write to it.
• RAM is volatile, meaning when the power is turned off, all the contents are destroyed.
RAM is a direct access memory, meaning we can access the desired memory location,
directly without the need for traversing through the entire memory locations to reach the
desired memory position) (i.e. random access of memory location).
• RAM generally falls into three categories: Static RAM (SRAM), dynamic RAM (DRAM)
and non-volatile RAM (NVRAM).

Read/Write
Memory (RAM)

SRAM DRAM NVRAM

Classification of working memory (RAM)

1.Static RAM (SRAM)

• Static RAM stores data in the form of voltage. They are made up of flip-flops.
• Static RAM is the fastest form of RAM available.
• In typical implementation, an SRAM cell (bit) is realized using six transistors (or 6
MOSFETs). Four of the transistors are used for building the Latch (fIip-flop) part of the
memory cell and two for controlling the access.
• SRAM is fast in operation due to its resistive networking and switching capabilities. In its
simplest representation and SRAM cell can be visualized as shown in Fig:

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Bit Line B\ Bit Line B

Q1 Q3

Q5 Q6

Q2 Q4
Vcc

Word Line

SRAM cell implementation

• This implementation in its simpler form can be Visualized as two cross coupled inverters
with read/ write control through transistors. The four transistors in the middle form the
cross-coupled inverters. This can be visualized as shown in Fig.
• From the SRAM implementation diagram, it is clear that access to the memory cell is
controlled by the line Word Line, which controls the access transistors (MOSFETS) Q5
and Q6. The access transistors control the connection to bit lines B & B\. In order to write
a value to the memory cell, apply the desired value to the bit control lines (For writing
1, make B = 1 and B =0; for writing 0, make B = 0 and B\ =1) and assert the Word Line
(Make Word line high). This operation latches the bit written in the dip-hop. For reading
the content of the memory cell, assert both 8 and B\ bit lines to l and set the Word line to
1.
• The major limitations of SRAM are low capacity and high cost. Since a minimum of six
transistors are required to build a single memory cell, imagine how many memory cells we
can fabricate on a silicon wafer.

2.Dynamic RAM(DRAM)

• Dynamic RAM stores data in the form of charge. They are made up of MOS transistor
gates.
• The advantages of DRAM are its high density and low cost compared to SRAM. The
disadvantage is that since the information is stored as charge it gets leaked off with time
and to prevent this they need to be refreshed periodically. Special Circuits called DRAM
controllers are used for the refreshing operation. The refresh operation is done periodically
in milli-seconds interval.

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• Figure illustrates the typical implementation of a DRAM cell.

Bit Line B

Word Line

+
-

• The MOSFET acts as the gate for the incoming and outgoing data whereas the capacitor
acts as the bit storage unit.
• Table given below summarizes the relative merits and demerits of SRAM and DRAM
technology.

SRAM Cell DRAM Cell

Made up of 6 CMOS transistors Made up of a MOSFET and a capacitor
(MOSFET)
Doesn’t Require refreshing Requires refreshing

Low capacity (Less dense) High Capacity (Highly dense)

More expensive Less Expensive

Fast in operation. Typical access Slow in operation due to refresh requirements.

time is 10ns Typical access time is 60ns. Write operation is
faster than read operation.

3.NVRAM

• Non-volatile RAM is a random access memory with battery backup.

• It contains static RAM based memory and a minute battery for providing supply to the
memory in the absence of external power supply. The memory and battery are packed
together in a single package.
• NVRAM is used for the non-volatile storage of results of operations or for setting up of
flags, etc.

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• The life span of NVRAM is expected to be around 10 years. DSl744 from Maxim/Dallas
is an example for 32KB NVRAM.

2.3 SENSORS AND ACTUATORS

2.3.1 Sensors
Sensor is a transducer device that converts energy from one farm to another for any
measurement or control purpose.
Sensors acts as an input device
Example: sensor which measures the distance between the cushion and magnet in the
smart running shoe is a magnetic Hall Effect sensor.

2.3.2 Actuators
• Actuator is a form of transducer device (mechanical or electrical) which converts signals
to corresponding physical action (motion).
• Actuator acts as an output device.
• Example: Looking back to the “Smart” running shoe example, we can see that the actuator
used for adjusting the position of the cushioning element is a micro stepper motor.

2.3.3 The I/0 Subsystem

I/0 subsystem of the embedded system facilitates the interaction of the embedded system with the
external world.

2.3.3.1 Light Emitting Diode (LED)

• Light Emitting Diode (LED) is an important output device for visual indication in any
embedded system.
• LED can be used as an indicator for the status of various signal or situations. Typical
examples are indicating the presence of power conditions like ‘Device ON’ Battery low’
or ‘Charging of battery’ for a battery operated hand held embedded devices.
• Light Emitting Diode is a pn junction diode and it contains an anode and a cathode. For
proper functioning of the LED, the anode of it should be connected to +ve terminal of the
supply voltage and cathode to the -ve terminal of supply voltage.
• The current flowing through the LED must be limited to a value below the maximum
current that it can conduct.
• A resister is used in series between the power supply and the LED to limit the current
through the LED. The ideal LED interfacing circuit is shown in Figure.

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Vcc

R
GND

2.3.3.2 7-Segment LED Display

• The 7 – segment LED display is an output device for displaying alpha numeric
characters
• It contains 8 light-emitting diode (LED) segments arranged in a special form. Out
of the 8 LED segments, 7 are used for displaying alpha numeric characters and 1 is
used for representing decimal point.
• The LED segments are named A to G and the decimal point LED segment is named
as DP
• The LED Segments A to G and DP should be lit accordingly to display numbers and
characters
• The 7 – segment LED displays are available in two different configurations, namely;
Common anode and Common cathode
• In the Common anode configuration, the anodes of the 8 segments are connected
commonly whereas in the Common cathode configuration, the 8 LED segments
share a common cathode line
• Based on the configuration of the 7 – segment LED unit, the LED segment anode or
cathode is connected to the Port of the processor/controller in the order ‘A’ segment
to the Least significant port Pin and DP segment to the most significant Port Pin.
• The current flow through each of the LED segments should be limited to the
maximum value supported by the LED display unit
• The typical value for the current falls within the range of 20mA
• The current through each segment can be limited by connecting a current limiting
resistor to the anode or cathode of each segment

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Anode Common Cathode LED Display

DP G F E D C B A

DP G F E D C B A
Common Anode LED Display Cathode

Fig.2.15 common anode and cathode configurations of a 7-segment LED Display

2.3.3.3 Opto-coupler

• Opto-coupler is a solid state device to isolate two parts of a circuit. Optocoupler combines
an LED and a photo-transistor in a single housing (package).
• In electronic circuits, an Optocoupler is used for suppressing interference in data
communication, circuit isolation, high voltage separation, simultaneous separation and
signal intensification, etc.
• Optocouplers can be used in either input circuits or in output circuits. Figure illustrates the
usage of optocoupler in input circuit and output circuit of an embedded system with a
micro-controller as the system core. Optocoupler is available as IC from different
semiconductor manufacturers. The MCT2M IC from Fair child semiconductor is an
example for optocoupler IC.
• Figure Optocoupler device illustrates the functioning of an Optocoupler device.
Vcc

LED AT89C51 LED

I/p interface Port Pin
O/p interface
Port Pin
Photo-transistor Photo-transistor

Opto-Coupler Microcontroller Opto-Coupler

IC MCT2M IC MCT2M

Opto-coupler in Input and Output circuit

1.3.3.5 Relay
• Relay is an electro-mechanical device. In embedded application, the ‘Relay’ unit acts as
dynamic path selectors for signals and power. The ‘Relay’ unit contains a relay coil made
up of insulated wire on a metal core and 3 metal armature with one or more contacts.
• ‘Relay’ works on electromagnetic principle. When a voltage is applied to the relay coil,
current flows through the coil, which in turn generates a magnetic field. The magnetic field
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attracts the armature core and moves the contact point. The movement of the contact point
changes the power/signal flow path. ‘Relays’ are available in different configurations.
• Figure given below illustrates the widely used relay configurations for embedded
applications.

Relay Coil
Relay Coil

Relay Coil
Single Pole Single Single Pole Single Single Pole Double
Throw Normally Throw Normally Throw
Open Closed

Relay configuration
• The Single Pole Single Throw configuration has only one path for information flow. The
path is either open or closed in normal condition.
• For normally Open Single Pole Single Throw relay, the circuit is normally open and it
becomes closed when the relay is energized.
• For normally closed Single Pole Single Throw configuration, the circuit is normally closed
and it becomes open when the relay is energized.
• For Single Pole Double Throw Relay, there are two paths for information how and they are
selected by energizing or de-energizing the relay.
• The Relay is normally controlled using a relay driver circuit connected to the port pin of
the processor/controller. A transistor is used for building the relay driver circuit. Figure
illustrates the same.

Vcc
Freewheeling Diode

Relay Coil

Load
Port Pin

Relay Unit

• A free-wheeling diode is used for free-wheeling the voltage produced in the opposite
direction when the relay coil is de-energized. The freewheeling diode is essential for
protecting the relay and the transistor.

2. 3.6 Piezo Buzzer

• Piezo buzzer is a piezoelectric device for generating audio indications in embedded

application.

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• A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible sound

in response to the voltage applied to it.
• Piezoelectric buzzers are available in two types. ‘Self-driving’ and ‘external driving’. The
‘Self-driving’ circuit contains all the necessary components to generate sound at a
predefined tone. It will generate a tone on applying the voltage. External driving
piez0buzzers supports the generation of different tones. The tone can be varied by applying
a variable pulse train to the piezoelectric buzzer.
• A piez0buzzer can be directly interfaced to the port pin of the processor/control. Depending
on the driving current requirements, the piezo0buzzer can also be interfaced using a
transistor based driver circuit as in the case of a ‘Relay’.
1.3.3.6 Push Button Switch
• It is an input device.
• Push button switch comes in two configurations, namely ‘Push to Make’ and ‘Push to
Break’.
• In the ‘Push to Make’ configuration, the switch is normally in the open state and it makes
a circuit contact when it is pushed or pressed.
• In the ‘Push to Break ‘configuration, the switch is normally in the closed state and it breaks
the circuit contact when it is pushed or pressed.
• The push button stays in the ‘closed’ (For Push to Make type) or ‘open’ (For Push to Break
type) state as long as it is kept in the pushed state and it breaks/makes the circuit connection
when it is released.
• The Push button is normally connected to the port pin of the host processor/controller.
Depending on the way in which the push button interfaced to the controller, it can generate
either a ‘HIGH’ pulse or a ‘LOW’ pulse.
• Figure illustrates how the push button can be used for generating ‘LOW’ and ‘HIGH’
pulses.

2.4 COMMUNICATION INTERFACE

✓ Communication interface is essential for communicating with various subsystems of the
embedded system and with the external world

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✓ For an embedded product, the communication interface can be viewed in two different
perspectives; namely;
1.Device/board level communication interface (Onboard Communication Interface)
2.Product level communication interface (External Communication Interface)

✓ Embedded product is a combination of different types of components (chips/devices)

arranged on a Printed Circuit Board (PCB). The communication channel which
interconnects the various components within an embedded product is referred as
Device/board level communication interface (Onboard Communication Interface)

✓ Serial interfaces like I2C, SPI, UART, 1-Wire etc and Parallel bus interface are
examples of ‘Onboard Communication Interface’

✓ The ‘Product level communication interface’ (External Communication Interface) is

responsible for data transfer between the embedded system and other devices or modules

✓ The external communication interface can be either wired media or wireless media and it
can be a serial or parallel interface. Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi),
Radio Frequency waves (RF), GPRS etc are examples for wireless communication
interface

✓ RS-232C/RS-422/RS 485, USB, Ethernet (TCP-IP), IEEE 1394 port, Parallel port, CF-II
Slot, SDIO, PCMCIA etc are examples for wired interfaces.

2.4.1 On-board Communication Interfaces

On-board Communication Interface refers to the different communication channels/buses

for interconnecting the various integrated circuits and other peripherals within the embedded
system. The following section gives an overview of the various interfaces for on-board
communication.

2.4.1.1 Inter Integrated Circuit (12C) Bus

• The Inter Integrated Circuit Bus (I2C-Pronounced ‘I square C‘) is a synchronous bi-
directional half duplex (one-directional communication at a given point of time) two wire
serial interface bus.
• The concept of I2C bus was developed by ‘Philips semiconductors’ in the early 1980s.
• The original intention of I2C was to provide an easy way of connection between a
microprocessor/micr0controller system and the peripheral chips in television sets.
• The I2C bus comprise of two bus lines. Namely; Serial Clock SCL and Serial Data SDA.
• SCL line is responsible for generating synchronization clock pulses and SDA is responsible
for transmitting the serial data across devices.

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• I2C bus is a shared bus system to which many number of I2C devices can be connected.
Devices connected to the I2C bus can act as either 'Master’ device or ‘Slave’ device.
• The ‘Master' device is responsible for controlling the communication by
initiating/terminating data transfer. Sending data and generating necessary synchronization
clock pulses.
• ‘Slave’ devices wait for the commands from the master and respond upon receiving the
command, ‘Master’ and ‘Slave’ devices can act as either transmitter or receiver. Regardless
whether a master is acting as transmitter or receiver, the synchronization clock signal is
generated by the ‘Master’ device only.
• I2C supports multi masters on the same bus.
• The following bus interface diagram shown in Fig. illustrates the connection of master and
slave devices on the I2C bus.

SCL SDA Vcc

2.2K

SDA
2.2K
Port Pins SCL
Slave 1
SCL I2C Device
Master SDA (Eg: Serial
(Microprocessor/ EEPROM)
Controller)

SCL Slave 2
SDA I2C Device

I2C Bus

I2C Bus Interfacing

• The I2C bus interface is built around an input buffer and an open drain or collector
transistor. When the bus is in the idle state, the open drain/collector transistor will be in the
floating state and the output lines (SDA and SCL) switch to the ‘High Impedance’ state.
For proper operation of the bus, both the bus lines should be pulled to the supply voltage
(+5V for TTL family and +3.3V for CMOS family devices) using pull-up resistors. The
typical value of resistors used in pull-up is 2.2K. With pull-up resistors, the output lines of
the bus in the idle state will be ‘HIGH’.

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• The address of a 12C device is assigned by hardwiring the address lines of the device to
the desired logic level. The address to various I2C devices in an embedded device is
assigned and hardwired at the time of designing the embedded hardware.
• The sequence of operations for communicating with a I2C slave device is listed below:

1. The master device pulls the clock line (SCL) of the bus to ‘HIGH’

2. The master device pulls the data line (SDA) ‘LOW’, when the SCL line is at logic ‘HIGH’ (This
is the ‘Start’ condition for data transfer)

3. The master device sends the address (7 bit or 10 bit wide) of the ‘slave’ device to which it wants
to communicate, over the SDA line. Clock pulses are generated at the SCL line for synchronizing
the bit reception by the slave device. The MSB of the data is always transmitted first. The data in
the bus is valid during the ‘HIGH’ period of the clock signal

4. The master device sends the Read or Write bit (Bit value = 1 Read operation; Bit value 0 Write
Operation) according to the requirement.

5. The master device waits for the acknowledgement bit from the slave device whose address is
sent on the bus along with the Read/Write operation command.

6. Slave devices connected to the bus compares the address received with the address assigned to
them 6. The slave device with the address requested by the master device responds by sending an
acknowledge bit (Bit value = 1) over the SDA line.

7. Upon receiving the acknowledge bit, the Master device sends the 8bit data to the slave device
over SDA line, if the requested operation is ‘Write to device‘. If the requested operation is ‘Read
from device', the slave device sends data to the master over the SDA line.

8. The master device waits for the acknowledgement bit from the device upon byte transfer
complete for a write operation and sends an acknowledge bit to the Slave device for a read
operation

9. The master device terminates the transfer by pulling the SDA line ‘HlGI-I’ when the clock line
SCL is at logic ‘HIGH’ (Indicating the ‘STOP’ condition)

• I2C bus supports three different data rates. They are: Standard mode (Data rate up to
100kbits/sec (100 kbps)), Fast mode (Data rate up to 400kbits sec (400 kbps)) and High
Speed mode (Data rate up to 3.4 Mbps). The first generation I2C devices were designed to
support data rates only up to 100kbps. The new generation I2C devices are designed to
operate at data rates up to 3.4Mbits/sec.

2.4.1.2 Serial peripheral Interface (SPI) Bus

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• The Serial Peripheral Interface Bus (SPI) is a synchronous bi-directional full duplex four-
wire serial interface bus. The concept of SPI was introduced by Motorola.
• SPI is a single master multi-slave system. It is possible to have a system where more than
one SPI device can be master, provided the condition only one master device is active at
any given point of time, is satisfied.
• SPI requires four signal lines for communication. They are:

Master Out Slave in (MOSI): Signal line carrying the data from master to slave device. It is also
known as Slave Input/Slave Data in (SI/SD1)

Master in Slave out (MISO): Signal line carrying the data from slave to master device. It is also
known as Slave Output (SO/SDO)

Serial Clock (SCLK): Signal line carrying the clock signals

Slave Select (SS): Signal line for slave device select. It is an active low signal

• The bus interface diagram shown in Figure illustrates the connection of master and slave
devices on the SPI bus.

MOSI SCL MISO

MISO
SCL
MOSI MOSI Slave 1
SCL SPI Device
Master
MISO (Eg: Serial
(Microprocessor/
SS\ EEPROM)
Controller)
SS1\
SS2\
MOSI
Slave 2
SCL
SPI Device
MISO
(Eg: LCD)
SS\

SPI Bus

SPI bus Interfacing

• The master device is responsible for generating the clock signal. It selects the required
slave device by asserting the corresponding slave device’s slave select signal ‘LOW’. The
data out line (MISO) of all the slave devices when not selected floats at high impedance
state.

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• SP1 works on the principle of ‘Shift Register’. The master and slave devices contain a
special shift register for the data to transmit or receive. The size of the shift register is
device dependent. Normally it is a multiple of 8.
• During transmission from the master to slave, the data in the master’s shift register is
shifted out to the M0SI pin and it enters the shift register of the slave device through the
M0SI pin of the slave device. At the same time the shifted out data bit from the slave
device’s shift register enters the shift register of the master device through MISO pin. In
summary, the shift registers of ‘master’ and ‘slave’ devices form a circular buffer. For some
devices, the decision on whether the LS/MS bit of data needs to be sent out first is
configurable through configuration register (e.g. LSBF bit of the SP1 control register for
Motorola’s 68HC12 controller).
• When compared to 12C. SPI bus is most suitable for applications requiring transfer of data
in ‘streams'. The only limitation is SPI doesn’t support an acknowledgement mechanism.

2.4.1.3 Universal Asynchronous Receiver Transmitter (UART)

• Universal Asynchronous Receiver Transmitter (UART) based data transmission is an

asynchronous form of serial data transmission.
• UART based serial data transmission doesn’t require a clock signal to synchronize the
transmitting end and receiving end for transmission. Instead it relies upon the pre-defined
agreement between the transmitting device and receiving device. The serial communication
settings (Baud rate, number of bits per byte. parity, number of start bits and stop bit and
flow control) for both transmitter and receiver should be set as identical.
• The start and stop of communication is indicated through inserting special bits in the data
stream. While sending a byte of data, a start bit is added first and a stop bit is added at the
end of the bit stream. The least significant bit of the data byte follows the ‘start’ bit.
• The ‘start’ bit informs the receiver that a data byte is about to arrive. The receiver device
starts polling its received line’ as per the baud rate settings.
• If parity is enabled for communication, the UART of the transmitting device adds a parity
bit.
• The UART of the receiving device calculates the parity of the bits received and compares
it with the received parity bit for error checking. The UART of the receiving device
discards the ‘Start’, ‘Stop’ and ‘Parity' bit from the received serial bit data to a word.
• For proper communication, the ‘Transmit line’ of the sending device should be connected
to the ‘Receive line’ of the receiving device. Figure illustrates the same.

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TXD TXD
UART UART
RXD RXD

TXD: Transmitter Line

RXD: Receiver Line

• In addition to the serial data transmission function, UART provides hardware handshake
signal support for controlling the serial data now.

2.4.1.4 1–Wire Interface

• 1-wire interface is an asynchronous half-duplex communication protocol developed by

Maxim Dallas Semiconductor. It is also known as Dallas 1-Wire® protocol.
• It makes use of only a single signal line (wire) called DQ for communication and follows
the master-slave communication model.
• One of the key feature of l-wire bus is that it allows power to be sent along the signal wire
as well. The 12C slave devices incorporate internal capacitor (typically of the order of 800
pF) to power the device from the signal line. The l-wire interface supports a Single master
and one or more slave devices on the bus.
• The bus interface diagram shown in Figure illustrates the connection of master and slave
devices on the l-wire bus.

Vcc

4.7K

DQ Slave 1
Port Pin
1-Wire Device
(Eg: DS2760 Battery
GND
monitor IC )
Master
(Microprocessor/
Controller) DQ Slave 2
1-Wire Device
(Eg: DS2431 1024
GND GND
Bit EEPROM )

1-Wire Interface

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• Every l-wire device contains a globally unique 64bit identification number stored within
it. The unique identification number can be used for addressing individual devices present
on the bus in case there are multiple slave devices connected to the 1-wire bus.
• The identifier has three parts: an 8bit family code, a 48bit serial number and anS bit CRC
computed from the first 56 bits.
• The sequence of operation for communicating with a 1-wire slave device is listed below:

1. The master device sends a ‘Reset’ pulse on the l-wire bus.

2. The slave device(s) present on the bus respond with 3 ‘Presence’ pulse.
3. The master device sends a ROM command (Net Address Command followed by the 64bit
address of the device). This addresses the slave device(s) to which it wants to initiate a
communication.
4. The master device sends a read/write function command to read/write the internal memory or
register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device

• All communication over the l-wire bus is master initiated. The communication over the l-
wire bus 3, divided into timeslots of 60 microseconds. The ‘Reset’ pulse occupies 8 time
slots.
• For starting a communication, the master asserts the reset pulse by pulling the 1-wire bus
‘LOW’ for at least 8 time slots ‘slave’ device is present on the bus and is ready for
communication it should respond to the master with a ‘Presence’ pulse, within 60us of the
release of the ‘Reset’ pulse by the master.
• The slave device(s) responds with a ‘Presence’ pulse by pulling the l-wire bus ‘LOW’ for
a minimum of 1 time slot (60448).
• For writing a bit value of 1 on the l-wire bus, the bus master pulls the bus for l to l5 bus
and then releases the bus for the rest of the time slot. A bit value of ‘0’ is written on the
bus by master pulling the bus for a minimum of 1 time slot (60us) and a maximum of 2
time slots.
• To Read a bit from the slave device, the master pulls the bus ‘LOW’ for l to 15us. If the
slave wants to send a bit value ‘1’ in response to the read request from the master, it simply
releases the bus for the rest of the time slot. If the slave wants to send a bit value ‘0’, it
pulls the bus ‘LOW’ for the rest of the time slot.

2.4.1.5 Parallel Interface

• The on-board parallel interface is normal used for communicating with peripheral devices
which are memory mapped to the host of the system.
• The host processor/controller of the embedded system contains a parallel bus and the
device which supports parallel bus can directly connect to this bus system.

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• The communication through the parallel bus is controlled by the control signal interface
between the device and the host.
• The ‘Control Signals’ for communication includes ‘Read/ Write’ signal and device select
signal. The device normally contains a device select line and the device becomes active
only when this line is asserted by the host processor.
• The direction of data transfer (Host to Device or Device to Host) can be controlled through
the control signal lines for ‘Read’ and ‘Write’. Only the host processor has control over the
‘Read’ and ‘Write’ control signals.
• The device is normally memory mapped to the host processor and a range of address is
assigned to it. An address decoder circuit is used for generating the chip select signal for
the device. When the address selected by the processor is within the range assigned for the
device, the decoder circuit activates the chip select line and thereby the device becomes
active.
• The processor then can read or write from or to the device by asserting the corresponding
control line (RD and WR respectively). Strict timing characteristics are followed for
parallel communication. As mentioned earlier, parallel communication is host processor
initiated. If a (device wants to initiate the communication, it can inform the same to the
processor through interrupts. For this, the interrupt line of the device is connected to the
interrupt line of the processor and the core, responding interrupt is enabled in the host
processor. The width of the parallel interbank is determined by the data bus width of the
host processor. It can be 4bit, 8bit, 16bit, 32bit or 64bit etc. The bus width supported by
the device should be same as that of the host processor.

The bus interface diagram shown in Figure illustrates the interfacing of devices through parallel
interface.

D0 to Data Bus
Dx-1 Peripheral Device
RD\ RD\ (Eg: ADC)
WR\ WR\
Host Control Signals CS\
(Microprocessor/
Controller) Chip Select

A0 to Address Bus Address De-coder

Ay-1 Circuit

x: Data bus width

y: Address Bus width

Fig: Interfacing of devices through parallel interface

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2.4.2 External Communication Interfaces:

The External Communication Interface refers to the different communication

channels/buses used by the embedded system to communicate with the external world. The
following section gives an overview of the various interfaces for external communication.

2.4.2.1 RS-232 & RS 485:

• RS-232 C (Recommended Standard number 232, revision C from the Electronic Industry
Association) is a legacy, full duplex, wired, asynchronous serial communication interface.
• The RS-232 interface is developed by the Electronics Industries Association (EIA) during
the early 1960s. RS-232 extends the UART communication signals for external data
communication.
• UART uses the standard TTL/CMOS logic (Logic ‘High’ corresponds to bit value 1 and
Logic ‘Low‘ corresponds to hit value 0) for bit transmission whereas RS-232 follows the
EIA standard for bit transmission.
• As per the EIA standard, a logic ‘0’ is represented with voltage between +3 and +25V and
a logic ‘l’ is represented with voltage between -3 and -25V. In EIA standard, logic ‘0’ is
known as ‘Space’ and logic ‘1’ as ‘Mark’. The RS-232 interface defines various
handshaking and control signals for communication apart from the ‘Transmit’ and
‘Receive' signal lines for data communication.
• RS-232 supports two different types of connectors, namely; DB-9: 9-Pin connector and
DB-25: 25-Pin connector. Figure illustrates the connector details for DB-9 and DB-25.

1 13
1 5

6 9 14 25
DB-25
DB-9

• The pin details for the DB-9 connectors are explained in the following table:

Pin Pin No: Description

Name (For DB-9 Connector)

TXD 3 Transmit Pin. Used for Transmitting Serial Data

RXD 2 Receive Pin. Used for Receiving serial Data

RTS 7 Request to send.

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CTS 8 Clear To Send

DSR 6 Data Set ready

GND 5 Signal Ground

DCD 1 Data Carrier Detect

DTR 4 Data Terminal Ready

RI 9 Ring Indicator

• RS-232 is a point-to-point communication interface and the devices involved in RS-232

communication are called “Data Terminal Equipment (DTE)” and “Data Communication
Equipment (DCE)”.
• If no data flow control is required. Only TXD and RXD signal lines and ground line (GND)
are required for data transmission and reception. The RXD pin of DCE should be connected
to the TXD pin of DTE and vice versa for proper data transmission.
• If hardware data how control is required for serial transmission, various control signal lines
of the RS-232 connection are used appropriately. The control signals are implemented
mainly for modem communication and some of them may not be relevant for other type of
devices.
• The Request to Send (RTS) and Clear to Send (CTS) signals co-ordinate the
communication between DTE and DCE. Whenever the DTE has a data to send, it activates
the RTS line and if the DCE is ready to accept the data, it activates the CTS line.
• The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept
data.
• The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a
communication link. DTR should be in the activated state before the activation of DSR.
• The Data Carrier Detect (DCD) control signal is used by the DCE to indicate the DTE that
a good signal is being received.
• Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the
telephone line.
• The 25 pin DB connector contains two sets of signal lines for transmit, receive and control
lines. Nowadays DB-25 connector is obsolete and most of the desktop systems are
available with DB-9 connectors only.
• As per the EIA standard RS-232 C supports baud rates up to 20Kbps (Upper limit 19.2
Kbps) The commonly used baud rates by devices are 300bps, l200bps, 2400bps, 9600bps,
11.52Kbps and 19.2Kbps. 9600 is the popular baud rate setting used for PC
communication. The maximum operating distance supported by RS-232 is 50 feet at the
highest supported baudrate.

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• Embedded devices contain a UART for serial communication and they generate signal
levels conforming to TTL CMOS logic.
• A level translator lC like MAX 232 from Maxim Dallas semiconductor is used for
converting the signal lines from the UART to RS-232 signal lines for communication.
• On the receiving side the received data is converted back to digital logic level by a
converter IC. Convener chips contain converters for both transmitter and receiver.
• Though RS-232 was the most popular communication interface during the olden days, the
advent of other communication techniques like Bluetooth, USB, Fire wire, etc. are pushing
down RS-232 from the scenes. Still RS-232 is popular in certain legacy industrial
applications.
• RS-232 supports only point-to-point communication and not suitable for multi-drop
communication. It uses single ended data transfer technique for signal transmission and
thereby more susceptible to noise and it greatly reduces the operating distance.
• RS-422 is another serial interface standard from EIA for differential data communication.
It supports data rates up to 100 Kbps and distance up to 400 ft. The same RS-232 connector
is used at the device end and an RS-232 to RS-422 converter is plugged in the transmission
line. At the receiver end the conversion from RS-422 to RS-232 is performed. RS-422
supports multi-drop communication with one transmitter device and receiver devices up to
10.
• RS-485 is the enhanced version of RS-422 and it supports multi-drop communication with
up to 32 transmitting devices (drivers) and 32 receiving devices on the bus. The
communication between devices in the bus uses the ‘addressing’ mechanism to identify
slave devices.

2.4.2.2 Universal Serial Bus (USB):

• Universal Serial Bus (USB) is a wired high speed serial bus for data communication. The
first version of USB (USB1.0) was released in 1995 and was created by the USB core
group members consisting of Intel, Microsoft, IBM, Compaq, Digital and Northern
Telecom.
• The USB communication system follows a star topology with a USB host at the center and
one or more USB peripheral devices/USB hosts connected to it.
• A USB host can support connections up to 127, including slave peripheral devices and
other USB hosts.
• Figure illustrates the star topology for USB device connection.

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Peripheral
Device 2

Peripheral USB Host Peripheral

Device 1 (Hub) Device 3

USB Host
(Hub)

Peripheral Peripheral
Device 4 Device 5

USB Device Connection Topology

• USB transmits data in packet format. Each data packet has a standard format. The USB
communication is a host initiated one. The USB host contains a host controller which is
responsible for controlling the data communication, including establishing connectivity
with USB slave devices, packetizing and formatting the data.
• There are different standards for implementing the USB Host Control interface; namely
Open Host Control Interface (OHCI) and Universal Host Control Interface (UHCI).
• USB uses differential signals for data transmission. It improves the noise immunity. USB
interface has the ability to supply power to the connecting devices. Two connection lines
(Ground and Power) of the USB interface are dedicated for carrying power. It can supply
power up to 500 mA at 5 V. It is sufficient to operate low power devices. Mini and Micro
USB connectors are available for small form factor devices like portable media players.
• The pin details for connectors are listed below:

Pin No: Pin Name Description

1 VBUS Carries power (5V)
2 D- Differential data carrier line
3 D+ Differential data carrier line
4 GND Ground signal line

• Each USB device contains a Product ID (PID) and a Vendor ID (VID). The PID and VID
are embedded into the USB chip by the USB device manufacturer. The VID for a device
is supplied by the USB standards forum. PID and VID are essential for loading the drivers
corresponding to a USB device for communication.
• USB supports four different types of data transfers, namely; Control, Bulk, Isochronous
and Interrupt.
• Control transfer is used by USB system software to query, configure and issue commands
to the USB device. 8qu transfer is used for sending a block of data to a device.

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• Bulk transfer supports error checking and correction. Transferring data to a printer is an
example for bulk transfer.
• Isochronous data transfer is used for real-time data communication. In Isochronous
transfer, data is transmitted as streams in real-time. Isochronous transfer doesn’t support
error checking and re-transmission of data in case of any transmission loss. All streaming
devices like audio devices and medical equipment for data collection make use of the
isochronous transfer.
• Interrupt transfer is used for transferring small amount of data. Interrupt transfer
mechanism makes use of polling technique to see whether the USB device has any data to
send.
• The frequency of polling is determined by the USB device and it varies from 1 to 255
milliseconds. Devices like Mouse and Keyboard, which transmits fewer amounts of data,
uses interrupt transfer.
• Presently USB supports four different data rates namely; Low Speed (1.5Mbps), Full Speed
(l2Mbps), High Speed (480Mbps) and Super Speed (4.8Gbps). The Low Speed and Full
Speed specifications are defined by USB 1.0 and the High Speed specification is defined
by USB 2.0. USB 3.0 defines the specifications for Super Speed. USB 3.0 is expected to
be in action by year 2009.

2.4.2.3 IEEE 1394 (Fire wire):

• IEEE 1394 is a wired, isochronous high speed serial communication bus. It is also known
as High Performance Serial Bus (HPSB). The research on 1394 was started by Apple Inc.
in 1985 and the standard for this was coined by IEEE.
• 1394 supports peer-to-peer connection and point-to-multipoint communication allowing
63 devices to be connected on the bus in a tree topology. 1394 is a wired serial interface
and it can support a cable length of up to 15 feet for interconnection.
• The 1394 standard has evolved a lot from the first version IEEE 1394-1995 released in
1995 to the recent version IEEE 1394-2008 released in June 2008. The 1394 standard
supports a data rate of 400 to 3200Mbits/second.
• The IEEE 1394 uses differential data transfer and the interface cable supports 3 types of
connectors, namely; 4-pin connector, 6-pin connector (alpha connector) and 9 pin
connector (beta connector).
• The table given below illustrates the pin details for 4, 6 and 9 pin connectors.

Pin Pin No: Pin No: Pin No: Description

Name
(4 Pin (6 Pin (9 Pin
Connector) Connector) Connector)
Power 1 8 Unregulated DC supply. 24 to 30V

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Signal 2 6 Ground connection

Ground
TPB- 1 3 1 Differential Signal line for Signal
Line B
TPB+ 2 4 2 Differential Signal line for Signal
Line B
TPA- 3 5 3 Differential Signal line for Signal
Line A
TPA+ 4 6 4 Differential Signal line for Signal
Line A
TPA(S) 5 Shield for the differential signal line
A. Normally grounded
TPB(S) 9 Shield for the differential signal line
B. Normally grounded
NC 7 No connection

• There are two differential data transfer lines A and B per connector. In a 1394 cable,
normally the differential lines of A are connected to B (TPA+ to TPB+ and TPA-to TPB~)
and vice versa.
• 1394 is a popular communication interface for connecting embedded devices like Digital
Camera, Camcorder, and Scanners to desktop computers for data transfer and storage.
• Unlike USB interface (Except USB OTG), IEEE 1394 doesn‘t require a host for
communicating between devices. For example, you can directly connect a scanner with a
printer for printing.

2.4 IrDA (Infrared):

• Infrared (IrDA) is a serial, half duplex, line of sight based wireless technology for data
communication between devices. It is in use from the olden days of communication and
you may be very familiar with it. The remote control of your TV, VCD player, etc. works
on infrared data communication principle.
• Infrared communication technique uses infrared waves of the electromagnetic spectrum for
transmitting the data.
• IrDA supports point-point and point-to-multipoint communication, provided all devices
involved in the communication are within the line of sight.
• The typical communication range for IrDA lies in the range 10 cm to 1 m. The range can
be increased increasing the transmitting power of the IR device.

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• IR supports data rates ranging from 9600bits/second to 16Mbps.

• Depending on the speed of data transmission IR is classified into Serial IR (SIR), Median1
IR (MIR), Fast IR (FIR), Very Fast IR (VFIR) and Ultra-Fast IR (UFIR).
• SIR supports transmissio1 rates ranging from 9600bps to 115.2kbps. MIR supports data
rates of 0.576Mbps and 1.152Mbps. FIR supports data rates up to 4Mbps. VFIR is designed
to support high data rates up to 16Mbps. The UFIR specs are under development and it is
targeting a data rate up to l00Mbps.
• IrDA communication involves a transmitter unit for transmitting the data over IR and a
receiver for receiving the data.
• Infrared Light Emitting Diode (LED) is the IR source for transmitter and at the receiving
end a photodiode acts as the receiver. Both transmitter and receiver unit will be present in
each device supporting IrDA communication for bidirectional data transfer. Such IR units
are known as ‘Transceiver’.
• Certain devices like a TV remote control always require unidirectional communication and
so they contain either the transmitter or receiver unit (The remote control unit contains the
transmit. per unit and TV contains the receiver unit).
• The IrDA control protocol contains implementations for Physical Layer (PHY), Media
Access Control (MAC) and Logical Link Control (LLC). The Physical Layer defines the
physical characteristics of communication like range, data rates, power, etc.

2.5 Bluetooth (BT):

• Bluetooth is a low cost, low power, short range wireless technology for data and voice
communication. Bluetooth was first proposed by ‘Ericsson’ in 1994.
• Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the Frequency
Hopping Spread Spectrum (FHSS) technique for communication.
• It supports a data rate of up to 1Mbps and a range of approximately 30 feet for data
communication.
• Bluetooth communication also has two essential parts; a physical link part and a protocol
part. The physical link is responsible for the physical transmission of data between devices
supporting high Bluetooth communication and protocol part is responsible for defining the
rules of communication. The physical link works on the wireless principle making use of
RF waves for communication. Bluetooth enabled devices essentially contain a Bluetooth
wireless radio for the transmission and reception of data. The rules governing the Bluetooth
communication is implemented in the ‘Bluetooth protocol stack’. The Bluetooth
communication IC holds the stack. Each Bluetooth device will have a 48 bit unique
identification number. Bluetooth communication follows packet used data.
• Bluetooth supports point-to-point (device to device) and point-to-multipoint (device to
multiple device broadcasting) wireless communication. The point-to-point communication
follows the master slave relationship.

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• A Bluetooth device can function as either master or slave. When a network is formed with
one Bluetooth device as master and more than one device as slaves, it is called a Piconet/
A Pico net supports a maximum of seven slave devices.
• Bluetooth is the favorite choice for short range data communication in handheld embedded
devices. Bluetooth technology is very popular among cell phone users as they are the
easiest communication channel for transferring ringtones, music files, pictures, media files,
etc. between neighboring Bluetooth enabled phones.
• The Bluetooth standard specifies the minimum requirements that a Bluetooth device must
support for a specific usage scenario.
• The Generic Access Profile (GAP) defines the requirements for detecting a Bluetooth
device and establishing a connection with it. All other specific usage profiles are based on
GAP.
• Serial Port Profile (SPP) for serial data communication, File Transfer Profile (FTP) for file
transfer between devices, Human Interface Device (HID) for supporting human interface
devices like keyboard and mouse are examples for Bluetooth profiles.
• The specifications for Bluetooth communication is defined and licensed by the standards
body ‘Bluetooth Special interest Group (SIG)’.

2.6 WI-FI:

• Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices.
• Wi-Fi follows the IEEE 802.11 standard. Wi-Fi 1s intended for network communication
and it supports Internet Protocol (IP) based communication it is essential to have device
identities in a multipoint communication to address specific devices for data
communication.
• In a 1P based communication each device is identified by an IP address, which is unique
to each device on the network. Wi-Fi based communications require an intermediate agent
called Wi-Fi router/Wireless Access point to manage the communications.
• The Wi-Fi router is responsible for restricting the access to a network, assigning IP address
to devices on the network, routing data packets to the intended devices on the network.
• Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the
form of radio signals through an antenna. The hardware part of it is known as Wi-Fi Radio.
• Wi-Fi operates at 2.4GHz or 5GHz of radio spectrum and they co-exist with other ISM
band devices like Bluetooth. Figure illustrates the typical interfacing of devices in a Wi-Fi
network.

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Wi-Fi Router

Device 1
Device 2 Device 3

• For communicating with devices over a Wi-Fi network, the device when its Wi-Fi radio is
turned ON, searches the available Wi-Fi network in its vicinity and lists out the Service Set
Identifier (SSID) of the available networks.
• If the network is security enabled, a password may be required to connect to a particular
SSID. Wi-Fi employs different security mechanisms like Wired Equivalency Privacy
(WEP) Wireless Protected Access (WPA), etc. for securing the data communication.
• Wi-Fi supports data rates ranging from 1Mbps to 150Mbps.
• Wi-Fi offers a range of 100 to 300 feet.

2.7 ZigBee:

• ZigBee is a low power, low cost, wireless network communication protocol based on the
IEEE 802.15.4-2006 standard.
• ZigBee is targeted for low power, low data rate and secure applications for wireless Area
Networking (W PAN).
• The ZigBee specifications support a robust mesh network containing multiple nodes. This
networking strategy makes the network reliable by permitting messages to travel through
a number of different paths to get from one node to another.
• ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to
2.484 GHZ, 902 to 928 MHz and 868.0 to 868.6MHz.
• ZigBee Supports an operating distance of up to 109 meters and a data rate of 20 to 250Kbps.
• In the ZigBee terminology, each ZigBee device falls under any one of the following ZigBee
device category
1.ZigBee Coordinator (ZC)/Network Coordinator: The ZigBee coordinator acts as the
root of the ZigBee network. The ZC is responsible for initiating the ZigBee network and it
has the capability to Store information about the network.
2.ZigBee Router (ZR)/Full function Device (FFD): Responsible for passing information
from device to another device or to another ZR.
3.ZigBee End Device (ZED)/Reduced Function Device (RFD): End device containing
ZigBee functionality for data communication. It can talk only with a ZR or ZC and doesn’t
have the capability to act as a mediator for transferring data from one device to another.

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ZED ZED

ZED

ZR ZC ZR

ZED ZED

2.5 EMBEDDED FIRMWARE

Embedded firmware refers to the control algorithm (Program instructions) and or the
configuration settings that an embedded system developer dumps into the code (Program) memory
of the embedded system. It is an un-avoidable part of an embedded system. There are various
methods available for developing the embedded firmware. They are listed below.

1. Write the program in high level languages like Embedded C/C++ using an Integrated
Development Environment (The IDE will contain an editor, compiler, linker, debugger, simulator,
etc. IDES are different for different family of processors/controllers. For example, Keil micro
vision3 IDE is used for all family members of 8051 microcontroller, since it contains the generic
8051 compiler C51).

2. Write the program in Assembly language using the instructions supported by your application’s
target processor controller.

2.6 OTHER SYSTEM COMPONENTS

The other system components refer to the components/circuits/ICS which are necessary for
the proper functioning of the embedded system. Some of these circuits may be essential for the
proper functioning of the processor/controller and firmware execution. Watchdog timer, Reset IC
(or passive circuit), brown-out protection 1C (or passive circuit), etc. are examples of circuits/1C5
which are essential for the proper functioning of the processor/controllers. Some of the controllers
or SOC’s integrate these components within a single IC and doesn’t require such components
externally connected to the chip for proper functioning.

2.6.1 Reset Circuit

✓ The Reset circuit is essential to ensure that the device is not operating at a voltage level
where the device is not guaranteed to operate, during system power ON
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✓ The Reset signal brings the internal registers and the different hardware systems of the
processor/controller to a known state and starts the firmware execution from the reset
vector (Normally from vector address 0x0000 for conventional processors/controllers

✓ The reset vector can be relocated to an address for processors/controllers supporting

bootloader

✓ The reset signal can be either active high (The processor undergoes reset when the reset
pin of the processor is at logic high) or active low (The processor undergoes reset when the
reset pin of the processor is at logic low).

Figure illustrates a Resistor capacitor based passive reset circuit for active high and low
configuration:

Fig:RC based Reset Circuit

2.6.2 Brown-out Protection Circuit

✓ Brown-out protection circuit prevents the processor/controller from unexpected program

execution behavior when the supply voltage to the processor/controller falls below a
specified voltage

✓ The processor behavior may not be predictable if the supply voltage falls below the
recommended operating voltage. It may lead to situations like data corruption

✓ A brown-out protection circuit holds the processor/controller in reset state, when the
operating voltage falls below the threshold, until it rises above the threshold voltage

✓ Certain processors/controllers support built in brown-out protection circuit which monitors

the supply voltage internally

✓ If the processor/controller doesn’t integrate a built-in brown-out protection circuit, the

same can be implemented using external passive circuits or supervisor ICs

Figure illustrates a brown-out circuit implementation using Zener diode and transistor for
processor/controller with active low Reset Logic.

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Vcc

R1

V BE
R2
Q

Reset Pulse
DZ Active Low

Vz
R3

GND

Brown-out Protection circuit using active low output

The Zener diode Dz and transistor Q forms the heart of this circuit. The transistor conducts
always when the supply voltage Vcc is greater than that of the sum of VBE and Vz (Zener voltage).
The transistor stops conducting when the supply voltage falls below the sum of Var. and VzSelect
the Zener diode with required voltage for setting the low threshold value for Vcc. The values of
R1, R2, and R3 can be selected based on the electrical characteristics (Absolute maximum current
and voltage ratings) of the transistor in use. Microprocessor Supervisor like D81232 from Maxim
Dallas (www.maximigcom) also provides Brown-out protection.

2.6.3 Oscillator Unit

✓ A microprocessor/microcontroller is a digital device made up of digital combinational and

sequential circuits

✓ The instruction execution of a microprocessor/controller occurs in sync with a clock signal

✓ The oscillator unit of the embedded system is responsible for generating the precise clock
for the processor

✓ Certain processors/controllers integrate a built-in oscillator unit and simply require an

external ceramic resonator/quartz crystal for producing the necessary clock signals

✓ Certain processor/controller chips may not contain a built-in oscillator unit and require the
clock pulses to be generated and supplied externally

✓ Quartz crystal Oscillators are example for clock pulse generating devices

✓ Figure illustrates the usage of quartz crystal/ceramic resonator and external oscillator chip
for clock generation.

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Microcontroller Microprocessor
C : Capacitor
Y : Resonator

Crystal Oscillator
Oscillator
Unit
Quartz Crystal Clock Input Pin
Resonator C C
Y Oscillator
Unit

Oscillator circuitry using quartz crystal and quartz crystal oscillator

2.6.4. Real-Time Clock (RTC)

✓ The system component responsible for keeping track of time. RTC holds information like
current time (In hour, minutes and seconds) in 12 hour /24 hour format, date, month, year,
day of the week etc and supplies timing reference to the system

✓ RTC is intended to function even in the absence of power. RTCs are available in the form
of Integrated Circuits from different semiconductor manufacturers like Maxim/Dallas, ST
Microelectronics etc

✓ The RTC chip contains a microchip for holding the time and date related information and
backup battery cell for functioning in the absence of power, in a single IC package

✓ The RTC chip is interfaced to the processor or controller of the embedded system

✓ For Operating System based embedded devices, a timing reference is essential for
synchronizing the operations of the OS kernel. The RTC can interrupt the OS kernel by
asserting the interrupt line of the processor/controller to which the RTC interrupt line is
connected

✓ The OS kernel identifies the interrupt in terms of the Interrupt Request (IRQ) number
generated by an interrupt controller

✓ One IRQ can be assigned to the RTC interrupt and the kernel can perform necessary
operations like system date time updation, managing software timers etc when an RTC
timer tick interrupt occurs

2.6.5 Watchdog Timer

• The watchdog timer is a timing device that resets the system after a predefined timeout. It
is activated within the first few clock cycles after power-up.

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• It helps in rescuing the system if a fault develops and program gets stuck. On restart, the
system functions normally.

• The watchdog timer reset is a required feature in control applications.

• Assume that we anticipate that a set of tasks must finish in 100 ms interval.

• The watchdog timer is disabled and stopped by the program instruction in case the tasks
finish within 100 ms interval.

• In case task does not finish (not disabled by the program instruction), watchdog timer
generates interrupts after 100 ms and executes a routine, which is programmed to run
because there is failure of finishing the task in anticipated interval.

• An application in mobile phone is that display is off in case no GUI interaction takes place
within a watched time interval.

• The interval is usually set at 15 s, 20 s,

• 25 s, 30 s in mobile phone.This saves power.

• A timer unit for monitoring the firmware execution

• Depending on the internal implementation, the watchdog timer increments or decrements

a free running counter with each clock pulse and generates a reset signal to reset the
processor if the count reaches zero for a down counting watchdog, or the highest count
value for an up counting watchdog

• If the watchdog counter is in the enabled state, the firmware can write a zero (for up
counting watchdog implementation) to it before starting the execution of a piece of code
(subroutine or portion of code which is susceptible to execution hang up) and the watchdog
will start counting. If the firmware execution doesn’t complete due to malfunctioning,
within the time required by the watchdog to reach the maximum count, the counter will
generate a reset pulse and this will reset the processor

• If the firmware execution completes before the expiration of the watchdog timer the WDT
can be stopped from action

• Most of the processors implement watchdog as a built-in component and provides status
register to control the watchdog timer (like enabling and disabling watchdog functioning)
and watchdog timer register for writing the count value. If the processor/controller doesn’t
contain a built in watchdog timer, the same can be implemented using an external watchdog
timer IC circuit.

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Microoprocessor/
Controller
Watchdog
Free Running
Reset Pin
Counter

Watchdog Reset

System Clock

Watch Dog timer for firmware execution supervision

2.7 PCB AND PASSIVE COMPONENTS

Printed Circuit Board (PCB) is the backbone of every embedded system. After finalizing
the component and the inter-connection among them, a schematic design is created and according
to the schematic PCB is fabricated.

PCB acts as a platform for mounting all the necessary components as per the design requirement.
Also it acts as a platform for testing your embedded firmware.

Apart from the above-mentioned important subsystems of an embedded system, you can find some
passive electronic components like resistor, capacitor, diodes, etc. on your board. They are the co-
workers of various chips contained in your embedded hardware. They are very essential for the
proper functioning of you embedded system.

For example for providing a regulated ripple-free supply voltage to the system, a regulator IC and
spike suppressor filter capacitors are very essential.

QUESTION BANK

1. Explain the 6 purposes of embedded systems with an example for each.

2. Explain the components of a typical embedded system with a neat diagram.
3. Differentiate between (i) General Computing Systems and Embedded Systems.
(ii) RISC and CISC architectures. (iii)microprocessor and microcontroller.(iv) Hardvard vs
von Neumann (v) Big endian vs Little endian
4. Explain the 3 classifications of embedded systems based on complexity and performance.
5. Mention the applications of embedded systems with an example for each.
6. What are the core used in embedded system? Discuss in detail.
7. What are the different types of memories used in Embedded system design? Explain the
role of each.
8. Brifly explain PLDs and type of PLDs
9. Explain the functions of Opt coupler and Relay with diagrams.
10. Write a note on embedded firmware.
11. Discuss the I2c communication interface with neat diagram.

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12. Explain the sequence of operations for communicating with an I2C slave device.
13. Elaborate the working of SPI bus with a neat interfacing diagram.
14. Explain the working of a relay driver with a diagram.
15. Explain operation of UART .Compare UART and USB.
16. Compare serial and parallel communication.
17. Explain USB protocol with a neat diagram also discuss different data transferred in USB.
18. Write a note on 1-wire bus .Explain its advantage and disadvantages.
19. Explain the reset and brown out protection circuits their significance and application in
embedded system.
20. Mention the role of watch dog timer in embedded system with relevant examples.
21. Explain the features of the following: (i)IrDA (ii)WiFi

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