Architecture, Programming, and Interfacing (8086 to Pentium)
MEMORY INTERFACING
PROF. DR. SHAMIM AKHTER
Professor, Computer Science and Engineering (CSE)
Objectives
-Transistors -Transistors, Capacitor
-No refreshing -Refreshing
--Access time 10ns --Access time 60ns
ROM
RAM
Address decoder Controller
Programmable Logic Devices (PLDs)
Interfacing Memory to Data Bus
µP-20 bit address (1 M)
Interfacing
MISS MATCHED
ROM has 11(2 K) /16 address pins (64 K)
Memory Unit
• Memory unit –
– a collection of cells capable of storing a large quantity of
binary information and
• to which binary information is transferred for storage
• from which information is available when needed for processing
– together with associated circuits needed to transfer
information in and out of the device
• write operation: storing new information into memory
• read operation: transferring the stored information out of the
memory
• Two major types
– RAM (Random-access memory): Read + Write
• accept new information for storage to be available later for use
– ROM (Read-only memory): performs only read operation
Memory(ROM/RAM) Pin Connections
8 I/O connections
reflect memory can
store 8 bits data in each
location
N bits
M bits
# of address
connections depend on 1KxMbits
memory locations
1M= 20 bit address
CS ROM has 1 control signal R/W
RAM has 2 control signals OE(G), WE (W)
2716 2Kx8 EPROM
A0-A3
A4-A10
RAM Memory
TMS4016 2Kx8 static RAM(SRAM)
SRAMs used for caches have access times as low as 10ns.
Slowest 4016 SRAM Access Time = 250 ns
- Fast enough to connect directly with 8086/8088 (5 MHz) without wait states
Largest SRAM 1Mx8
Address line
Address line
, High vol activates
Low/High vol
Asserted Wordline
Transistor turned on
The charge stored in the capacitor is fed out onto the Bitline
And to the sense amplifier.
The sense amplifier compares the capacitor voltage to a ref. value and determine the cell
value 1/ 0.
60-100 ms
Capacitor have a natural tendency
to discharge
BL BL’
Address Decoding
• Micro-processor
– 20 address pins (1MB)
• EPROM
– 11 address pins (2KB)
• The mismatch must be corrected
– Decoder corrects the mismatch
Address Decoding
2716 EPROM, NAND Gate Decoder
• NAND Gate Decoder decodes Memory Location
FF800H- FFFFFH
The 3 to 8 Line Decoder (74LS138)
EQ. Design a circuit to address memory range F0000H-FFFFFH using 74LS138 3- to-8
decoder and 2764 (8Kx8) EPROMs.
Must be High
8x8Kx8
EPROMs
Dual 2 to 4 Line Decoder
Simple Memory
System with
74HCT139
00000H–1FFFFH
EPROM(271000) 128K × 8
SRAM (621000) 128K × 8
E0000H–FFFFFH
Programmable Logic Array
Behave like a ROM but has a different structure
•Uses ANDs array instead of decoder to produce product terms of inputs
•Has programmable connections
-before ANDs, between ANDs and Ors, and after ORs. That is 2n k + km + m fuses
•More flexible than ROM but more difficult to program
•Logic expressions for content information to be stored in PLA must be obtained first, then
minimized, and finally programmed into the PLA using a PLA program table
•PLA program table specifies product terms and sum terms of information that will be stored
in PLA
PLA
kxm
PLA is used to provide control over datapath.
nxk PLA is used as a counter.
PLA is used as a decoder.
m PLA is used as a BUS interface in programmed I/O.
PLD-Programmable Device
• A programmable logic device (PLD) is an electronic component used to
build reconfigurable digital circuits.
• Unlike a logic gate, which has a fixed function, a PLD has an undefined
function at the time of manufacture.
• Before the PLD can be used in a circuit it must be programmed, that is,
reconfigured. [WIKI,2018]
ROM and RAM Interface Using PLD
00000H-1FFFFH
00000H–1FFFFH
60000H-7FFFFH
60000H–7FFFFH
Memory Interface – 8088/80188
8 bit data bus
EPROM
27256
32K of EPROM
(at addresses
U1= E8000H EFFFFH,
8088 (5MHz) U2=F0000H-F7FFFH and
U3= F8000H-FFFFFH.
20 address 74HCT138
connections 74LS138 (3-to-8
(A19 to A0). line decoder)
EPROM will also require the generation of a
wait state.
plus 3 2732
8 data bus ( 32K X 8 )
•The EPROM has an access time of 450ns .
connections EPROMs.
•The 74LS138 requires 8ns to decode.
(AD7 to AD0). •The 8088 runs at 5MHz and only
allows 460ns for memory to access data.
3 control signals, •A wait state adds 200ns of additional time.
IO/M, RD, and WR.
RAM
62256
32K x8 of 16
SRAMs
(at addresses
00000H -7FFFFH).
EPROM Interfacing with 8088
A19 A18 A17 A16 A15
E8000H 1 1 1 0 1 xxx xxxx xxxx xxxx
F0000H 1 1 1 1 0 xxx xxxx xxxx xxxx
F8000H 1 1 1 1 1 xxx xxxx xxxx xxxx
Memory Interface – 8086/80286
16 bit data bus
• Differ from 8088/80188
– Data bus 16 bits (24bit @ 80286,80386SX)
– M/IO(8086,80186)
– Control signal BHE and A0 or BLE
– MRDC, MWTC (80286, 80386SX) instead RD, WR
• 16 bit data bus challenge
– Processor can work on 8 bits or 16 bits data
– Separate sections (banks)-8 bits
A0
BHE BLE Function
0 0 Both
enabled
0 1 High
bank(8)
1 0 Low
bank(8)
1 1 None
• Bank selection can be done in two (2) ways
– Separate decoders for each bank
– Separate write signal is developed to select a write to each bank
of the memory
D8-D15
Separate Bank Decoder
x
Sixteen 64k (216)RAM = 1M byte
RAM , 24 bit address
(80386SX)
U1
Memory address range:
000000H-0FFFFFH
U3
Book has wrong (U3 and
U2) in Fig-10-28.
19 18 17 16 15 … 1 0
0 0 0 0 0 00
1 1 1 1 1 11
U2
Separate Bank Write Strobes
8086 micro processor
80286/80386SX generates MWTC instead of WR
No separates read strobes for each memory bank:
-8086,80186, 80286 and 80386SX always read only the byte of data
-- for 16 bits sections of data are always presented to the data bus during a read, the
microprocessor ignores the 8 bit section that it does not need, without any conflicts or
special problems.
MRDC
BHE
Error Correcting Code Function
How the comparison
is done? 0 to 2k-1
X-OR -> Syndrome K needs to be choose in a
way so that 2k-1 >=
M+ K
Hamming Code
Venn Diagrams
• 4 bits Words (M=4)
• Choosing Parity bit=1/0
– so that total # of 1 in circle is even
How many k bits for total M bit data
that 2k-1 >= M+ K
M K
8 3 23-1 < M+ K
8 4 24-1 >= M+ K, 4 bits OK
Discrepancies in A and C but not in B
Layout of Data Bits and Check Bits
Single-Error-Correcting (SEC)
Example
• 8 bits input- 0 0 1 1 1 0 0 1
• Check bits Calculation:
• C1=D1 ⊕ D2 ⊕ D4 ⊕D5 ⊕D7
• = 1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1
• C2= D1 ⊕ D3 ⊕D4 ⊕D6 ⊕D7
• =1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1
• C4= D2 ⊕D3 ⊕D4 ⊕D8
• = 0 ⊕ 0 ⊕ 1 ⊕ 0 =1
• C8=D5 ⊕D6 ⊕D7 ⊕D8
• = 1 ⊕ 1 ⊕ 0 ⊕ 0 =0
• C1=1, C2=1, C4=1, C8=0
• 8 bits input- 0 0 1 1 1 1 0 1
• Check bits Calculation:
• C1=D1 ⊕ D2 ⊕ D4 ⊕D5 ⊕D7
• = 1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1
• C2= D1 ⊕ D3 ⊕D4 ⊕D6 ⊕D7
• =1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 0 =0
• C4= D2 ⊕D3 ⊕D4 ⊕D8 If the syndrome contains all 0s, no error has been
• = 0 ⊕ 1 ⊕ 1 ⊕ 0 =0 detected.
• C8=D5 ⊕D6 ⊕D7 ⊕D8 If the syndrome contains one and only one bit set to 1,
then the error has occurred in one of the 4 check bits.
• = 1 ⊕ 1 ⊕ 0 ⊕ 0 =0
No correction is needed.
• C1=1, C2=0, C4=0, C8=0
If the syndrome contains more than one bit set to 1,
then the numerical value of the syndrome indicates
C8 C4 C2 C1 the position of the data bit in error. The data bit is
0 1 1 1 inverted for correction.
⊕ 0 0 0 1
0 1 1 0 6 # bit has error (D3)
Double-Error-Detection (DED)
Example
• TX-8 bits input- 0 0 1 1 1 0 0 1
• Check bits Calculation:
• C1=D1 ⊕ D2 ⊕ D4 ⊕D5 ⊕D7
• = 1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1
• C2= D1 ⊕ D3 ⊕D4 ⊕D6 ⊕D7
• =1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 =1
• C4= D2 ⊕D3 ⊕D4 ⊕D8
• = 0 ⊕ 0 ⊕ 1 ⊕ 0 =1
• C8=D5 ⊕D6 ⊕D7 ⊕D8
• = 1 ⊕ 1 ⊕ 0 ⊕ 0 =0
• C1=1, C2=1, C4=1, C8=0
• General Parity Bit (GP) = 0 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 0 ⊕ 0 ⊕ 1=0
• Even Parity Bit
• Rx: 8 bits input- 0 0 1 1 0 1 0 1 GP=0
• Check bits Calculation:
• C1=D1 ⊕ D2 ⊕ D4 ⊕D5 ⊕D7
• = 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 0 =0
• C2= D1 ⊕ D3 ⊕D4 ⊕D6 ⊕D7
• =1 ⊕ 1 ⊕ 0 ⊕ 1 ⊕ 0 =1
• C4= D2 ⊕D3 ⊕D4 ⊕D8 If the syndrome contains all 0s, and GPs are same-
• = 0 ⊕ 1 ⊕ 0 ⊕ 0 =1 no error has been detected.
• C8=D5 ⊕D6 ⊕D7 ⊕D8 If the syndrome is not 0, but GPs are the same then
• = 1 ⊕ 1 ⊕ 0 ⊕ 0 =0 DED.
• C1=1, C2=0, C4=0, C8=0
SEC: If the GPs are not the same and the syndrome
contains more than one bit set to 1, then the
C8 C4 C2 C1
numerical value of the syndrome indicates the
0 1 1 1
position of the data bit in error. The data bit is
⊕ 0 1 1 0
inverted for correction.
0 0 0 1
If the syndrome contains all 0s but GPs are not the
same, GP has a problem.
Error Correcting Circuit
8 data I/O pins
5 check bit I/O pins
2 control pins (S0 and S1 – selects the operation)
2 error outputs
- Single error flag ( SEF)
- Double error flag ( DEF)
8 bit Error correction and detection circuit
Corrects single bit memory read error and
Flags any 2 bit error called SECDED (Single error correction
and double error detection)
S1 S0 Function SEF DEF
0 0 Write Check Word 0 0
0 1 Correct data word Determine by error type
1 0 Read Data 0 0
1 1 Latch Data Determine by error type
