CSE_3523

Segment-6
I/O operation

Course Teacher: Mujibur Rahman Maruf 1

 Microprocessor, microcontroller and
embedded system
Course code: CSE-3523
Credit Hour: 3
Md. Mujibur Rahman Maruf
Assistant Lecturer,
Dept. of CSE, IIUC
Mujiburmaruf.cuet17@gmail.com

International Islamic Uni)versity Chittagong(IIUC)

Course Teacher: Mujibur Rahman Maruf 2
 Introduction to I/O Interface
The I/O interface allows communication between the microprocessor and
external devices . IN and OUT Instruction transfer data between an I/O
device and the microprocessor's accumulator (AL, AX or EAX).
IN/OUT Operation Examples Based on Data and Address Size
# Address Type Data Size Example Instruction Meaning
IN AL, 60H I/O with fixed port 60H
1 8-bit fixed 8-bit
OUT 60H, AL using AL
MOV DX, 03F8H
I/O with port in DX
2 16-bit via DX 8-bit IN AL, DX
using AL
OUT DX, AL
MOV DX, 0378H
I/O with port in DX
3 16-bit via DX 16-bit IN AX, DX
using AX
OUT DX, AX
IN AX, 19H I/O with fixed port
4 8-bit fixed 16-bit
OUT 19H, AX 0019H using AX
Course Teacher: Mujibur Rahman Maruf
3
 Isolated Vs Memory Mapped
Isolated I/O
Memory
FFFFF
• Uses separate address space for I/O.
• Requires special instructions: IN, OUT.
I/O Overlapped
spaces
• Hardware using M/IO andW/R needed to
develop signals IORC 𝑹𝑫 𝑾𝑹 𝑰𝑶/𝑴 Signal 1M X 8
Separate spaces
0 1 0 𝑀𝐸𝑀𝑅
• and IOWC. I/O
1 0 0 𝑀𝐸MW
FFFF
0 1 1 𝐼𝑂𝑅 64K X 8 64K X 8
00000 0000
1 0 1
Memory-Mapped I/O 𝐼𝑂𝑊
• 8-bit port addresses used to access system
• I/O shares memory address space.
board device, e.g. timer and keyboard.
• Uses normal instructions: MOV, ADD, etc.
IORC and IOWC not required.
Course Teacher: Mujibur Rahman Maruf
4
 Addressing Techniques for I/O Instructions
There are two ways to specify the address of an I/O port:
• Fixed I/O Addressing (8-bit)
• The port address is within the instruction.(e.g. IN AL, 60H)
• It appears on address lines A7–A0, while A15–A8 are 00000000b.
• Used for accessing first 256 ports (00H–FFH).
• used to access system board device,( e.g. keyboard. ) MOV DX, 0378H
• Variable I/O Addressing (16-bit) IN AX, DX

• The port address is stored in the DX register.

• The full 16-bit address appears on address lines A15–A0.
• Enables access to full 64K I/O space.
• used to access serial and parallel ports, harddrives, etc.
Course Teacher: Mujibur Rahman Maruf
5
 Basic I/O
I/O
Interface
Basic Input Interface:The basic input device (to the microprocessor) is a
set of tri-state buffers(74ALS244)

The 74ALS244 tri-state buffer VCC
8-bit input port 
.
reads input from toggle 
Toggle switches 
switches and places 8-bit data are data source. 10K
74ALS244
on the CPU data bus. 1A1 1Y1
Data Bus
1A2 1Y2
A decoded SEL signal enables 1A3 1Y3
1A4 1Y4
the buffer to transfer data during 2A1 2Y1
2A2 2Y2
an IN instruction. 2A3 2Y3
2A4 2Y4
10kΩ pull-up resistors ensure SEL 1G
2G
proper logic levels for stable I/O port address decoded to SEL

input.
 Basic I/O Interface
Basic Output Interface:The basic output device (from the microprocessor) is
a set of latches.
VCC
captures output data from the
. D flip-flops hold
CPU using the OUT instruction. data from microprocessor 330

A SEL signal triggers the latch U1

to store data, which controls D0

D1
Q0
Q1

74ALS374
LEDs connected to its outputs. Data Bus D2 Q2
D3 Q3
330Ω resistors limit current, D4 Q4
D5 Q5 Light-emitting diodes emit
D6 Q6 when Q output is 0
and LEDs turn ON when output D7 Q7
OC
is logic 0
SEL
CLK
 Minimum Mode Memory Interfacing
In minimum mode, the address bus and data
bus are multiplexed on the same lines (AD0
to AD15).
• During the first clock cycle, these lines act as a
memory/IO address bus.
• For the second and third clock cycles, they
The control signals in minimum mode
function as a data bus, carrying data. are listed in table below

• Demultiplexing is the process of separating

these address and data signals for read/write
operations.

Course Teacher: Mujibur Rahman Maruf

8
 8086 Memory Organization
The 8086 microprocessor's memory address space
has distinct logical and physical organizations.
• Logical Organization: The memory is seen as a
single 1M×8 memory bank. Byte-wide storage
locations are assigned consecutive addresses from
00000H to FFFFFH.

• Physical Organization: Physically, memory is

implemented as two independent 512 Kbyte
banks: the low (even) bank and the high (odd)
bank

Course Teacher: Mujibur Rahman Maruf

9
 Address Decoding
A microprocessor can typically address a much larger memory space than a
single memory chip can cover. This is where address decoding becomes
essential.
• Purpose of Decoding: Decoding ensures that a memory device functions at
a unique section or partition of the memory map.
• Without a Decoder: Only one memory device could be connected to a
microprocessor, severely limiting its utility.
• Correcting Mismatches: A decoder corrects mismatches when the
microprocessor's address pins exceed the memory component's address pins.
For instance, the 8088 has 20 address connections, while a 2716 EPROM has
only 11.
Course Teacher: Mujibur Rahman Maruf
10
 NAND Gate Decoder
a 2K × 8 EPROM, like the 2716, being used
with an 8088 microprocessor.
• The 8088's address connections
A10−A0 are directly connected to the
EPROM's address inputs A10−A0.
• The remaining nine address pins (A19−A11 )
are connected to a NAND gate decoder.
• This decoder selects the EPROM from one of the 2K-byte sections within the
8088's 1M-byte memory system.
A simple NAND gate decoder can be used to map a memory device to a specific
address range, such as FF800H to FFFFFH
Course Teacher: Mujibur Rahman Maruf
 Using a 3-to-8 Decoder (74LS138)
For more complex memory systems, a
3-to-8 decoder like the 74LS138 is often
used.In a system with eight 2764 EPROMs for
a 64K × 8 memory section in an 8088
microprocessor:
• Address bits A19−A17 are connected to a
three-input NAND gate. When all three are
high, the NAND gate output goes low, A circuit that uses eight 2764 EPROMs for a 64K × 8
section of memory in an 8088 microprocessor-based
enabling input G2B of the 74LS138. system. The addresses selected in this circuit are
F0000H–FFFFFH.
• Input G1 is directly connected to A16.
.•For this decoder to be enabled, the first four address connections (A19−A16)
must all be high Course Teacher: Mujibur Rahman Maruf
12
 Using a 3-to-8 Decoder (74LS138)
• Address inputs C, B, and A of the 74LS138
connect to microprocessor address pins
A15−A13. These inputs determine which of
the decoder's output pins goes low, selecting
a specific EPROM.

Course Teacher: Mujibur Rahman Maruf

13
 Memory Expansion

There are two primary reasons to expand memory capacity beyond a single
device:
1. The byte-wide length is insufficient.
2. The total storage capacity isn't enough bytes.
Both needs can be met by interconnecting multiple Integrated Circuits (ICs).

Course Teacher: Mujibur Rahman Maruf

14
 Memory Expansion
Example 1: Implementing 32Kx16 EPROM
using 32Kx8 EPROMs
To implement a 32K × 16 EPROM using 32K × 8
EPROMs, you'd use two 32K × 8 chips in parallel.
• A 32K × 8 EPROM has 15 address lines
(A0−A14) (215=32K).
• A 32K × 16 EPROM also needs 15 address
lines (A0−A14).
• One 32K × 8 EPROM handles data lines D0−D7,
and the other handles D8−D15 to achieve the
16-bit wide data path.
Course Teacher: Mujibur Rahman Maruf
15
 Arithmetic Microprocessor
Example 2: Implementing 64Kx16
EPROM using 32Kx8 EPROMs
To implement a 64K × 16 EPROM
using 32K × 8 EPROMs:
• A 32K × 8 bit EPROM has 15 address
lines (A0−A14).
• A 64K × 16 bit EPROM requires 16 address lines (A0−A15) (216=64K).
• You would need four 32K × 8 EPROMs. Two chips form a 32K × 16 bank, and
the A15 address line is used to select between two such 32K × 16 banks,
effectively creating a 64K × 16 memory.

Course Teacher: Mujibur Rahman Maruf

16
 82C55 Programmable Peripheral Interface (PPI)
Pinout of 82C55 PPI

The 82C55 Programmable Group A D0

D1
PA0
PA1
Port A (PA7-PA0) and upper D2 PA2
Peripheral Interface (PPI) half of port C (PC7 - PC4)
D3 PA3
D4 PA4
D5 PA5
is a versatile interfacing D6 PA6
Group B D7 PA7
component that connects I/O Port B (PB7-PB0) and lower PB0
half of port C (PC3 - PC0) PB1
PB2
devices to a microprocessor. RD PB3
WR PB4
commonly found in PCs, I/O Port Assignments
A0
A1
PB5
PB6
PB7
RESET
often as part of an integrated A1 A0 Function CS PC0
PC1
chipset, for interfacing with 0 0 Port A PC2
PC3
0 1 Port B PC4
the keyboard and parallel 1 0 Port C VCC PC5
1 1 Command Register PC6
GND PC7
printer port
Course Teacher: Mujibur Rahman Maruf
17
 Operation Modes of 82C55
The 82C55 PPI operates in:
• Mode 0 (Simple I/O): Provides basic, unhandshaked input/output for general-
purpose parallel data transfer.
• Mode 1 (Strobed I/O): Enables handshaked input/output for synchronized
data transfer, using Port C for control signals.
• Mode 2 (Bidirectional Strobed I/O): Configures Port A for bidirectional data
flow with handshaking, suitable for bused communication.

Mode / Port Port A (PA0-PA7) Port B (PB0-PB7) Port C (PC0-PC7)

8-bit Input or Output (simple 8-bit Input or Output Divided into two 4-bit nibbles,
Mode 0
I/O) (simple I/O) each Input or Output.
8-bit Strobed Input or Output 8-bit Strobed Input or Provides handshaking signals for
Mode 1
(with handshaking) Output (with handshaking) Port A & B.
8-bit Bidirectional Strobed I/O Provides handshaking &
Mode 2 Cannot be used as Mode 2
(Port A only) interrupt control for Port A.

Course Teacher: Mujibur Rahman Maruf

18
 Programming the 82C55
Systems Design & Programming
Command Byte A (Programs ports A, B, C)
The command byte configures ports
7 6 5 4 3 2 1 0
A, B, and C as input or output and 1
Group A
Group B
selects Mode 0, 1, or 2. Port C (PC7 - PC4)
1 = input Port C (PC3 - PC0)
1 = input
It controls both Group A (Port A + 0 output 0 = output
Port A Port B
upper Port C) and Group B (Port 1 = input 1 = input
0 = output 0 = output
B + lower Port C). Mode Mode
00 = mode 0 0 = mode 0
BSR mode is used to set or reset 01 = mode 1 1 = mode 1
1x = mode2
individual bits of Port C only,
Command Byte B (Sets or resets any bits in port C)
without affecting other ports. 7 6 5 4 3 2 1 0
0 x x x
It is selected when bit 7 of the
Bit set/reset
command byte is 0. 1 = set
0 = reset
Selects a bit
 Handshaking
Handshaking is a technique used to coordinate data transfer between the
CPU and slower I/O devices.It uses control signals to confirm that both the
sender and receiver are ready before data is sent or received.This avoids data
corruption, especially when devices operate at different speeds
Input Handshaking Example – Keyboard
When you press a key, the keyboard sends data to the 82C55 and signals it's
ready.The 82C55 stores the key data and notifies the CPU, which then reads it safely.
Output Handshaking Example – Printer
The CPU sends a character to the printer via 82C55.
The printer sends an ACK after receiving it, telling the CPU it's ready for the next one.
Handshaking Input (Mode 1 Strobe Input)
82C55: Mode 1 Strobed Input
Mode 1 Port A Timing Diagram

PORTA
STB
INTE
A PC4 STB
PC5 IBF
IBF (Buffer full)

PC3 INTR
PC6+7 I/O INTR (Interrupt request)

Mode 1 Port B RD
PORT B
INTE
B PC2 STB Port
PC1 IBF
Data strobed Data read by
INTR into port microprocessor
PC0
 Handshaking Input (Mode 1 Strobe Input)
1. STB (Strobe):An external device pulls STB low → this tells the 82C55 to latch
the incoming data.Data must be valid before STB goes low and held until just after it
returns high.
2. IBF (Input Buffer Full):After STB rises, IBF goes high to indicate that valid
data is latched in the input port.It stays high until the CPU reads the data.
3. INTR (Interrupt Request):If interrupts are enabled (via INTE), the rising edge
of IBF causes INTR to go high.This signals the CPU that input data is ready to be
read.
4. RD (Read):The CPU responds by pulling RD low to read the data from the port.
After the read, IBF and INTR go low, completing the cycle.
Handshaking Output (Mode
I/O 1 Strobe output)
Mode 1 Port A
Timing Diagram
PORTA
INTE WR
A PC6 ACK
PC7 OBF OBF (Buffer full)

PC3 INTR INTR (Interrupt

request)
PC4+5 I/O

Mode 1 Port B ACK

PORT B
INTE Port
B PC2 ACK
PC1 OBF
Data sent Data removed
PC0 INTR to port from port
Handshaking Output (Mode 1 Strobe output)
1. WR (Write):The CPU places valid data on the bus and pulls WR low to
latch data into the output port.
2. OBF (Output Buffer Full):After WR goes high, OBF goes low to indicate
that the port holds valid output data.It remains low until the external device
acknowledges the data.
3. ACK (Acknowledge):When the external device receives the data, it pulls
ACK low.This tells the 82C55 that the data was accepted.
4. INTR (Interrupt Request):If interrupts are enabled (via INTE), when
ACK occurs and OBF goes high again, INTR is triggered.
This notifies the CPU that the device is ready for the next data.