Lab Report 05

Design and Analysis of a Current Mirror

Date: 05-May-2025
Introduction
Current mirrors are fundamental building blocks of analog integrated circuits.
Operational amplifiers, operational transconductance amplifiers and biasing
networks are examples of circuits that are composed of current mirrors. The design of
current mirrors is therefore an important aspect of successful analog circuit design.

Objectives
Design, simulate, and test various current mirror circuits..

Tasks
1. NMOS Current Mirror
1.1. Introduction
An NMOS current mirror is a basic analog circuit that uses two matched NMOS
transistors to replicate a reference current from one branch of the circuit to
another, ensuring stable and consistent current flow. In its simplest form, one NMOS
transistor is diode-connected (its gate and drain are tied together) to set the
reference current, while the second transistor has its gate connected to the first
and its source grounded, allowing it to mirror the input current at its drain. This
configuration is widely used in analog integrated circuits for biasing and as a
building block in amplifiers, as it provides precise and reliable current sources or
sinks, which are essential for predictable circuit behavior.

1.2. Components Used

The following components were used in the schematic:
• Two NMOS transistors (M1 and M2)
• DC voltage and Current sources (for IREF and VOUT)
• Ground connections (GND)
• Wires (for interconnections)

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 1.3. Schematic Diagram

Figure 1: NMOS Current Mirror Schematic

1.4. Analyses and Results

1.4.1. DC Analysis
A DC sweep analysis was performed by varying Vout and observing the output
current (ID2) through M2. The resulting plot of ID2 versus Vout was analyzed to
study how well the output current mirrors the reference current and to identify
the output voltage range where the current mirror operates ideally (i.e., where
ID2 remains constant, indicating saturation). Additionally, node voltages and
DC operating points were annotated to further understand the circuit’s
behavior under different biasing conditions.

1.4.2. Observation
This graph shows the relationship between the output voltage (Vout) and the
output current (ID) of the NMOS current mirror during DC analysis. Initially, as
Vout increases from zero, the output current (ID) rises rapidly, indicating that
the output transistor (M2) is transitioning from the cutoff region to the saturation
region. Once Vout reaches a certain threshold (around 0.5 V in this case), the
current levels off and becomes nearly constant, demonstrating the ideal
current mirror behavior where the output current remains stable and
independent of Vout. This flat region confirms that the current mirror is
effectively mirroring the reference current, providing a stable bias current as
intended.

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 Figure 2: ID vs VOUT Graph

2. NMOS Current Mirror with PMOS Active Load

2.1. Introduction
NMOS current mirror with a PMOS active load is a configuration where the basic
NMOS current mirror circuit is enhanced by replacing the passive resistor load with
a PMOS transistor operating in saturation as an active load. In this setup, the NMOS
transistors form the core current mirror, with one NMOS diode-connected to set the
reference current and the other providing the mirrored output. The PMOS active
load improves the output resistance and increases the voltage gain of the circuit
by providing a high-impedance path at the output.

2.2. Components Used

The following components were used in the schematic:
• Two NMOS transistors (M1 and M2)
• One PMOS transistor
• DC current source (for IREF)
• Ground connections (GND)
• Wires (for interconnections)

2.3. Schematic Diagram

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 Figure 3: NMOS current mirror with a PMOS active load Schematic

2.3. Analyses and Results

2.3.1. DC Analysis
In this DC analysis, a DC sweep was performed by varying the supply voltage
(VDD) and measuring the output current (ID) of the NMOS current mirror with a
PMOS active load. The purpose of this simulation was to observe how the
output current responds as VDD increases, thereby evaluating the current
mirror’s ability to maintain a stable, mirrored current under different supply
conditions.

2.3.2. Observation
The resulting graph of ID versus VDD shows how the output current responds as
the supply voltage increases. Initially, at low VDD, the current remains near zero
because the transistors are not yet properly biased. As VDD increases past the
threshold voltage, the current rises sharply and then gradually saturates,
indicating that the current mirror is now operating in its active region and the
PMOS active load is providing a high output impedance. This analysis
demonstrates the minimum VDD required for proper current mirror operation
and highlights the region where the circuit delivers a stable, mirrored current,
confirming the effectiveness of the PMOS active load in maintaining a
consistent output current over a range of supply voltages.

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 Figure 4: ID vs VDD Graph for NMOS current mirror with PMOS active load

3. PMOS Current Mirror with NMOS Active Load

3.1. Introduction
A PMOS current mirror with NMOS active load is an analog circuit configuration
where two matched PMOS transistors form the core current mirror, and an NMOS
transistor is used as an active load at the output. In this setup, one PMOS transistor
is diode-connected to set the reference current, while the other PMOS transistor
mirrors this current to the output branch. The NMOS active load, operating in
saturation, replaces the traditional resistive load and provides a high output
impedance, which improves current matching and enhances the voltage gain of
the circuit.

3.2. Components Used

The following components were used in the schematic:
• Two PMOS transistors (M1 and M2)
• One NMOS transistor
• DC voltage and Current sources (for IREF and VOUT)
• Ground connections (GND)
• Wires (for interconnections)

3.3. Schematic Diagram

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 Figure 5: PMOS Current Mirror with NMOS active load

3.4. Analyses and Results

3.4.1. DC Analysis
In the DC analysis of the PMOS current mirror with an NMOS active load, a DC
sweep was performed by varying the supply voltage (VDD) and measuring the
drain current (ID) of the output PMOS transistor.

Figure 6: ID vs VDD plot for PMOS current mirror with NMOS active load

3.4.2. Observation
In the above plot, the drain current (ID) of the output PMOS transistor is plotted
against the supply voltage (VDD). At low VDD values, the current remains close
to zero because the transistors are not yet properly biased. As VDD increases
past a certain threshold (around 0.3–0.4 V), the current starts to rise sharply,
indicating that the transistors are entering their active regions. Beyond this
point, the current continues to increase with VDD, reflecting the combined
effects of the current mirror operation and the NMOS active load. The curve

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 does not fully flatten, which suggests that the output current is still somewhat
dependent on VDD, likely due to channel length modulation and the
characteristics of the active load.

4. Biasing of Differential Amplifier

4.1. Introduction
To bias the differential amplifier using an NMOS current mirror, as shown in the
attached schematic, the current mirror circuit (formed by two or more NMOS
transistors at the bottom left, typically labeled as M0 and M1) sets a precise and
stable tail current for the differential pair (M2 and M3). The reference current is
established by applying a known voltage to the gate of the reference NMOS
transistor (M0), which is mirrored to the other transistor (M1) through their
connected gates and sources. This mirrored current (ITAIL) then flows through the
source node shared by the differential pair, ensuring both NMOS input transistors
operate in saturation and receive a constant bias current regardless of input
voltage variations.

4.2. Components Used

The following components were used in the schematic:
• NMOS transistors (differential pair and current mirror)
• PMOS transistors (active load/current mirror)
• DC current sources (tail current source and biasing)
• Voltage sources (VDD, VSS, VB, VIN+, VIN-)
• Ground (gnd)
• Wires/nets for interconnections
• Test points (for outputs: VOUT+, VOUT-, ITAIL)
• Labels/nodes for signal identification

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 4.3. Schematic Diagram:

Figure 7: Differential Pair with current mirror load

4.4. Analyses and Results

4.4.1. Transient Analysis
In the transient analysis of this NMOS differential amplifier with PMOS active load
(as shown in your schematic), a small time-varying differential input signal
(typically a sine wave, e.g., 1 mV at 10 kHz) is applied to VIN+ and VIN-. The
simulation is run over a time interval (such as 0 to 1 ms) to observe how the
output voltages (VOUT+ and VOUT-) respond in real time. This analysis allows
you to verify that the amplifier produces amplified, out-of-phase output signals
corresponding to the differential input, confirming that the circuit is functioning
correctly, remains in its linear region, and is free from distortion or instability.

4.4.2. DC Analysis
In the DC analysis of this NMOS differential amplifier circuit, the drain current
(ID) of the differential pair transistor (such as M2) is measured while sweeping
the supply voltage (VDD) over a range of values. This is done to verify that the
circuit is properly biased and that the transistors operate in the saturation region
across the intended VDD range.

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 Figure 8: ID vs VDD plot for Differential Pair with current mirror load

4.4.3. Observation
The plot indicates that for low values of VDD, the current remains near zero, as
the transistors are not yet turned on. Once VDD exceeds a certain threshold
(the sum of the threshold voltages and overdrive voltages required to bias the
differential pair and current source in saturation), the drain current rapidly
increases and then plateaus, reflecting the activation and proper biasing of
the differential amplifier.

5. Current Multiplier Circuit

5.1. Multiplying factor 2
For doubling the output current, the width of the output transistor is altered as
follows:
5.1.1. Schematic Diagram

Figure 9: Changed width of output transistor for multiplying factor 2

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 5.1.2. DC Analysis
After selecting width of output transistor for which IOUT is 2 times IREF, following
dc results have been obtained:

Figure 10: ID vs VOUT plot for multiplying factor 2

Figure 11: DC Operating Points for multiplying factor 2

5.1.3. Observation

We see that the relation isn’t exactly followed here in doubling

the current because of the effect of channel length modulation.

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 5.2. Multiplying factor 8
For increasing the output current by 8, the width of the output transistor is altered
as follows:
5.2.1. Schematic Diagram

Figure 12: Changed width of output transistor for multiplying factor 2

5.2.2. DC Analysis
After selecting width of output transistor for which IOUT is 8 times IREF, following
dc results have been obtained:

Figure 13: ID vs VOUT plot for multiplying factor 8

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 Figure 14: DC Operating Points for multiplying factor 8

5.2.3. Observation

We see that the relation isn’t exactly followed here in doubling

the current because of the effect of channel length modulation.

5.3. Multiplying factor 0.5

For making output current half of IREF, the width of the output transistor is altered as
follows:
5.3.1. Schematic Diagram

Figure 15: Changed width of output transistor for multiplying factor 0.5

5.3.2. DC Analysis

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 After selecting width of output transistor for which IOUT is 0.5 times IREF, following
dc results have been obtained:

Figure 16: ID vs VOUT plot for multiplying factor 0.5

Figure 17: DC Operating Points for multiplying factor 0.5

5.3.3. Observation

We see that the relation isn’t exactly followed here in doubling

the current because of the effect of channel length modulation.

5.4. PMOS doubling current circuit

For generating a current of 2u across output NMOS, we swept RD with IOUT and
choose the value of RD which in this case was 365Kohm.

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 Figure 18: PMOS current doubling circuit

Figure 19: ID vs VDD plot for PMOS current doubling circuit

5.4.1. Observation

We see that the relation isn’t exactly followed here in doubling

the current because of the effect of channel length modulation.

Conclusion
This lab focused on the design and implementation of a current mirror for stable
biasing. The current mirror, consisting of matched transistors, ensures consistent

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current flow through the differential pair, enhancing the amplifier's performance. This
exercise emphasized the importance of precise biasing in achieving reliable and
predictable amplifier behavior.

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