Basic Processing Unit

Module 5
overview
• Instruction Set Processor (ISP): which executes
machine instruction
Fetching
Decoding
execution
• Central Processing Unit (CPU)
• A typical computing task consists of a series of
steps specified by a sequence of machine
instructions that constitute a program.
• An instruction is executed by carrying out a
sequence of more rudimentary operations.
Some Fundamental Concepts
• Processor fetches one instruction at a time and
perform the operation specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• Processor keeps track of the address of the
memory location containing the next instruction
to be fetched using Program Counter (PC).
• Instruction Register (IR)
 Executing an Instruction
1. Fetch the contents of the memory location pointed to
by the PC. The contents of this location are loaded into
the IR (fetch phase).
IR ← [[PC]]
2. Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
3. Carry out the actions specified by the instruction in the
IR (execution phase).
Processor Organization
• Transfer a word of data from one processor
register to another or to the ALU.
• Perform an arithmetic or a logic operation
and store the result in a processor register.
• Fetch the contents of a given memory
location and load them into a processor
register.
• Store a word of data from a processor register
into a given memory location.
 Register Transfers
Internal processor
b us
R i in

Ri

R i out

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Example
• [R4] ← [R1]
• Enable the output of register R1 by setting
R1out to 1. this places the contents of R1 on
the processor bus.
• Enable the input of register R4 by setting R4in
to 1. This loads data from the processor bus
into register R4.
 Register Transfers
• All operations and data transfers are controlled by the processor clock.

Tri state
gate
M
U
X

Edge
triggered
D flip
flop
Figure 7.3. Input and output gating for one register
bit.
Performing an Arithmetic or Logic
Operation
• The ALU is a combinational circuit that has no internal
storage.
• ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
• The sequence of operations to add the contents of
register R1 to those of R2 and store the result in R3
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
Fetching a Word from Memory
• Address into MAR; issue Read operation; data into MDR.

Figure 7.4. Connection and control signals for register

MDR.
 Fetching a Word from Memory
• The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).
• Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
Storing a word in memory
• Move R2, (R1)

R1out , MARin
R2out , MDRin , write
MDRoutE , WMFC
Execution of a Complete Instruction
Execution of Branch Instructions
Multiple-Bus Organization
Hardwired Control
 Overview
• To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
• Two categories:
• hardwired control
• microprogrammed control
• Hardwired system can operate at high speed;
but with little flexibility.
Control Unit Organization
CL Control
Cloc K counte
step
k r

Externa
l input
Decoder s
I /encode
R
r Conditio
n code
s

Control
signals

Figure 7.10. Control unit

organization.
Detailed Block Description
 Generating Zin
• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Ad
d

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
 Generating End
• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
A Complete Processor
Microprogrammed Control
 Overview
• Control signals are generated by a program similar to machine language
programs.
• Control Word (CW); microroutine; microinstruction
Overview
 Overview
• Control store

One function
cannot be carried
out by this simple
organization.
 Overview
• The previous organization cannot handle the situation when the control unit
is required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
• Use conditional branch microinstruction.
Addres Microinstructio
s n
0 P ou , MA i , Read Select4 Add Z i
C t R n , , , n
1 Zou , P i , Y i , WM C
MD C , IR
t n n F
2 ou i
R t n
3 Branc t startin addres o appropriat microroutin
. . . . . . . . . . . .h. . . . . . . o
. . . g. . . . . . . .s. . . . . . . .f . . e. . . . . . . . . . . .e. . . . . . . . . . . . . .
2 I N=0 then branc t microinstructio 0
5 fOffset-field-of-
, h o n
2 ou , SelectY, Add Z i
6 IR t , n
2 Zou , P i , En
7 t C n d

Figure 7.17. Microroutine for the instruction

Branch<0.
 Overview
Externa
l input
s
Starting
branch Conditio
I and
generato
address n code
R s
r

Cloc μPC
k

Contro
C
l stor
e W

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.