SWITCHING THEORY AND LOGIC DESIGN LABORATORY

REPORTS

Submitted by

Harsh panchal
Roll number: 22PHC1R26
M.Sc. (Tech) Engineering physics

2nd year, III semester.

Submitted in partial fulfillment of the requirement for the degree

of Master Of Science (Technology) in Engineering Physics

Under the supervision of

Dr. Rakesh Kumar Rajaboina

Assistant Professor

Department of physics
National Institute of Technology Warangal
Warangal – 506004, Telangana, India.
Date of submission: 6-12-2023

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Drive link:

https://drive.google.com/drive/folders/1V89S49OFnG1azJJZ_0RRT
JxdB9LCNBl?usp=drive_link
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Department of physics
National Institute of Technology Warangal
Warangal, TS – 506004.

Certification of approval
This is to certify that the work contained in this report of switching
theory and logic design laboratory is submitted by Mr. Harsh Panchal (Roll No:
22PHC1R26) of M.Sc. Tech Engineering Physics to the department of physics,
National Institute of Technology Warangal, for the partial fulfillment of the
requirements of the degree of master of science & Technology Engineering
Physics.
He has carried out his work under my supervision and guidance during
the odd semester of 2023.

Dr. Rakesh Kumar Rajaboina

Assistant Professor
Department of Physics

NIT Warangal.

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…………………………………………INDEX…………………………………………………..
Sr. Experiment Page Date Signatur
No No. e

1 Identify IC 7404, IC 7408, IC 7432, IC 7402, 17/8

IC 7400 integrated circuits and its
configuration

2 Check the basic gate input output and its 31/8

logic operation also.

3 Construct basic gate and check its logic 4/9

operation in Deeds software using universal
gates.

4 Construct logic circuit design that can 11/9

detect prime number.

5 Construct half adder using basic gates and Full 5/10

adder using basic gates, HA block and half
adder and full adder using NAND gate as well
as NOR gate.

6 Construct 2-3 bit multiplier, 4-bit 12/10

adder subtractor, BCD adder, CLA
adder.

IC7483 (binary full adder)

7 Construct 3-bit comparator, 4*1 MUX, 1*4 20/10

De MUX, full adder implementation using De-
MUX.

IC7485 (4-bit comparator)

IC74151 (MUX)

8 7-bit humming code detection and correction, 02/11

8- bit tri state bus, IC 74280 parity circuit.

IC 74280 (parity checker)

9 Construct up and down counter, mod 5 16/11

counter, mod 10 counter, 3-bit pre-settable
counter.

IC74163 (pre-settable synchronous 4-bit counter)

10 24 hours clock, shift register counter 20/11

(johnson and ring counter, self starting ring
counter.

IC74148 priority encoder

11 CALCULATOR USING GATES 09/11

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17, August – 2023

Lab session 1:

Identify IC 7404, IC 7408, IC 7432, IC 7402, IC 7400 integrated circuits and its configuration
and check its pin according to its number.

Lab Work:

1) IC 7432 (OR gate)

IC 7432 is a digital integrated circuit (IC) that contains four 2- input OR gates. The OR gate
performs logical OR operation. Each gate has three terminals, two input and one output. The
7432 is part of 74xx series, which is family of logic gates. Its design to operate with a power
supply range of 2.0 V to 6.0V. The inputs include clamp diodes.

) IC 7408 (AND gate)

IC 7408 is a digital Integrated circuit (IC) that contains four two-input AND gates. Each gate
has one output, two input and three pins. The 7408 IC can be used to create basic functions
and complex logic operation. The 7408 IC is design for operation with a power supply range
of 2.0 to 6.0. It becomes in a 14-pin DIP package.

3) IC 7404 (NOT gate)

The IC 7404 is a high-speed CMOS logic quad NOT gate. It’s also known as a hex inverter. It
contains six independents NOT gates in one package. Each gate has one input and output.
A NOT gate outputs the Boolean inverse of the
applied input.

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4) IC 7400 (NAND gate)

The IC 7400 is a 14-pin logic gate integrated circuit (IC) that contains four two-input NAND
gates. Each NAND gate in the IC 7400 requires two input pins and provides one output pin.
The remaining two pins are for power and ground. The IC 7400 is the most widely used TTL
(transistor-transistor logic) device in the world. It’s popular because any logic gate function
can be created using NAND gates. It called universal gate also.

5) IC 7402 (NOR gate)

The IC 7402 is a device that contains four independents gates that perform the logic NOR
function. It has 14 pins and two inputs. The 7402 uses advances silicon-gate COMS
technology to achieve operating speeds similar to HC gates with low power consumption of
standard CMOS integrated circuits.

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Check the basic gate input output and its logic operation
 also. Lab work:
1) AND gate
The AND gate is a basic digital logic gate that implements logical conjunction ( ∧) from mathematical
logic AND gate behaves according to the truth table. A high output (1) results only if all the input to
the AND gates are high (1). If not all inputs to the AND
gate are high, low output results.

Here, truth table is given how it performs the logic operation how it become high or low. And how it
gives output with respective to its input.

A B Y

0 0 0

0 1 0
2) OR 1 0 0

gate 1 1 1

INPUT OUTPUT
The OR gate is a basic digital logic gate that implements logical disjunction from mathematical logic
OR gate behaves according to the truth table. A high output (1) results only if one of the inputs to the
OR gates is high (1). If not all inputs to the OR gate are high, low output results.

Here, truth table is given how it performs the logic

operation how it become high or low. And how it gives
output with respective to its input.

A B Y

0 0 0

0 1 1

1 0 1

1 1 1
INPUT OUTPUT

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3) NAND gate
 The NAND gate is a basic digital logic gate that implements inverted logical conjunction ( ∧) from
mathematical logic NAND gate behaves according to the truth table. A low output (0) results only if
all the input to the NAND gates is high (1). If not all inputs to the AND gate are high, high output
results. It is inverted of AND gate connected by NOT gate.

Here,

truth table is given how it performs the logic operation how it become high or low. And how it gives
output with respective to its input.

A B Y

0 0 1

0 1 1
4) NOR gate
1 0 1

INPUT OUTPUT 1 1 0

The NOR gate is a basic digital logic gate that implements inverted logical disjunction from
mathematical logic NOR gate behaves according to the truth table. A low output (0) results only if
one of the inputs to the NOR gates is high (1). If not all inputs to the NOR gate are high, high output
results. It is inverted of AND gate connected by NOT gate.

Here,

truth table is given how it performs the logic operation how it become high or low. And how it gives
output with respective to its input.

A B Y

0 0 1

0 1 0

1 0 0
–––
1 1 0
INPUT OUTPUT

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5) X-OR gate
The XOR gate is a hybrid digital logic gate that implements exclusive disjunction from mathematical
logic X-OR gate behaves according to the truth table. A low output (0) results only if all the input to
the X-OR gates is high (1) or low (0). If not all inputs to the X-OR gate are high, low output results.
 Ab

ove configuration shows that how exclusive OR gate is created using AND, OR and NOT gates.
Here, truth table is given how it performs the logic operation how it become high or low. And how it
gives output with respective to its input.

0 1 1

1 0 1

1 1 0

6) X-
NOR gate

INPUT OUTPUT

A B Y

0 0 0
The X-NOR gate is a hybrid digital logic gate that implements inverted exclusive disjunction from
mathematical logic X-NOR gate behaves according to the truth table. A high output (1) results only if
all the input to the X-NOR gates is high (1) or low (0). If not all inputs to the X-NOR gate are high, low
output results. It is inverted of AND gate connected by NOT gate.

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11
Here, truth table is given how it performs the logic operation how it become high or low. And how it
gives output with respective to its input.

INPUT OUTPUT

––– 7)
NOT gate
 A B Y

0 0 1

0 1 0

1 0 0

1 1 1

The NOT gate is a basic digital logic gate that implements inverts input. mathematical logic NOT gate
behaves according to the truth table. A high output (1) results only if all the input to the NOT gates is
low (0). If not input to the NOT gate is high, low output results. It need only one logical input either
high or low.

Here, truth table is given how it performs the logic operation how it become high or low. And how it
gives output with respective to its input.

INPUT OUTPUT

0 1

1 0

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31st august-2023.

Lab session 2:
Construct basic gate and check its logic operation in Deeds software using universal gates
(NOR gate and NAND gate).

Lab work:
Basic gates using NAND gate.

1) NOT gate
To construct NOT gate we have to connect the two input terminals of NAND gate to
form a single input terminal of the NOT gate, and the output of the NOT gate is taken from
the output terminal when both are the same input so if it will perform same output for AND
gate and after it inverts the output. This how NOT gate logic works in universal gate
configuration. Below the diagram shows the NOT gate using NAND gate.
If input is given by (A) then, we will get
output by (A’). if input is high then
output is
low and if input is low then output is
high.

2) AND gate
To construct NAND gate, we have to connect the two different inputs to the NAND gate to
form a signal to the input terminal and one output must be connected to another NAND
gate which is used as NOT gate. Now input A and B is given as input. It performs first NAND
operation and then it will perform NOT operation. This how AND gate logic works in
universal NAND gate configuration. Below the diagram shows the AND operation using
NAND gate.

If input is (A) and (B),

Then, output = (AB)’ …….(1)

Final output is = ((AB)’)’

= AB

3) OR gate
To construct OR gate, we have to connect input A and B individual with NOT gate and that
output must be connected with the NAND gate. Now input A and B are inverted since this
NAND gate performs NOT operation and we will get inverted output and that output is
connected to NAND, according to de-morgans theorem, at the end we get OR gate, this
how OR gate configuration works. below the diagram shows the OR operation using NAND
gate.

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input A, input B

output = ((A’) (B)’)’

= (A+B)

according de-morgan theorem.

4) NOR gate
To construct NOR gate, we have to connect input A and B individual with NOT gate and that
output must be connected with the NAND gate and that output again connected to the
NAND gate. Now input A and B are inverted since this NAND gate performs NOT operation
and we will get inverted output and that output is connected to NAND, according to de
morgans theorem, at the end we get NOR operation, this how NOR gate configuration works.
below the diagram shows the NOR operation using NAND gate.
input A, input B

output = ((A’) (B)’)’

final output = (A+B)’

according de-morgan theorem.

according de-morgan theorem.

5) BUFFER gate
To construct BUFFER gate, we have to connect input A NOT gate and that output must be
connected with the NAND gate. Now input A is inverted since common NAND gate performs
NOT operation and we will get inverted output twice, at the end we get output which we’ve
given as input, this how BUFFER gate configuration works. below the diagram shows the
BUFFER operation using NAND gate.

input A,

output = (A’)’

final output = A

6) XOR gate
To construct XOR gate, we have to connect four NAND gate as shown in figure. The inputs A
and B are passed through a NAND gate. The output is then passed through another NAND
gate along with the input A. finally, the output of the second NAND gate is passed through a
third NAND gate along with the input B. the final output of the third NAND gate represents
the XOR of input A and B.

This is how XOR gate configuration works. Below circuit diagram shows the XOR operation
using NAND gate.

₈Here, input is A and B

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we are getting output Y = A ⊕ B

output Y = A’B + B’A

7) XNOR gate
To construct XNOR gate, we have to connect five NAND gate as shown in figure. XNOR gate
is a logic gate that can have infinite number of inputs and only one output. It gives a high
output only if all the inputs are the same either 0 or 1. The output of an XNOR gate is low
when the inputs are not equal. The
output or one of the inputs can be
inverted to convert the XOR gate to
an XNOR gate.

This is how XOR gate configuration

works. Below circuit diagram shows
the XOR operation using NAND gate.
Here, input is A and B

we are getting output Y = A ⊙ B

output Y = A’B + B’A

basic gates using universal NOR gate.

1) NOT gate
To construct NOT gate we have to connect the two input terminals of NOR gate to
form a single input terminal of the NOT gate, and the output of the NOR gate is taken from
the output terminal when both are the same input so if it will perform same output for OR
gate and after it inverts the output. This how NOT gate logic works in universal NOR gate
configuration. Below the diagram shows the
NOT
gate using NOR gate.

If input is given by (A) then, we will get

output by
(A’). if input is high then output is low and if
input is low then output is high.

2) AND gate
To construct AND gate, we have to connect the two different inputs A and B common
individual to the NOR gate which will perform NOT operation and it connected to again NOR
gate. Now input A and B is given as input. It performs first NOT operation and then it will
perform NOR operation. Applying de-morgan theorem we will get AND gate.

This how AND gate logic works in universal NOR gate configuration. Below the diagram
shows the AND operation using NOR gate.

If input is (A) and (B),

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Then, output = (A’ + B’)’

Final output is = (A’B’)’

= AB

Applying de-morgans theorem.

3) OR gate
To construct OR gate, we have to connect input A and B individual applied to NOR gate and
that output must be connected with the NOR gate. Now input A and B are added and
inverted since this NOR gate performs NOT operation and we will get inverted output and
that output is connected to NOR at the end we get OR gate, this how OR gate configuration
works. below the diagram shows the OR operation using OR gate.
input A, input B

output = ((A+B)’)’

= A+B

4) NAND gate
To construct NAND gate, we have to connect the two different inputs A and B common
individual to the NOR gate which will perform NOT operation and it connected to again NOR
gate. Now input A and B is given as input. It performs first NOT operation and then it will
perform NOR operation, again it is connected to NOR gate so we will get inverted NOT gate.
Applying de-morgan theorem we will get AND gate.

This how AND gate logic works in universal NOR gate configuration. Below the diagram
shows the AND operation using
NOR gate.

Then, output = ((A’ + B’)’)’

Final output is = (A’B’)’

= AB

Applying de-morgans theorem.

5) BUFFER gate
To construct BUFFER gate, we have to connect input A NOR gate as NOT gate and that
output must be connected with the NOR gate. Now input A is inverted since common NOR
gate performs NOT operation and we will get inverted output twice, at the end we get
output which we’ve given as input, this how BUFFER gate configuration works. below the
diagram shows the BUFFER operation
using NAND gate.

output = (A’)’

final output = A

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6) XNOR gate
To construct XNOR gate, we have to connect four NOR gate as shown in figure. The inputs A
and B are passed through a NOR gate. The output is then passed through another NOR gate
along with the input A. finally, the output of the second NOR gate is passed through a third
NOR gate along with the input B. the final output of the third NOR gate represents the XNOR
of input A and B.

This is how XNOR gate configuration works. Below circuit diagram shows the XNOR
operation using NOR gate.

Here, input is A and B

we are getting output Y = A ⊙ B

output Y = AB + A’B’
 or Y = (A’B + B’A)’

7) XOR gate
To construct XNOR gate, we have to connect five NOR gate as shown in figure. XOR gate is a
logic gate that can have infinite number of inputs and only one output. It gives a high output
only if all the inputs are the same either 0 or 1. The output of an XOR gate is low when the
inputs are not equal. The output or one of the inputs can be inverted to convert the XOR
gate to an XOR gate.

This is how XOR gate configuration works. Below circuit diagram shows the XOR
operation using NOR gate.

Here, input is A and B

we are getting output Y = A ⊕ B

output Y = A’B + B’A

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th
11 September-2023

Lab session 4:
Construct logic circuit design that can detect prime
number. Lab Work:
Prime number detection is a minimized (SOP) 0 0 1 1
A’B’
combinational logic circuit to detect if a BCD digit is
prime (0,1,2,3,5,7,11,13). A’B 0 1 1 0

For prime number the logic circuit design will come 0 1 0 0

AB
out high (1), and for rest number the logic circuit will
give low (0) output. By solving following truth-table AB’ 0 0 1 0
we can convert these truth table into Karnaugh map.

Karnaugh map is given by,

C’D’ C’D CD CD’ A B C D Y num
 0 0 0 0 0 0 1 0 0 0 0 8

0 0 0 1 0 1 1 0 0 1 0 9

0 0 1 0 1 2 1 0 1 0 0 10

1 0 1 1 1 11
0 0 1 1 1 3

1 1 0 0 0 12
0 1 0 0 0 4
1 1 0 1 1 13
0 1 0 1 1 5

1 1 1 0 0 14
0 1 1 0 0 6
1 1 1 1 0 15
0 1 1 1 1 7

By solving above Karnaugh map is the Boolean algebra looks like,

Y = A’B’C + A’BD + BC’D + B’CD

Y = A’B’C + BC’D + D ( B⊕C )

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th
5 October – 2023
 Lab session 5:
Construct half adder using basic gates.

Construct Full adder using basic gates, HA block.

Construct half adder and full adder using NAND gate as well as NOR gate.

Lab Work: HALF ADDER

The simplest adder, called a half adder, adds two 1-bit operands X and Y producing a 2-bit
sum. The sun can change range from 0 to 10, which requires 2-bit expression. The low-order
bit of the sum may be named S(sum) and the high-order bit may be named as Co (carry out).
We can write Boolean equation to solve the half adder 0 0 0 0
circuit. By solving the truth table and Karnaugh map, 0 1 0 1

Truth Table 1 0 0 1

A B Co S 1 1 1 0

SUM B’ B Co B’ B

A’ 0 1 A’ 0 0

A 1 0 A 0 1

We will get the Boolean algebra for SUM,

Y = A’B + AB’

OR Y = A⊕B

And Boolean algebra for

carry out,

Y = AB

(a) HA using gate (b) HA block (c) HA using basic gate

(d) HA using NOR gate Page | 19
(e) HA using NAND gate
FULL ADDER:

To add operands more than one bit, we must provide for carries between bit positions. The
building block for this operation is called a full adder besides the addend bit inputs X and Y, a
full adder has a carry bit input, Cin. The sum of three inputs can range from 0 to 3 which can
expressed just two output bits, S and Cout, having the following equations. We can write
Boolean equation to solve the half adder circuit.

By solving the truth table and Karnaugh map, We will get the Boolean algebra for Cout, Y = AB + BC
SUM B’C’ B’C BC BC’ + AC

A’ 0 1 0 1 A B Cin Co S

A 1 0 1 0 0 0 0 0 0

0 0 1 0 1

0 1 0 0 1
Co B’C’ B’C BC BC’
0 1 1 1 0
A’ 0 0 1 0
1 0 0 0 1
A 0 1 1 1
1 0 1 1 0

1 1 0 1 0
We will get the Boolean algebra for SUM, Y = A’B’C +
1 1 1 1 1
A’BC’ + AB’C’ + ABC

OR Y = A⊕B⊕C
 Page | 20
Extra work:
Construct two-bit parallel adder using full adder block, Four bit parallel adder using full
adder block, four bit parallel adder using four bit adder block, using one bit input, four bit
input, seven segment display.
 12th
October – 2023.
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Lab session 6:
Construct 4-bit adder and subtractor using XOR gate and full adder blocks. Construct 2-bit

multiplier and 3-bit multiplier using basic gates and HA block and FA block. Construct BCD

adder with correction circuit.

Construct CLA adder using Floyd book logic.

Lab Work: 4-bit adder/subtractor using XOR

As shown in the figure, the first full adder has a control line directly as its input(input carry
Cin), The input A0 (The least significant bit of A) is directly input in the full adder. The third
input is the exor of B0 and K. The two outputs produced are Sum/Difference (S0) and Carry
(C0).

If the value of K (Control line) is 1, the output of B0(exor)K=B0′ (Complement B0). The
operation would be A+(B0′). Now 2’s complement subtraction for two numbers A and B is
given by A+B’+Cin. This suggests that when K=1, the operation being performed on the four
bit numbers is subtraction.

Similarly, If the Value of K=0, B0 (exor) K=B0. The operation is A+B which is simple binary
addition. This suggests that When K=0, the operation is performed on the four-bit numbers
in addition.

Then C0 is serially passed to the second full adder as one of its outputs. The sum/difference
S0 is recorded as the least significant bit of the sum/difference. A1, A2, A3 are direct inputs
to the second, third and fourth full adders. Then the third input is the B1, B2, B3 EXOR with K
to the second, third and fourth full adder respectively. The carry C1, C2 are serially passed to
the successive full adder as one of the inputs. C3 becomes the total carry to the
 sum/difference. S1, S2, S3 are recorded to form the result with S0.

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2-bit and 3-bit multiplier using basic gates and HA and FA

• Using basic gates.

2-bit multiplier where A and B are the input having binary number A1A0 and B1B0. To
multiply and A and B using basic gate, we have to construct its truth table and have to
solve
it by Karnaugh map. 0 1 1 0 0 0 1 0
From the truth table we can construct Karnaugh 0 1 1 1 0 0 1 1
Truth Table
1 0 0 0 0 0 0 0
INPUT (A) INPUT (B) MULTIPLICATION
1 0 0 1 0 0 1 0
A1 A0 B1 B0 P3 P2 P1 P0
1 0 1 0 0 1 0 0
0 0 0 0 0 0 0 0
1 0 1 1 0 1 1 0
0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0
1 1 0 1 0 0 1 1
0 0 1 1 0 0 0 0
1 1 1 0 0 1 1 0
0 1 0 0 0 0 0 1
1 1 1 1 1 0 0 1
0 1 0 1 0 0 0 1

Po B1’Bo’ B1’Bo B1Bo B1Bo’ A1’Ao’ 0 0 0 0 A1’Ao 0 1 1 0 A1Ao 0 1 1 0 A1Ao’ 0 0 0 0

P1 B1’Bo’ B1’Bo B1Bo B1Bo’ A1’Ao’ 0 0 0 0 A1’Ao 0 0 1 1 A1Ao 0 1 0 1 A1Ao’ 0

11 0
P2 B1’Bo’ B1’Bo B1Bo B1Bo’ A1’Ao’ 0 0 0 0 A1’Ao 0 0 0 0 A1Ao 0 0 0 1 A1Ao’ 0 0

11
P3 B1’Bo’ B1’Bo B1Bo B1Bo’ A1’Ao’ 0 0 0 0 A1’Ao 0 0 0 0 A1Ao 0 0 1 0 A1Ao’ 0 0 0 0

The outputs are given by,

Po = Ao Bo

map.

P1 = AoB1 (A1’+Bo’) + A1Bo (Ao’+B1’)

P2 = A1 B1 Bo’

P3 = A1Ao B1Bo

• Using Half Adder

A1 A0 is multiplicand. B1 B0 is the multiplier. The first product obtained from multiplying Bo

with the multiplicand is called partial product 1 and the second product obtained from
multiplying B1 with the multiplicand is known as the partial product 2.

Page | 23
As the number of bits increases, we keep shifting each successive partial product to the left
by 1 bit in the end, we add the digits while keeping in mind the carry that might generate.
 • 3-bit

multiplier using HA and FA block

A 3-bit multiplier can be implemented using a 3-bit full adder and individual
single-bit adders. The 3-bit multiplier can multiply two numbers with a
maximum bit size of 3 bits. The size of the product will be 6. The maximum
range of its product is 7*7 = 49.
So, this 3-bit multiplier requires 9 AND gates and two 3-bit full adder. When the
three partial product terms
are added together, the LSB
of the sum of each 3- bit full is
directly taken as the output
and the remaining 3-bits are
added to the next partial
product,

A2 A1 A0 (multiplicand)
X B2 B1 B0 (multiplier)
——————————————
A2B0 A1B0 A0B0
A2B1 A1B1 A0B1 X
A2B2 A1B2 A0B2 X X
———————————————
A2B2+C+C A2B2+A1B2+A2B2+C+C
A1B1+C+A0B2+A2B0 A0B1+A1B0 A0B

Page | 24
• BCD adder with correction circuit.
 A BCD adder is a circuit that adds two BCD
digits in
parallel and makes a sum digit also in BCD. A
BCD
adder should contain the correction logic in its
internal construction. To implement a BCD
adder
circuit, we need a 4-bit binary adder for initial
addition and logic circuit to detect sum greater
than
9.

One more 4-bit adder to add 01102 in the sum

if
sum is greater than 9 or carry is 1. The output of the
addition is a BCD-format 4-bit output word, which
defines the decimal sum of the addend and augend
and a carry that is created in case this sum exceeds a
decimal value of 9. The circuit checks the result at the output of the first adder circuit to
determine if the result has exceeded 9 or a Carry has been generated. If the circuit
determines any of the two error conditions the circuit adds a 6 to the.

• CLA adder

A carry-look ahead adder (CLA) is a type of adder used in digital logic. It is also known as a
fast adder. A CLA is made of a number of full-adder that are connected together. It uses
simple logic gates to add two binary numbers. A CLA improves speed by reducing the time
needed to determine carry bits. It also reduces propagation delay by using more complex
hardware circuitry.

Pa
ge | 25
HARDWARE PART:
IC7483 BINARY FULL ADDER.
The IC 7483 is a high-speed 4-bit binary full adder with internal carry lookahead. It has four independent
stages of full adder circuts in a single package. The IC is commonly used in application that involves
arithmatic operations.

The IC 7483 accepts two 4-bit binary words and a carry input. It generates the binary sum outputs and the
carry output from the most significant bit.

The inputs to the IC are A, B, C 0 while outputs are S and C 4. The IC adds the two four bit words along with
input carry to produce a 4 bit sum and a one bit carry-out.

Page | 26

20th October-2023
Lab session 7:
3-bit comparator using basic gates

4X1 MUX with enable using basic gates

4X1 MUX using 2X1 MUX

8X1 MUX using 4X1 MUX

1X4 De-MUX using enable

Full adder implementation using De-MUX

Lab Work: 3-bit comparator using basic gates

A 3-bit comparator compares two 3-bit binary numbers and produces three outputs. The
outputs are based on the relative magnitudes of the binary bits. The outputs are A>B, A=B,
and A<B.
COMPARING PARTS OUTPUT

A3, B3 A2, B2 A1, B1 A0, B0 A>B A<B A=B

A3>B3 X X X 1 0 0

A3<B3 X X X 0 1 0
 A3=B3 A2>B2 X X 1 0 0

A3=B3 A2<B2 X X 0 1 0

A3=B3 A2=B2 A1>B1 X 1 0 0

A3=B3 A2=B2 A1<B1 X 0 1 0

A3=B3 A2=B2 A1=B1 A0>B0 1 0 0

A3=B3 A2=B2 A1=B1 A0<B0 0 1 0

A3=B3 A2=B2 A1=B1 A0=B0 0 0 1

Pa

ge | 27

• 4X1 MUX USING WITH ENABLE

Multiplexer is a combination circuit. It has a 2n 2inputs lien and a single output line. In other
word the multiplexer are multiple inputs and one output. The binary information is place on
the input line and directed to output line. The output line selection is depending on the
select line.
Unlike encoder and decoder, there are “n” inputs lines and “m” input lines. The
multiplexer is also treated as a MUX.

S1 S0 OUTPUT

0 0 A0

0 1 A1
• 8X1
1 0 A2

1 1 A3 MUX USING 4X1 MUX

4x1
• 4x1 MUX USING 2X1 MUX multiplexer
mu

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• 1x4 De-MUX WITH ENABLE USING

BASIC
GATES
A 1x4 demultiplexer (DEMUX) has the following
characteristics:
Inputs: One input (I)
Selection lines: Two selection lines (S1 and S0)
Outputs: Four outputs (O0, O1, O2, and O3)
A DEMUX is the reverse process of a
multiplexer.
The MP1812A is a high performance 1x4
demultiplexer
that supports Super FEC rates up to 48 Gb/s

• FULL ADDER IMPLEMENTATION USING DEMUX

Full Adder is a combinatorial circuit that computes the sum and carries out two input bits
 and an input carry. So it has three inputs – the two bits A and B, and the input carry Cin, and
two outputs – sum S and output carry Cout.

Demultiplexer is a combinational circuit which has 1 input, n selection lines and generates 2n
outputs. It is the reverse operation of multiplexer.

In this article, the Full Adder circuit is implemented by using the concept of the
demultiplexer. By using the expression of the truth table of the Full Adder we connect a
Demultiplexer with two OR gates and it performs an addition operation on three bits and
produces output as sum and carry.
1 1 1 1 1
A B Cin Cout SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0 Pag
e | 29
HARDWARE:
IC7485 (4-BIT COMPARATOR)
The 7485 IC is a 4-bit magnitude comparator. It can compare two 4-bit binary data inputs
and output the result in a 3-bit parallel form. The 7485 IC has the following specifications:
Voltage range: 4.75–5.25
Input voltage: 2–0.8
Output current: -0.4mA–8mA
Operating temperature: 0–70°C
Number of channels: 4
Number of bits: 4
Number of pins: 16
The 7485 IC has low power consumption and is compatible with other TTL devices and
microcontrollers
 IC74

151 (MUX)
The 74151 IC is an 8-input, 1-output multiplexer. It can select one of eight inputs and pass it
to the output. It has a number of control inputs, including:
Select input
Three address inputs
Three select lines A, B and C
One active low enable input

The 74151 IC has two outputs, active low and active high. The selection lines S2, S1 and S0
select the particular input to be multiplexed and applied to the output. Strobe S acts as an

enable signal.

Page | 30
nd
2 October-2023

Lab session 8:
7-bit humming code error detection and correction circuit

8-bit tristate bus

74280 parity circuit using basic gates

Lab work: 7-bit humming code error detection and correction circuit
 The 7-bit Hamming code, also known as
Hamming(7,4), is a linear error-
correcting
code that can detect and correct single-
bit
errors. It was introduced by Richard W.
Hamming in 1950.

The code works by adding three parity

bits to
a 4-bit data word. The parity bits are
chosen
to ensure that each 4-bit group has an
even
number of 1's. This allows the code to
detect
and correct single-bit errors.
The 7-bit Hamming code is made up of:
Data bits: 4-bits (D3, D5, D6 & D7)
Parity bits: 3-bits (P1, P2, & P4)
Parity bit-1 covers bits positioned at 1, 3, 5, 7,
9, 11, and so on. Parity bit-2 covers bits positioned at 2, 3, 6, 7, 10, 11, and so on.

• 8-Bit tristate bus

A tristate buffer is a digital buffer with three stable states:

High output state
Low output state
High-impedance state
The tristate buffer is a current valve that can shut off the output from specific components.
It allows multiple logic devices to be connected to the same wire or bus without damage or
loss of data

The tristate buffer has the following input and output states:
Input A
Output Y
Enable E
High (1):
Low (0):
Floating (Z):
When the enable is TRUE, the tristate buffer acts as a simple buffer, transferring the input

Page | 31
value to the output. When the output enable signal is false, the buffer turns off. The tristate buffer is used in
many electronic and microprocessor circuits.
 • 74280 parity checker circuit

using basic gates

A parity checker circuit can be designed using XOR gates. XOR gates produce a "0" if the bits are the same, or
a "1" if the bits are different. This can also be interpreted as checking if two bits contain an even or odd
amount of "1"s.

Parity circuits are based on the principle that the sum of an odd number of 1s is always 1, and the sum of an
even number of 1s is always 0.

To generate even parity, the bits of data are Exclusive-ORed together in groups of two until there is only a
single output left. This output is the parity bit. To generate odd parity, simply invert the even parity.

Even Parity checkers can be made using EXOR gates, while Odd Parity checkers can be made using EXNOR
gates.

Page | 32
HARDWARE PART

• IC74280 parity checker circuit

The 74280 is a TTL IC parity generator/checker circuit. It's a 9-bit odd/even parity generator/checker with 14
pins and a supply voltage range of 4.5V to 5.5V. The 74280 IC has the following characteristics:
Number of channels: 9
Logic case style: DIP
Number of pins: 14
Supply voltage range: 4.5V to 5.5V
Parity is a technique that checks if data has been lost or written over when it's moved from one storage
location to another or when it's transmitted between computers. The parity check method adds a bit to the
original data to check for errors at the receiver end. If the received data is damaged, the receiver will request
the sender to retransmit the data.
 Page | 33

16th October-2023

Lab session 9:
Construct up and down synchronous counter

Construct mod 5 counter

Construct mod 10 counter

Construct 3-bit pre-settable counter.

Lab Work: up and down synchronous counter

A synchronous up/down counter is a 4-bit counter that increments or decrements its value
based on the logic value of the Up/Down input. The counter's value changes on the falling
edge of the clock signal. The counter also has an enable input that can disable or enable
counting.

Synchronous counters have flip-flops that share a common clock line. The output transition
of each flip-flop occurs at the same time. To get the desired count waveform, some logic
circuitry is needed between the flip-flop inputs and outputs.

• Construct mod 5 counter

A mod-5 counter is a truncated modulus counter that produces a 3-bit binary count
sequence from 0 to 4. The binary count sequence is: 000, 001, 010, 011, 100. A mod-5

counter has five states. It's not a decade counter because it has five states, from decimal
0 to 4.

Page | 34
• Construct mod 10 counter

A mod-10 counter, also known as a decade counter, is a counter that counts from 0 to 9
and then resets to 0. It counts in natural binary sequence. The terminal count for a mod-10
counter is 9.
A mod-10 counter requires four flip-flops. The number of flip-flops required for a mod-N
counter is less than or equal to 2 raised to the power of n, where n is a positive integer.
Here are some things to consider when buying a mod-10 counter:
10 flip flops
4 flip flops
2 flip flops
Synchronous clocking
Decades counters are useful for interfacing to digital displays
 • Construct 3-bit pre-settable counter

A 3-bit pre-settable counter is a digital circuit that uses three flip-flops to count down from a
preset value to zero. It uses synchronous logic and clock signals to ensure precise counting in
a downward sequence

Page |
35
HARDWARE PART

• IC74163 (pre-settable synchronous counter)

The IC 74163 is a high-speed, synchronous, modulo-16, binary counter. It has a single 4-bit counter circuit
and is an UP counter. The IC 74163 has the following features: Count enable inputs: Two types
Terminal count output: Forms a synchronous multistage counter
Preset inputs: Four, which allow it to start counting with any loaded input Physical case/package: PDIP
Mount: Through hole
Number of pins: 16
Weight: 951.693491 mg
Clock edge trigger type: Positive
The IC 74163 has a high speed of f MAX = 63 MHz (TYP.) at VCC = 5 V. It also has a low power dissipation of
ICC = 4 µA (MAX.).
The IC 74163 can be used in cascading multiple 74163 ICs.
 Page | 36

20th October-2023

Lab session 9:
Construct 24-hour clock.

Construct shift register counter (johnson and ring counter)

Self-starting ring counter

Lab Work: construct 24 hour clock.

The IC 74163 is a high-speed, synchronous, modulo-16, binary counter. It has a 4-bit counter
circuit and is an UP counter. The 74163 has the following features:
Synchronous reset input: Overrides counting and parallel loading
Internal carry look-ahead: For high-speed counting designs
Clear terminal: Receives logic 0 and resets the IC on the next clock signal Synchronous
operation: All flip-flops are clocked simultaneously on the positive-going edge of the clock
The 74163 has two types of count enable inputs and a terminal count output. The outputs
(Q0 to Q3) of the counters can be preset to a HIGH or LOW.
Counters are used in digital logic circuits to count the number of clock cycles, pulses, or
other events. They are also used in traffic control systems and medical and industrial
applications.

• Construct shift register counter (johnson and ring counter)

Shift registers are a type of sequential logic that can be used as counters. They are made up
of a series of flip-flops where the output of one flip-flop is connected to the input of the
next. The output of the shift register is taken as output.
 Shift registers are used for a variety of applications, including:
Data storage
Serial-to-parallel and parallel-to-serial data conversion
Shift and rotate operations
Frequency division

Page | 37
Serial data transmission and reception
Some types of shift registers include:
Serial In-Serial Out (SISO)
Serial In-Parallel Out (SIPO)
Parallel In-Serial Out (PISO)
Parallel In-Parallel Out (PIPO)
Shift registers are synchronous devices because all the latches are driven by a common clock
signal. They are also provided with a Clear or Reset connection.

1. Ring
counter
2. Johnson counter
 Page |
38
• Self-starting ring counter

A self-starting counter is a counter that can enter a loop regardless of its initial state. A ring counter is not
self-starting, meaning it requires external intervention to initialize.

A ring counter is similar to a shift counter, but the output of the last flip-flop is connected to the input of the
first flip-flop. A ring counter has more stages than a binary synchronous counter, but it is self-decoding

Page | 39

9th December-2023

ASSIGNMENT: CALCULATOR
We have design calculator using the basic gates for two bits circuits. This circuit can calculate
the operation of addition, multiplication, subtraction, division.

ADDITION:
 Page |

40
SUBTRACTION:
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41
MULTIPLICATION:
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42
DIVISION:
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