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PRACTICAL 1
AIM: Getting familiar with various digital integrated circuits of different
logic families. Study of data sheet of these circuits and see how to test these
circuits using Digital IC Tester.
THEORY:
INTRODUCTION :-
Logic gate is the most basic type of digital circuit, which consists of two or more inputs and
one output. A gate can be used alone to perform a logic function. It can also be connected to
several other gates to form a logic network.

BASIC LOGIC GATE :-

The basic gates are NOT, AND, OR, XOR, XNOR, NAND & NOR. The symbols for these
gates and their corresponding Boolean expressions are briefly discussed in this chapter.

1) AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B or can be written as AB.
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2) OR gate
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.

3) NOT gate
The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known
as NOT A. This is also shown as A' or A with a bar over the top, as shown at the outputs.
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4) NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs
of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a
small circle on the output. The small circle represents inversion.
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5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of
all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.

6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its
two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.
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7) Ex-NOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low
output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a
small circle on the output. The small circle represents inversion.
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PRACTICAL-2
AIM: Configure diodes and transistor as logic gates and Digital ICs for
verification of truth table of logic gates.
THEORY:
1. IC-7408

 The 7408 is a high-speed CMOS Logic Quad AND Gate. 7408 contains Four
independent AND gates in one package.
 An AND gate is a digital logic gate with two or more inputs and one output that
performs logical conjunction.
 The output of an AND gate is true only when all of the inputs are true.
 If one or more of an AND gate’s inputs are false, then the output of the AND gate
is false.
2. IC-7432

 7432 IC is a member of 74xxx series gate ICs and has the functionality of OR gate or
function.
 It will give high if either all or any of the input is high. 7432 has 4 OR gates of 2
inputs in 1 package.
 The internal gates in the ICs are made of Schottky Transistor of low power.
 OR gate finds a Maximum of 2 binary digits.
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3. IC-7404

 The 7404 is a high-speed CMOS Logic Quad NOT Gate.

 7404 contains Six independent NOT gates in one package.
 The NOT gate consists of only one input and one output.
 A NOT gate is used to output the Boolean inverse of the applied input. Hence the
name ‘Digital Inverter’ or ‘Inverting buffer’.
  The most commonly used NOT gate IC is 7404.



 4. IC-7400












 The 7400 IC using NAND gate is most generally used transistor-transistor-logic
(TTL) device. The IC 7400 is a 14-pin chip and it includes four 2-input NAND gates.
 It can be built with 4-independent 2-input NAND gates.
 Every gate utilizes 2-input pins & 1-output pin, by the remaining 2-pins being power
& ground.
 The main feature of this is that any type of logic gate can be designed with the help of
only NAND gates.
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5. IC-7402

 74LS IC series comes up with multiple gates.

 It provides us with compact design and multiple packages of the same IC.
 Here we will discuss 74LS02. 74LS02 also know as 7402.
 IT comes up with 4 internal NOR gate. IC 7402 comes up in multiple packages with 14
pins and 2 inputs 4-NOR gates.
 NOR gate is designed with advanced technology based on silicon.
 IC 74LS02 internal structure based on CMOS technology.

6. IC-7486

 7486 is a 14 pin IC which is use to perform EXCLUSIVE-OR gate logic function in circuit.
 7486 having 1 VCC and 1 GND pin, and 8 input pins and 4 output pins.

7. IC-74266
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 Basically the “Exclusive-NOR Gate” is a combination of the Exclusive-OR gate and

the NOT gate but has a truth table similar to the standard NOR gate in that it has an
output that is normally HIGH (1) and goes LOW (0) when any of its inputs are HIGH
(1).
8. IC-7410

 7410 is a 14pin IC which is use to perform NAND gate logic function in circuit.
 It have 9 input pins and 3 output pins.

9. IC-7420

 7420 Dual 4-Input NAND Gates. The 7420 IC is composed of two independent Four-
Input NAND gates.
 The truth table for the 4-input of the NAND is identical to that of the 2-Input variant.
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PRACTICAL 3
AIM: Configuring NAND and NOR logic gates as universal gates.

1) Nand gate as Universal gate

NAND gate is actually a combination of two logic gates i.e. AND gate followed by NOT
gate. So its output is complement of the output of an AND gate.This gate can have minimum
two inputs. By using only NAND gates, we can realize all logic functions: AND, OR, NOT,
Ex-OR, Ex-NOR, NOR. So this gate is also called as universal gate.

1.1) NAND gates as OR gate

From DeMorgan’s theorems:

(A.B)’=A’+B’
(A’.B’)’=A’’+B’’=A+B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.
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1.2) NAND gates as AND gate

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted,
overall output will be that of an AND gate.

Y = ((A.B)’)’
Y = (A.B)
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1.3) NAND gates as Ex-OR gate

The output of a two input Ex-OR gate is shown by: Y = A’B + AB’. This can be achieved with
the logic diagram shown in the left side.
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1.4) NAND gates as Ex-NOR gate

Ex-NOR gate is actually Ex-OR gate followed by NOT gate. So give the output of Ex-OR gate
to a NOT gate, overall output is that of an Ex-NOR gate.

Y = AB+ A’B’
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1.5) Implementing the simplified function with NAND gates only

We can now start constructing the circuit. First note that the entire expression is inverted and
we have three terms ANDed. This means that we must use a 3-input NAND gate. Each of the
three terms is, itself, a NAND expression. Finally, negated single terms can be generates with
a 2-input NAND gate acting as an inverted. The expression illustrates a circuit using NAND
gates only.

F=((C'.B.A)'(D'.C.A)'(C.B'.A)')'

The stepwise simplication of this expression is done on the basis of this logic diagram in
Figure 9:
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2) Nor gate as Universal Gate

NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. So its
output is complement of the output of an OR gate.This gate can have minimum two inputs,
output is always one. By using only NOR gates, we can realize all logic functions: AND, OR,
NOT, Ex-OR, Ex-NOR, NAND. So this gate is also called universal gate.

2.1) NOR gates as OR gate

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall
output will be that of an OR gate.

Y = ((A+B)’)’
Y = (A+B)
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2.2) NOR gates as AND gate

From DeMorgan’s theorems:

(A+B)’=A’B’
(A’+B’)’=A’’B’’=AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.
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2.3) NOR gates as Ex-OR gate

Ex-OR gate is actually Ex-NOR gate followed by NOT gate. So give the output of Ex-NOR
gate to a NOT gate, overall output is that of an Ex-ORgate.

Y = A’B+ AB’
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2.4) NOR gates as Ex-NOR gate

The output of a two input Ex-NOR gate is shown by: Y = AB + A’B’. This can be achieved
with the logic diagram shown in the left side.
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2.5) Constructing a circuit with NOR gates only

Designing a circuit with NOR gates only uses the same basic techniques as designing a circuit
with NAND gates; that is, the application of deMorgan’s theorem. The only difference between
NOR gate design and NAND gate design is that the former must eliminate product terms and
the later must eliminate sum terms.

F=(((C.B'.A)+(D.C'.A)+(C.B'.A))')'
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PRACTICAL-4
AIM: Implementation of Boolean Logic Functions using logic gates and
combinational circuits. Measure digital logic gate specifications such as
propagation delay, noise margin, fan in and fan out.
THEORY:-
1. AB + A’C + BC = AB + A’C
According to consensus theorem, the Boolean identity holds

In above picture both circuits are equivalent.

2. AB + A’C = (A + C)(A’ + B)
According to consensus theorem, the Boolean identity holds.

In above picture both circuits are equivalent.

3. Verify equivalence of AND-OR and NAND-NAND structure

In above picture both circuits are equivalent.

4. Verify equivalence of OR-AND and NOR-NOR structure

In above picture both circuits are equivalent.

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SIMULATOR:
1. Part – I:-

2. Part – II:-
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3. Part -III:-
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4. Part – IV:-

 Propagation Delay :Propagation delay is defined as the flight time of packets over
the transmission link and is limited by the speed of light.

 Noise Margin :Ability of the gate to tolerate fluctuations of the voltage levels.The
input and output voltage levels defined above point. Stray electric and magnetic fields
may induce unwanted voltages, known as noise, on the connecting wires between logic
circuits.

 Fan in :Fan-in refers to the maximum number of input signals that feed the
input equations of a logic cell.

 Fan out :Fan-out refers to the maximum number of output signals that are fed by
the output equations of a logic cell.
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PRACTICAL 5
AIM: Study and configure of various digital circuits such as adder,
subtractor, decoder, encoder, code converters.

Introduction(ADDER)
Adders are digital circuits that carry out addition of numbers. Adders are a key component of
arithmetic logic unit. Adders can be constructed for most of the numerical representations like
Binary Coded Decimal (BCD), Excess – 3, Gray code, Binary etc. out of these, binary addition
is the most frequently performed task by most common adders. Apart from addition, adders are
also used in certain digital applications like table index calculation, address decoding etc.

Binary addition is similar to that of decimal addition. Some basic binary additions are shown
below.

1) HALF-ADDER

Half adder is a combinational circuit that performs simple addition of two binary numbers. If
we assume A and B as the two bits whose addition is to be performed,the block diagram and a
truth table for half adder with A, B as inputs and Sum, Carry as outputs can be tabulated as
follows.

The sum output of the binary addition carried out above is similar to that of an Ex-OR
operation while the carry output is similar to that of an AND operation. The same can be
verified with help of Karnaugh Map.
The truth table and K Map simplification and logic diagram for sum output is shown below
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The truth table and K Map simplification and logic diagram for carry is shown below.

If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex
– OR of A and B and logic function to calculate carry C is AND of A and B. Combining
these two, the logical circuit to implement the combinational circuit of half adder is shown
below.

As we know that NAND and NOR are called universal gates as any logic system can be
implemented using these two, the half adder circuit can also be implemented using them. We
know that a half adder circuit has one Ex – OR gate and one AND gate.
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1.1) Half Adder using NAND gates

Five NAND gates are required in order to design a half adder. The circuit to realize half adder
using NAND gates is shown below.

1.2) Half Adder using NOR gates

Five NOR gates are required in order to design a half adder. The circuit to realize half adder
using NOR gates is shown below.
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2) Full Adder

Full adder is a digital circuit used to calculate the sum of three binary bits. Full adders are
complex and difficult to implement when compared to half adders. Two of the three bits are
same as before which are A, the augend bit and B, the addend bit. The additional third bit is
carry bit from the previous stage and is called 'Carry' – in generally represented by CIN. It
calculates the sum of three bits along with the carry. The output carry is called Carry – out
and is represented by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S, Carry OUT as outputs
is shown below.

Figure 8. Full Adder Block Diagram and Truth Table

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Figure 9. Full Adder Logic Diagram

Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be
derived using K – Map.

Figure 10. The K-Map simplified equation for sum is S = A'B'Cin + A'BCin' + ABCin

Figure 11. The K-Map simplified equation for COUT is COUT = AB + ACIN + BCIN

In order to implement a combinational circuit for full adder, it is clear from the equations
derived above, that we need four 3-input AND gates and one 4-input OR gates for Sum and
three 2-input AND gates and one 3-input OR gate for Carry – out.

2.1) Full Adder using NAND gates

As mentioned earlier, a NAND gate is one of the universal gates and can be used to
implement any logic design. The circuit of full adder using only NAND gates is shown
below.
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Figure 12. Full Adder using NAND gates

2.2) Full Adder using NOR gates

As mentioned earlier, a NOR gate is one of the universal gates and can be used to implement
any logic design. The circuit of full adder using only NOR gates is shown below.

Figure 13. Full Adder using NOR gates

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INTRODUCTION(SUBTRACTOR)
Subtractor circuits take two binary numbers as input and subtract one binary number input from
the other binary number input. Similar to adders, it gives out two outputs, difference and borrow
(carry-in the case of Adder). There are two types of subtractors.

1. Half Subtractor
2. Full Subtractor

1) Half Subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits.
It has two inputs, A (minuend) and B (subtrahend) and two outputs Difference and Borrow.
The logic symbol and truth table are shown below.

Figure-1:Logic Symbol of Half subtractor

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Figure-2:Truth Table of Half subtractor

Figure-3:Circuit Diagram of Half subtractor

From the above truth table we can find the boolean expression.

Difference = A ⊕ B
Borrow = A' B

From the equation we can draw the half-subtractor circuit as shown in the figure 3.
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2) Full Subtractor
A full subtractor is a combinational circuit that performs subtraction involving three bits,
namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A
(minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference)
and Bout (borrow out). The logic symbol and truth table are shown below.

Figure-4:Logic Symbol of Full subtractor

Figure-5:Truth Table of Full subtractor

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From the above truth table we can find the boolean expression.

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin
From the equation we can draw the Full-subtractor circuit as shown in the figure 6.

Figure-6:Circuit Diagram of Full subtractor

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BINARY TO GRAY CONVERSION

Introduction
Binary Numbers is default way to store numbers, but in many applications binary numbers
are difficult to use and a variation of binary numbers is needed. Gray code is an ordering of
the binary numeral system such that two successive values differ in only one bit (binary
digit). Gray codes are very useful in the normal sequence of binary numbers generated by the
hardware that may cause an error or ambiguity during the transition from one number to the
next. So, the Gray code can eliminate this problem easily since only one bit changes its value
during any transitions between two numbers.

Gray code has property that two successive numbers differ in only one bit because of this
property gray code does the cycling through various states with minimal effort and used in K-
maps, error correction, communications etc.
In computer science many a times we need to convert binary code to gray code and vice
versa. This conversion can be done by applying following rules :

1) Binary to Gray conversion :

1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given
binary code.
2. Other bits of the output gray code can be obtained by Ex-ORing binary code bit at that index
and previous index.
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3. There are four inputs and four outputs. The input variable are defined as B3, B2, B1, B0 and
the output variables are defined as G3, G2, G1, G0. From the truth table, combinational circuit
is designed.The logical expressions are defined as :

B3 = G3

B2 ⊕ B3 =
G2 B 1 ⊕ B2
= G1 B0 ⊕B1
=G0

Figure-1: Binary to Gray Code Converter Circuit

Figure-2: Binary to Gray Code Converter Truth Table

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2) Gray to binary conversion :

1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given
binary number.
2. Other bits of the output binary code can be obtained by checking gray code bit at that index.
If current gray code bit is 0, then copy previous binary code bit, else copy invert of previous
binary code bit.

There are four inputs and four outputs. The input variable are defined as G3, G2, G1, G0 and
the output variables are defined as B3, B2, B1, B0. From the truth table, combinational circuit
is designed.The logical expressions are defined as :

G 0 ⊕ G 1 ⊕ G 2 ⊕ G 3 = B0
G 1 ⊕ G 2 ⊕ G 3 = B1
G2 ⊕ G3 =
B2 G3 = B3

Figure-3: Gray to Binary Code Converter Circuit

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Figure-4: Gray to Binary Code Converter Truth Table

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Implementation and verification of decoder/de-multiplexer and encoder using

logic gates.

Introduction
Binary code of N digits can be used to store 2N distinct elements of coded information. This
is what encoders and decoders are used for. Encoders convert 2N lines of input into a code of
N bits and Decoders decode the N bits into 2N lines.

1) 2x4 Decoder / De-multiplexer

The name “Decoder” means to translate or decode coded information from one format into
another, so a digital decoder transforms a set of digital input signals into an equivalent decimal
code at its output

A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of m=2^n unique output lines.

Figure 1. Logic Diagram of Decoder

1.1) 2-to-4 Binary Decoder

Figure 2. Circuit Diagram of 2-to-4 Decoder

The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The 2
binary inputs labelled A and B are decoded into one of 4 outputs, hence the description of 2-
to-4 binary decoder. Each output represents one of the minterms of the 2 input variables,
(each output = a minterm).
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Figure 3. Logic Diagram and Truth table of 2-to-4 Decoder

The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output can be
active (HIGH) at any one time.

Therefore, whichever output line is “HIGH” identifies the binary code present at the input, in
other words it “decodes” the binary input.Some binary decoders have an additional input pin
labelled “Enable” that controls the outputs from the device.

This extra input allows the decoders outputs to be turned “ON” or “OFF” as required. Output
is only generated when the Enable input has value 1; otherwise, all outputs are 0. Only a
small change in the implementation is required: the Enable input is fed into the AND gates
which produce the outputs.

If Enable is 0, all AND gates are supplied with one of the inputs as 0 and hence no output is
produced. When Enable is 1, the AND gates get one of the inputs as 1, and now the output
depends upon the remaining inputs. Hence the output of the decoder is dependent on whether
the Enable is high or low.
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2) Encoder

An Encoder is a combinational circuit that performs the reverse operation of Decoder.It has
maximum of 2n input lines and ‘n’ output lines, hence it encodes the information from 2n inputs
into an n-bit code. It will produce a binary code equivalent to the input, which is active High.
Therefore, the encoder encodes 2n input lines with ‘n’ bits.

Figure 4. Logic Diagram of ENCODER

2.1 )4 : 2 Encoder
The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. At any
time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output.
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PRACTICAL 6
AIM: Study and configurations of multiplexer and demultiplexer
circuits.
Introduction
The function of a multiplexer is to select the input of any ‘n’ input lines and feed that to one
output line. The function of a de-multiplexer is to inverse the function of the multiplexer and
the shortcut forms of the multiplexer. The de-multiplexers are mux and demux. Some
multiplexers perform both multiplexing and de-multiplexing operations.

Figure-1:Block diagram of Multiplexer and De-multiplexer

1) Multiplexer Multiplexer:
Multiplexer Multiplexer is a device that has multiple inputs and a single line output. The
select lines determine which input is connected to the output, and also to increase the amount
of data that can be sent over a network within certain time. It is also called a data selector.

Multiplexers are classified into four types:

a) 2-1 multiplexer (1 select line)

b) 4-1 multiplexer (2 select lines)
c) 8-1 multiplexer(3 select lines)
d) 16-1 multiplexer (4 select lines)

a) 4x1 Multiplexer
4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.One of
these 4 inputs will be connected to the output based on the combination of inputs present at
these two selection lines. Truth table of 4x1 Multiplexer is shown below.
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Figure-2:Block diagram of 4x1 Multiplexer

Figure-3:Truth table of 4x1 Multiplexer

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2) De-multiplexer :
De-multiplexer is also a device with one input and multiple output lines. It is used to send a
signal to one of the many devices. The main difference between a multiplexer and a de-
multiplexer is that a multiplexer takes two or more signals and encodes them on a wire,
whereas a de-multiplexer does reverse to what the multiplexer does.

De-multiplexer are classified into four types:

a) 1-2 demultiplexer (1 select line)

b) 1-4 demultiplexer (2 select lines)
c) 1-8 demultiplexer (3 select lines)
d) 1-16 demultiplexer (4 select lines)

b) 1x4 De-multiplexer
1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and four outputs Y0,
Y1, Y2 & Y3. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

Figure-4:Block diagram of 1x4 De-Multiplexer

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Figure-5:Truth table of 1x4 De-Multiplexer

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PRACTICAL-7
AIM: Study and configure of flipflop , registers and counters using
digitalICs . Design digital system using these circuits

Introduction

A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems.

1. R-S flip flop

2. D flip flop
3. J-K flip flop
4. T flip flop

1) RS flip flop

The basic NAND gate RS flip flop circuit is used to store the data and thus provides feedback
from both of its outputs again back to its inputs. The RS flip flop actually has three inputs,
SET, RESET and clock pulse.

Figure-1:R-S flip flop circuit diagram

Figure-2:Characteristics table of R-S flip flop

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2) D flip flop
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop
by connecting the R input through an inverter, and the S input is connected directly to data
input. The modified clocked SR flip-flop is known as D-flip-flop and is shown below. From
the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable
state when the inputs are same and high. In many practical applications, these input
conditions are not required. These input conditions can be avoided by making them
complement of each other.

Figure-3:Circuit diagram of D flip flop

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Figure-4:Characteristics table of D flip flop

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3) J-K flip flop

In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit
may be re-joined if both inputs are 1 than also the outputs are complement of each other as
shown in characteristics table below.

Figure-5:Circuit diagram of J-K flip flop

Figure-6:Characteristics table of J-K flip flop

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4) T flip flop

T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop.
Both the JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to
change as shown in table below.

Figure-7:Circuit diagram of T flip flop

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Figure-8:Characteristics table of T flip flop

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