Hi-performance Regulator IC Series for PCs

Main Power Supply ICs

for Note PC (Linear Regulator Integrated)
No.10030EAT26
BD9528MUV

●Description
BD9528MUV is a 2ch switching regulator controller with high output current which can achieve low output voltage (1.0V～
5.5V) from a wide input voltage range (5.5V～28V). High efficiency for the switching regulator can be realized by utilizing an
external N-MOSFET power transistor. A new technology called H3RegTM(High speed, High efficiency, High performance)
is a Rohm proprietary control method to realize ultra high transient response against load change. SLLM (Simple Light Load
Mode) technology is also integrated to improve efficiency in light load mode, providing high efficiency over a wide load
range. For protection and ease of use, 2ch LDO (5V/100mA, 3.3V/100mA), the soft start function, variable frequency
function, short circuit protection function with timer latch, over voltage protection, and Power good function are all built in.
This switching regulator is specially designed for Main Power Supply of laptop PC.

●Features
1) 2ch H3REGTM DC/DC Converter controller
2) Adjustable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and Forced continuous Mode
3) Thermal Shut Down (TSD), Under Voltage LockOut (UVLO), Over Current Protection (OCP),
Over Voltage Protection (OVP), Short circuit protection with 0.75ms timer-latch (SCP)
4) Soft start function to minimize rush current during startup
5) Switching Frequency Variable (f=200kHz～500kHz)
6) Built-in Power good circuit
7) Built-in 2ch Linear regulator (5V/100mA,3.3V/100mA)
8) Built in reference voltage(0.7V)
9) VQFN032V5050 package
10) Built-in BOOT-Di
11) Built-in output discharge

●Applications
Laptop PC, Desktop PC, LCD-TV, Digital Components

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BD9528MUV Technical Note

●Absolute maximum ratings (Ta=25℃)

Parameter Symbol Limits Unit
VIN, CTL,SW1,SW2 30 *1*2 V
EN1, EN2, PGOOD1, PGOOD2
6 *1*2 V
Vo1, Vo2, MCTL1, MCTL2
FS1, FS2, FB1, FB2, ILIM1, ILIM2,
REG1+0.3 *1 V
SS1, SS2, LG1, LG2, REF,REG2
Terminal Voltage BOOT1, BOOT2 35 *1*2 V
BOOT1-SW1, BOOT2-SW2,
7 *1*2 V
HG1-SW1, HG2-SW2
HG1 BOOT1+0.3 *1*2 V
HG2 BOOT2+0.3 *1*2 V
PGND1, PGND2 AGND±0.3 *1*2 V
Power Dissipation1 Pd1 0.38 *3 W
Power Dissipation2 Pd2 0.88 *4 W
Power Dissipation3 Pd3 3.26 *5 W
6
Power Dissipation4 Pd4 4.56 * W
Operating temperature Range Topr -20～+100 ℃
Storage temperature Range Tstg -55～+150 ℃
Junction Temperature Tjmax +150 ℃

*1 Do not however exceed Pd.

*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.
*3 Reduced by 3.0mW for each increase in Ta of 1℃ over 25℃ (when don’t mounted on a heat radiation board )
*4 Reduced by 7.0mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 1 layer.
(Copper foil area : 20.2mm2)
*5 Reduced by 26.1mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 4 layers.
(1st and 4th copper foil area : 20.2mm2, 2nd and 3rd copper foil area : 5505mm2)
*6 Reduced by 36.5mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 4 layers.
(All copper foil area : 5505mm2)

●Operating conditions(Ta=25℃)

Parameter Symbol MIN. MAX. Unit

VIN 5.5 28 V
CTL -0.3 28 V
EN1, EN2, MCTL1, MCTL2 -0.3 5.5 V
Terminal Voltage BOOT1, BOOT2 4.5 33 V
SW1, SW2 -0.3 28 V
BOOT1-SW1, BOOT2-SW2, HG1-SW1, HG2-SW2 -0.3 5.5 V
Vo1, Vo2, PGOOD1, PGOOD2 -0.3 5.5 V
MIN ON TIME TONmin - 150 nsec

★ This product should not be used in a radioactive environment.

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BD9528MUV Technical Note

●Electrical characteristics
(unless otherwise noted, Ta=25℃ VIN=12V, CTL=OPEN, EN1=EN2=5V, FS1=FS2=51kΩ)
Standard Value
Parameter Symbol Unit Condition
MIN. TYP. MAX.
VIN standby current ISTB 70 150 250 μA CTL=5V, EN1=EN2=0V
VIN bias current IIN 60 130 230 μA Vo1=5V
VIN shut down mode current ISHD 6 12 18 μA CTL=0V
CTL Low Voltage VCTLL -0.3 - 0.8 V
CTL High Voltage VCTLH 2.3 - 28 V
CTL bias current ICTL -18 -12 -6 μA CTL=0V
EN Low Voltage VENL -0.3 - 0.8 V
EN High Voltage VENH 2.3 - 5.5 V
EN bias current IEN - 3 6 μA EN=3V
[5V linear regulator](VIN)
REG1 output voltage VREG1 4.90 5.00 5.10 V IREG1=1mA
Maximum current IREG1 100 - - mA IREG2=0mA
Line Regulation Reg.l1 - 90 180 mV VIN=5.5 to 25V
Load Regulation Reg.L1 - 30 50 mV IREG1=0 to 30mA
[3.3V linear regulator]
REG2 output voltage VREG2 3.27 3.30 3.33 V IREG2=1mA
Maximum current IREG2 100 - - mA IREG1=0mA
Line Regulation Reg.l2 - - 20 mV VIN=5.5 to 25V
Load Regulation Reg.L2 - - 30 mV IREG2=0 to 30mA
[5V linear regulator](Vo1)
Input threshold voltage REG1th 4.1 4.4 4.7 V Vo1: Sweep up
Input delay time TREG1 1.5 3.0 6.0 ms
Switch resistance RREG1 - 1.0 3.0 Ω
[Under Voltage lock out block]
REG1 threshold voltage REG1_UVLO 3.9 4.2 4.5 V REG1: Sweep up
Hysteresis voltage dV_UVLO 50 100 200 mV REG1, Sweep down
[Output voltage sense block]
Feedback voltage1 VFB1 0.693 0.700 0.707 V
FB1 bias current IFB1 - 0 1 μA FB1=REF
Output discharge resistance1 RDISOUT1 50 100 200 Ω
Feedback voltage2 VFB2 0.693 0.700 0.707 V
FB2 bias current IFB2 - 0 1 μA FB2=REF
Output discharge resistance2 RDISOUT2 50 100 200 Ω

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BD9528MUV Technical Note

●Electrical characteristics – Continued

(unless otherwise noted, Ta=25℃ VIN=12V, CTL=OPEN, EN1=EN2=5V, FS1=FS2=51kΩ)
Standard Value
Parameter Symbol Unit Condition
MIN. TYP. MAX.
[H3REG block]
Ontime1 TON1 0.760 0.910 1.060 μs Vo1=5V
Ontime2 TON2 0.470 0.620 0.770 μs Vo2=3.3V
Maximum On time 1 TONMAX1 2.5 5 10 μs Vo1=5V
Maximum On time 2 TONMAX2 1.65 3.3 6.6 μs Vo2=33V
Minimum Off time TOFFMIN - 0.2 0.4 μs
[FET driver block]
HG higher side ON resistor HGHON - 3.0 6.0 Ω
HG lower side ON resistor HGLON - 2.0 4.0 Ω
LG higher side ON resistor LGHON - 2.0 4.0 Ω
LG lower side ON resistor LGLON - 0.5 1.0 Ω
[Over voltage protection block]
0.77 0.84 0.91
OVP threshold voltage VOVP V
(+10%) (+20%) (+30%)
OVP Hysteresis dV_OVP 50 150 300 mV
[Short circuit protection block]
0.42 0.49 0.56
SCP threshold voltage VSCP V
(-40%) (-30%) (-20%)
Delay time TSCP 0.4 0.75 1.5 ms
[Current limit protection block]
Offset voltage dVSMAX 80 100 120 mV ILIM=100kΩ
[Power good block]
0.525 0.595 0.665
Power good low threshold VPGTHL V
(-25%) (-15%) (-5%)
Power good low voltage VPGL - 0.1 0.2 V IPGOOD=1mA
Delay time TPGOOD 0.4 0.75 1.5 ms
Power good leakage current ILEAKPG -2 0 2 μA VPGOOD=5V
[Soft start block]
Charge current ISS 1.5 2.3 3.1 μA
Standby voltage VSS_STB - - 50 mV
[Mode control block]
MCTL Low voltage VMCTL_L -0.3 - 0.3 V
REG1
MCTL High voltage VMCTL_H 2.3 - V
+0.3
MCTL bias current IMCTL 8 16 24 μA MCTL=5V

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BD9528MUV Technical Note

●Output condition table

Input Output
CTL EN1 EN2 REG1(5V) REG2(3.3V) DC/DC1 DC/DC2
Low Low Low OFF OFF OFF OFF
Low Low High OFF OFF OFF OFF
Low High Low OFF OFF OFF OFF
Low High High OFF OFF OFF OFF
High Low Low ON ON OFF OFF
High Low High ON ON OFF ON
High High Low ON ON ON OFF
High High High ON ON ON ON
※ CTL pin is connected to VIN pin with 1MΩ resistor(pull up) internal IC.
※ EN pin is connected to AGND pin with 1MΩ resistor(pull down) internal IC.

●Block Diagram, Application circuit

Adjustable
Adjustable

Vo1
Vo2

VIN
VIN
BOOT2

BOOT1

PGND1
PGND2
SW2

SW1
HG2

HG1
LG2

LG1

3 2 1 31 32 22 23 24 26 25

REG1 REG1
REG1
REG1

AGND

CL2 CL1
13
SCP2 Short through Short through SCP1
OVP2 Protection Protection OVP1
Circuit Circuit FS1 RFS1
FS2
15
10
SLLMTM SLLMTM
MCTL MCTL
Short Circuit Protect
SCP2

Block Block
SCP1
REG1

REG1
5 20
Short Circuit Protect

PGOOD2 PGOOD1
OVP2

OVP1

H3RegTM H3RegTM
Timer

Timer

Power Good
Over Voltage

Over Voltage

Timer

Timer

Controller FS2 FS1 Controller

Power Good

Block Block
Protect

Protect
TSD

EN2 EN1
UVLO

FB2 FB1
REF

11 Thermal 14
Protection
REF

REF
6 12
SS1
Over Current

SS2 19
CL2

Over Current
Protect

CL1
Protect

ILIM2 ILIM1
8 17
REF

REG1
SW2
PGND2

SW1
PGND1

Reference
MCTL

SLLM Mode Control

Block

5V 3.3V
Reg Reg
Vo1

EN2
4 EN1
21

7 9 30 29 28 18 16 27
MCTL1

MCTL2
VIN
Vo2

Vo1
CTL

REG1

REG2
1uF

REG2
REG1
VIN

5.5～28V

3.3V
5V

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BD9528MUV Technical Note

●Pin Configuration

PGOOD1
BOOT1

MCTL1

ILIM1
SW1

HG1

EN1

SS1
24 23 22 21 20 19 18 17
Input
PGND1 MCTL2 Control Mode
25 16 MCTL1 MCTL2
LG1 FS1 Low Low SLLM
26 15
Vo1 FB1 Low High QLLM
27 14
High Low Forced Continuous Mode
REG2 AGND
28 13 High High Forced Continuous Mode
FIN
REG1
29 12 REF
※MCTL pin is connected to AGND pin with 500kΩ
VIN FB2
30 11 resistor ( pull down) internal IC
LG2 FS2
31 10
PGND2 CTL
32 9

1 2 3 4 5 6 7 8
HG2

BOOT2

PGOOD2
EN2

SS2

Vo2

ILIM2
SW2

●Pin Function Table

PIN No. PIN name PIN Function

1 SW2 Highside FET source pin 2
2 HG2 Highside FET gate drive pin 2
3 BOOT2 HG Driver power supply pin 2
4 EN2 Vo2 ON/OFF pin (High=ON, Low,OPEN=OFF)
5 PGOOD2 Vo2 Power Good Open Drain Output pin
6 SS2 Vo2 Soft start pin
7 Vo2 Vo2 Output voltage sense pin
8 ILIM2 OCP setting pin 2
Linear regulator ON/OFF pin
9 CTL
(High,OPEN=ON, Low=OFF)
10 FS2 Input pin for setting Vo2 frequency
11 FB2 Vo2 output voltage feedback pin
12 REF Output voltage setting pin
13 AGND Input pin Ground
14 FB1 Vo1 output voltage feedback pin
15 FS1 Input pin for setting Vo1 frequency
16 MCTL2 Mode switch pin 2 ( OPEN = L )
17 ILIM1 OCP setting pin 1
18 MCTL1 Mode switch pin 1 ( OPEN = L )
19 SS1 Vo1 Soft start pin
20 PGOOD1 Vo1 Power Good Open Drain Output pin
Vo1 ON/OFF pin
21 EN1
(High=ON, Low,OPEN=OFF)
22 BOOT1 HG Driver power supply pin
23 HG1 Highside FET gate drive pin 1
24 SW1 Highside FET source pin 1
25 PGND1 Lowside FET source pin 1
26 LG1 Lowside FET gate drive pin 1
27 Vo1 Vo1 Output voltage sense pin
28 REG2 3.3V Linear regulator output pin
29 REG1 5V Linear regulator output pin
30 VIN Power supply input pin
31 LG2 Lowside FET gate drive pin 2
32 PGND2 Lowside FET source pin 2
reverse FIN Exposed Pad1, connect to GND

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BD9528MUV Technical Note

●Electrical characteristic curves (Reference data)

HG
10V/div HG
SW 10V/div HG
10V/div SW 10V/div
10V/div SW
10V/div
LG
5V/div LG
5V/div LG
5V/div
2us 2us 10us
Fig.1 Switching Waveform Fig.2 Switching Waveform Fig.3 Switching Waveform
(Vo=5V, PWM, Io=0A) (Vo=5V, PWM, Io=8A) (Vo=5V, QLLM, Io=0A)

HG
10V/div HG HG
SW 10V/div 10V/div
10V/div SW SW
10V/div 10V/div

LG
5V/div LG LG
10us 2us 5V/div 2us 5V/div

Fig.4 Switching Waveform Fig.5 Switching Waveform Fig.6 Switching Waveform

(Vo=5V, SLLM, Io=0A) (Vo=3.3V, PWM, Io=0A) (Vo=3.3V, PWM, Io=8A)

HG
10V/div HG HG
SW 10V/div 10V/div
10V/div SW SW
10V/div 10V/div

LG
5V/div LG LG
10us 10us 5V/div 2us 5V/div

Fig.7 Switching Waveform Fig.8 Switching Waveform Fig.9 Switching Waveform

(Vo=3.3V, QLLM, Io=0A) (Vo=3.3V, SLLM, Io=0A) (Vo=1V, PWM, Io=0A)

HG HG
10V/div HG
10V/div 10V/div
SW SW
10V/div SW
10V/div 10V/div

LG LG
2us 5V/div 10us 10us LG
5V/div 5V/div

Fig.10 Switching Waveform Fig.11 Switching Waveform Fig.12 Switching Waveform

(Vo=1V, PWM, Io=8A) (Vo=1V, QLLM, Io=0A) (Vo=1V, SLLM, Io=0A)

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BD9528MUV Technical Note

●Electrical characteristic curves (Reference data) – Continued

100 100 100

80 80 80 7V
7V 12V
60 60 12V 60
7V 12V

η[%]
21V
η[%]

η[%]
40 21V 40 21V
40

20 20 20

0 0 0
1 10 100 1000 10000 1 10 100 1000 10000 1 10 100 1000 10000
Io[mA] Io[mA] Io[mA]

Fig.13 Efficiency Fig.14 Efficiency Fig.15 Efficiency

(Vo=5V, PWM) (Vo=5V, QLLM) (Vo=5V, SLLM)

100 100 100

5V
80 80 80
7V 7V
7V 12V
12V
60 60 60
η[%]
η[%]

η[%]
12V
21V 21V
40 40 40
21V

20 20 20

0 0 0
1 10 100 1000 10000 1 10 100 1000 10000 1 10 100 1000 10000
Io[mA] Io[mA] Io[mA]

Fig.16 Efficiency Fig.17 Efficiency Fig.18 Efficiency

(Vo=3.3V, PWM) (Vo=3.3V, QLLM) (Vo=3.3V, SLLM)

100 100 100

7V 7V
80 7V 80 80

60 12V 12V 60 12V

60
η[%]

η[%]
η[%]

21V 21V 21V

40 40 40

20 20 20

0 0 0
1 10 100 1000 10000 1 10 100 1000 10000 1 10 100 1000 10000
Io[mA] Io[mA] Io[mA]

Fig.19 Efficiency Fig.20 Efficiency Fig.21 Efficiency

(Vo=1V, PWM) (Vo=1V, QLLM) (Vo=1V, SLLM)

20us 20us 20us

Vo Vo Vo
100mV/div 100mV/div 100mV/div

IL
IL 5A/div
5A/div IL Io
Io 5A/div 5A/div
5A/div Io
5A/div
Fig.22 Transient Response Fig.23 Transient Response Fig.24 Transient Response
(Vo=5V, PWM, Io=0→8A) (Vo=5V, PWM, Io=8→0A) (Vo=3.3V, PWM, Io=0→8A)

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BD9528MUV Technical Note

●Electrical characteristic curves (Reference data) – Continued

20us 20us 20us

Vo Vo
100mV/div Vo
100mV/div 100mV/div

IL
IL 5A/div
Io IL
5A/div 5A/div
Io 5A/div
Io
5A/div 5A/div
Fig.25 Transient Response Fig.26 Transient Response Fig.27 Transient Response
(Vo=3.3V, PWM, Io=8→0A) (Vo=1V, PWM, Io=0→8A) (Vo=1V, PWM, Io=8→0A)

Vo Vo Vo
50mV/div 50mV/div 50mV/div

2us 2us 10us

Fig.28 Output Voltage Fig.29 Output Voltage Fig.30 Output Voltage

(Vo=5V, PWM, Io=0A) (Vo=5V, PWM, Io=8A) (Vo=5V, QLLM, Io=0A)

Vo Vo
Vo 50mV/div 50mV/div
50mV/div

2us 2us 2us

Fig.31 Output Voltage Fig.32 Output Voltage Fig.33 Output Voltage

(Vo=5V, SLLM, Io=0A) (Vo=3.3V, PWM, Io=0A) (Vo=3.3V, PWM, Io=8A)

Vo Vo
50mV/div Vo
50mV/div 50mV/div

10us 2us 2us

Fig.34 Output Voltage Fig.35 Output Voltage Fig.36 Output Voltage

(Vo=3.3V, QLLM, Io=0A) (Vo=3.3V, SLLM, Io=0A) (Vo=1V, PWM, Io=0A)

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BD9528MUV Technical Note

●Electrical characteristic curves (Reference data) – Continued

Vo Vo
50mV/div Vo
50mV/div 50mV/div

2us 10us 2us

Fig.37 Output Voltage Fig.38 Output Voltage Fig.39 Output Voltage

(Vo=1V, PWM, Io=8A) (Vo=1V, QLLM, Io=0A) (Vo=1V, SLLM, Io=0A)

EN1 EN1 EN1

5V/div 5V/div 5V/div
Vo1 Vo1 Vo1
2V/div 2V/div 2V/div

EN2 EN2 EN2

5V/div 5V/div 5V/div
Vo2 Vo2 Vo2
2V/div 2V/div 2V/div

Fig.40 Wake up waveform Fig.41 Wake up waveform Fig.42Wake up waveform

(EN1=EN2) (EN2→EN1) (EN1→EN2)

IOUT-frequency (VOUT=5V, R(FS)=68kΩ) IOUT-frequency (VOUT=5V, R(FS)=68kΩ)

500 500
EN1
5V/div
PGOOD1 450 450

2V/div
frequency [kHz]

frequency [kHz]

400 400
EN2 VIN=7.5V VIN=7.5V
VIN=12V VIN=12V
5V/div VIN=18V VIN=18V
350 350
PGOOD2
2V/div
300 300
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
IOUT [A] IOUT [A]

Fig.43Wake up waveform Fig.44 Io-frequency Fig.45 Io-frequency

(EN1/2→PGOOD1/2) (Vo=5V, PWM, RFS=68kΩ) (Vo=3.3V, PWM, RFS=68kΩ)

2.5 700 5.500

5.000
600
VOUT=5V VOUT=5V 4.500
2 VIN=7.5V(-5℃）
VOUT=3.3V 500 VOUT=3.3V 4.000 VIN=21V（-5℃）
VIN=7.5V(75℃）
frequency [kHz]
ONTIME [usec]

3.500
VIN=21V（75℃）
1.5
400
VOUT [V]

3.000

2.500
300
1
2.000

200 1.500

0.5 1.000
100
0.500

0 0 0.000
0 2 4 6 8 10 12 14 16
0 50 100 150 0 50 100 150
RFS [kΩ] RFS [kΩ] IOUT [A]

Fig.46 FS-ONTIME Fig.47 FS-frequency Fig.48 Ta-IOCP

(Vo=5V)

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BD9528MUV Technical Note

●Electrical characteristic curves (Reference data) – Continued

IOUT - REG1 voltage IOUT - REG2 voltage

3.500
5.1 3.4

3.000
5 3.3
VIN=7.5V(-5℃）

REG2 voltage [V]

2.500 VIN=21V（-5℃）

REG1 voltage [V]

4.9 3.2
VIN=7.5V(75℃）
VIN=21V（75℃）
2.000
VOUT [V]

4.8 3.1

1.500
4.7 3
1.000
2.9
4.6
0.500
2.8
4.5
0.000 0 50 100 150 200 250
0 2 4 6 8 10 12 14 16
0 50 100 150 200 250
IOUT [mA]
IOUT [A] IOUT [mA]

Fig.49 Ta-IOCP Fig.50 IREG1-REG1 Fig.51 IREG2-REG2

(Vo=3.3V)

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BD9528MUV Technical Note

●Pin Descriptions
・VIN (30 pin)
This is the main power supply pin. The input supply voltage range is 5.5V to 25V. The duty cycle of BD9528MUV is
determined by input voltage and control output voltage. Therefore, when VIN voltage fluctuated, the output voltage also
becomes unstable. Since VIN line is also the input voltage of switching regulator, stability depends on the impedance of the
voltage supply. It is recommended to establish bypass capacitor and CR filter suitable for the actual application.
・CTL (9 pin)
When CTL pin voltage is at least 2.3V, the status of the linear regulator output becomes active (REG1=5V, REG2=3.3V).
Conversely, the status switches off when CTL pin voltage goes lower than 0.8V. The switching regulator doesn’t become
active when the status of CTL pin is low, if the status of EN pin is high.
(※CTL pin is connected to VIN pin with 1MΩ resistor(pull up) internal IC)
・EN1, 2 (21 pin, 4 pin)
When EN pin voltage is at least 2.3V, the status of the switching regulator becomes active. Conversely, the status switches
off when EN pin voltage goes lower than 0.8V.
(※EN pin is connected to AGND pin with 1MΩ resistor(pull down) internal IC)

・REG1 (29 pin)

This is the output pin for 5V linear regulator and also active in power supply for driver and control circuit of the inside. The
standby function for REG1 is determined by CTL pin. The voltage is 5V, with 100mA current ability. It is recommended that
a 10μF capacitor (X5R or X7R) be established between REG1 and GND.
・REG2 (28 pin)
This is the output pin for 3.3V linear regulator. The standby function for REG2 is determined by CTL. The voltage is 3.3V,
with 50mA current ability. It is recommended that a 10μF capacitor (X5R or X7R) be established between REG2 and GND.
・REF (12 pin)
This is the setting pin for output voltage of switching regulator. This IC controls the voltage in the status of REF≒FB.
・FB 1, 2 (14 pin, 11 pin)
This is the feedback pin from the output of switching regulator. This IC controls the voltage in the status of REF≒FB.
・Vo1 (27 pin)
This is the output discharge pin, and output voltage feedback pin for frequency setting. When the voltage is beyond 4.4V
from the external power supply during operation, it supplies REG1.
・Vo2 (7 pin)
This is the output discharge pin, and output voltage feedback pin for frequency setting.
・SS1, 2 (19 pin, 6 pin)
This is the setting pin for soft start. The rising time is determined by the capacitor connected between SS and GND, and
the fixed current inside IC after it is the status of low in standby mode. It controls the output voltage till SS voltage catch up
the REF pin to become the SS terminal voltage.
・FS1, 2 (15 pin, 10 pin)
This is the input pin for setting the frequency. It is available to set it in frequency range is 200KHz to 500kHz.
・ILIM1, 2 (17 pin, 8 pin)
BD9528MUV detects voltage differential between SW and PGND, and set OCP. OCP setting current value is determined
by the resistance value of ILIM pin. FET of various Ron is available.

・PGOOD 1, 2 (20 pin, 5 pin)

This is the open drain pin for deciding the output of switching regulator.
・MCTL1, 2 (18 pin, 16 pin)
This is the switching shift pin for SLLM (Simple Light Load Mode). MCTL pin is at low level when it goes lower than 0.8V,
and at high level when it goes higher than 2.3V.
(※MCTL pin is connected to AGND pin with 500kΩ resistor(pull down) internal IC)

・AGND (13 pin)

This is the ground pin.

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BD9528MUV Technical Note

・BOOT1, 2 (22 pin, 3 pin)

This is the power supply pin for high side FET driver. The maximum voltage range to GND pin is to 35V, to SW pin is to 7V.
In switching operations, the voltage swings from (VIN+REG1) to REG1 by BOOT pin operation.
・HG1, 2 (23 pin, 2 pin)
This is the highside FET gate drive pin. It is operated in switching between BOOT to SW. In case the output MOS is 3ohm
/the status of Hi, 2ohm/the status of Low, it is operated hi-side FET gate in high speed.
・SW1, 2 (24 pin, 1 pin)
This is the ground pin for high side FET drive. The maximum voltage range to GND pin is to 30V. Switching operation
swings from the status of BOOT to the status of GND.
・LG1, 2 (26 pin, 31 pin)
This is the lowside FET gate drive pin. It is operated in switching between REG1 to PGND. In case the output MOS is
2ohm /the status of Hi, 0.5ohm/the status of Low, it is operated low-side FET gate in high speed.
・PGND1, 2 (25 pin, 32 pin)
This is the ground pin for low side FET drive.

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BD9528MUV Technical Note

●Explanation of Operation
3
The BD9528MUV is a 2ch synchronous buck regulator controller incorporating ROHM’s proprietary H REG CONTROLLA
control system. Because controlling of output voltage by a comparator, high response is realized with not relying on the
switching frequency. And, when VOUT drops due to a rapid load change, the system quickly restores VOUT by extending
the TON time interval. Thus, it serves to improve the regulator’s transient response. Activating the Light Load Mode will also
exercise Simple Light Load Mode (SLLM) control when the load is light, to further increase efficiency.
VIN
H3RegTM control

Comparator for
output voltage Vout/Vin
control Circuit HG
FB
A VOU
SW T
B Driver

Internal LG
reference Transient
voltage Circuit
REF

(Normal operation)
FB When FB falls to a reference voltage (REF), the drop is
detected, activating the H3REG CONTROLLA
REF
system.<Route A>
（ tON= VOUT × 1 [sec]・・・(1) ）
HG
VIN f
HG output is determined by the formula above.
LG After the status of HG is OFF, LG go on outputting until
output voltage become FB=REF.

(VOUT drops due to a rapid load change)

FB
When VOUT drops due to a rapid load change, and the
REF voltage remains below reference voltage after the
programmed tON time interval has elapsed (Output of a
Io tON +α comparator for output voltage control =H), the system
quickly restores VOUT by extending the tON time,
HG improving the transient response.<Route B> After VOUT
restores (FB=REF), HG turns to be OFF, and it goes back
to a normal operation.
LG

(when VIN drops)

VIN
tON1 tON2 tON3 tON4 tON4+α

H3RegTM
HG
tOFF1 t OFF2 t OFF3 tOFF4=tOFF3 tOFF4=t OFF3

LG

FB

REF FB=REF
Output voltage drops

If VIN voltage drops because of the battery voltage fall, ontime tON and offtime tOFF is determined by the following formula:
tON=VOUT/VIN×I/f and tOFF=(VIN-VOUT)/VIN×f so that tON lengthen and tOFF shorten to keep output voltage constant. However,
if VIN still drops and tOFF equals to tminoff (tminoff：Minimum OFF time, regulated inside IC) , because tOFF cannot shorten any
3 TM
more, as a result output voltage drops. In H Reg system, lengthening tON time than regulated tON (lengthen tON time until FB＞REF)

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 BD9528MUV Technical Note

enables to operate stable not to drop the output voltage even if VIN turns to be low. With the reason above, it is suitable for
2-cell battery.

Light Load Control

(SLLM)
FB
In SLLM, when the status of LG is OFF and the coil
REF
current is within 0A (it flows to SW from VOUT.), SLLM
HG function is operated to prevent output next HG. The
status of HG is ON, when FB falls below reference voltage
again.
LG

0A

(QLLM) FB
REF In QLLM, when the status of LG is OFF and the coil
current is within 0A (it flows to SW from VOUT.), QLLM
HG function is operated to prevent output next HG.
Then, FB falls below the output programmed voltage
within the programmed time (typ=40μs), the status of HG
LG is ON. In case FB doesn’t fall in the programmed time, the
status of LG is ON forcedly and VOUT falls. As a result,
he status of next HG is ON.
0A

MCTL1 MCTL2 Control mode Running The BD9528MUV operates in PWM mode until SS pin
L L SLLM PWM reaches cramp voltage (2.5V), regardless of the control
L H QLLM PWM mode setting, in order to operate stable during the
operation. .
H X PWM PWM

3 TM
＊Attention: H Reg CONTROLLA monitors the supplying current from
capacitor to load, using the ESR of output capacitor, and realize
the rapid response. Bypass capacitor used at each load (Ex.
Ceramic capacitor) exercises the effect with connecting to each COUT Load
load side. Do not put a ceramic capacitor on COUT side of power
supply.

● Timing Chart
• Soft Start Function Soft start is exercised with the EN pin set high. Current
control takes effect at startup, enabling a moderate
EN
output voltage “ramping start.” Soft start timing and
TSS incoming current are calculated with formulas (2) and
(3) below.
SS Soft start time

[sec] ・・・(2)
REF×Css
Tss=
2.3μA(typ)
VOUT
Incoming current

IIN= Co×VOUT [A] ・・・(3)

IIN
Tss

(Css: Soft start capacitor; Co: Output capacitor)

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BD9528MUV Technical Note

Notes when waking up with CTL pin or VIN pin

If EN pin is High or short (or pull up resistor) to REG1 pin, IC starts up by switching CTL pin, the IC might fail to start up (SCP
function) with the reason below, please be careful of SS pin and REF pin capacitor capacity.

REG1 REG2 FB
VIN

CTL Inner BG
reference
circuit SCP circuit

Delay SCP
REF
SCP_REF 1ms(typ.)

SCP

PWM
SS (Switching control signal)

CTL
(VIN)
REG1
REG2
REG1 UVLO cancellation
REG1, REG2

BG
0.49V(typ)

SCP_REF
(REF start-up time＜SS start-up time)
SCP function masked SCP mask cancellation
REF FB starts up as SS reference

SS
FB
SS
FB
(REF start-up time＞SS start-up time)

REF SCP mask cancellation

SCP mask FB starts up as REF reference
FB

After the end of SS wake-up,

SS within SCP delay time (1ms), if
SCP function is masked until SS pin reaches REF voltage does not reach
cramp voltage (2.5V). SCP_REF(0.49V), SCP turns
ON and shut down.

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BD9528MUV Technical Note

●Output Discharge

It will be available to use if connecting VOUT pin to DC/DC output.

VIN,CTL (Total about 100Ω) . Discharge function operates when ①EN=’L’
②UVLO=ON(If input voltage is low) ③SCP Latch time ④TSD=ON.
EN The function at output discharge time is shown as left.

VOUT (1)during EN=’H’→‘L’

If EN pin voltage is below than EN threshold voltage, output
discharge function is operated, and discharge output capacitor
charge.

VIN, CTL (2) during VIIN=CTL=H→0V

① IC is in normal operation until REG1 voltage becomes lower than
REG1
UVLO voltage. However, because VIN voltage also becomes low,
output voltage will drop, too.
VOUT ② If REG1 voltage reaches the UVLO voltage, output discharge
The efficiency of
VIN voltage drop function is operated, and discharge output capacitor charge.
Output Discharge
③ In addition, if REG1 voltage drops, inner IC logic cannot operate, so
that output discharge function does not work, and becomes output
Output Hi-Z Hi-z. （In case, FB has resistor against GND, discharge at the
UVLO ON resistor.）

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BD9528MUV Technical Note

・Timer Latch Type Short Circuit Protection

FB Short protection kicks in when output falls to or below
REF×0.7 REF X 0.7.
When the programmed time period elapses, output is
latched OFF to prevent destruction of the IC. (HG=Low,
LG=Low) Output voltage can be restored either by
1ms(typ) reconnecting the EN pin or disabling UVLO.
SCP

EN / UVLO

・Over Voltage Protection

FB REF×1.2
When output rise to or above REF×1.2 (typ), output
over voltage protection is exercised, and low side FET
goes up maximum for reducing output.(LG=High,
HG HG=Low).When output falls, output voltage can be
restored., and go back to the normal operation.

LG

Switching
・Over current protection circuit

tON tON tON tON

During the normal operation, when FB becomes less
HG than REF, HG becomes High during the time tON, and
after HG becomes OFF, it output LG.
However, when inductor current exceeds ILIMIT threshold,
next HG pulse doesn’t pulsate until it is lower than ILIMIT
LG level.

IL

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BD9528MUV Technical Note

● External Component Selection

1. Inductor (L) selection

The inductor value is a major influence on the output ripple

current. As formula (4) below indicates, the greater the inductor or
ΔIL
the switching frequency, the lower the ripple current.
(VIN-VOUT)×VOUT
VIN ΔIL= [A]・・・(4)
L×VIN×f
The proper output ripple current setting is about 30% of maximum
IL output current.
ΔIL=0.3×IOUTmax. [A]・・・(5)
VOUT
L (VIN-VOUT)×VOUT
L= [H]・・・(6)
Co ΔIL×VIN×f
(ΔIL: output ripple current; f: switch frequency)

Output ripple current

※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease
system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the
inductor rated current value.
※To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance.

2.Output Capacitor (CO) Selection

VIN
When determining the proper output capacitor, be sure to factor in the
equivalent series resistance required to smooth out ripple volume and maintain
a stable output voltage range.
VOUT Output ripple voltage is determined as in formula (7) below.
L
ESR ΔVOUT=ΔIL×ESR+ESL×ΔIL/TON・・・(7)
Co (ΔIL: Output ripple current; ESR: CO equivalent series resistance)
※ In selecting a capacitor, make sure the capacitor rating allows sufficient
margin relative to output voltage. Note that a lower ESR can minimize output
Output Capacitor ripple voltage.

Please give due consideration to the conditions in formula (8) below for output capacity, bear in mind that output rise time
must be established within the soft start time frame. Capacitor for bypass capacitor is connected to Load side which connect
to output in output capacitor capacity (CEXT, figure above). Please set the soft start time or over current detecting value,
regarding these capacities.
Tss×(Limit-IOUT) Tss: Soft start time
Co≦ ・・・(8)
VOUT Limit: Over current detection

Note: Improper capacitor may cause startup malfunctions.

3. Input Capacitor (Cin) Selection

VIN The input capacitor selected must have low enough ESR resistance to fully
support large ripple output, in order to prevent extreme over current. The
Cin
formula for ripple current IRMS is given in (9) below.

VOUT √VIN(VIN-VOUT)
L IRMS=IOUT× [A]・・・(9)
Co VIN
IOUT
Where VIN=2×VOUT, IRMS=
2

Input Capacitor

A low ESR capacitor is recommended to reduce ESR loss and maximize efficiency.

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BD9528MUV Technical Note

4. MOSFET Selection
MOSFET may cause the loss as below, so please select proper FET for each.
VIN ＜Loss on the main MOSFET＞
Pmain=PRON+PGATE+PTRAN
main switch
2
VOUT VIN ×Crss×IOUT×f
= ×RON×IOUT2+Ciss×f×VDD+ ・・・(10)
VOUT VIN IDRIVE
L
(Ron: On-resistance of FET; Ciss: FET gate capacitance;
Co f: Switching frequency Crss: FET inverse transfer function;
IDRIVE: Gate peak current)

synchronous switch
＜Loss on the synchronous MOSFET＞

Psyn=PRON+PGATE
VIN-VOUT
= ×RON×IOUT2+Ciss×f×VDD ・・・(11)
VIN

5. Setting output voltage

This IC is operated that output voltage is REF≒FB.
And it is operated that output voltage is feed back to FB pin.

<Output Voltage>
(R1  R2) 1 (⊿VOUT:Output ripple voltage)
V OUT   REF(0.7V)  ⊿V OUT (⊿Iripple: ripple current of coil, ESR: ESR of output capacitor)
R2 2
⊿V OUT  ⊿I Ripple  ESR (L:inductance[H] f:switching frequency[Hz])
V OUT
⊿I Ripple  (V IN  V OUT ) 
(L  V IN  f)

※(Notice) Please set ⊿VOUT more than 20mV

Ex. VIN=20V,VOUT=5V,f=300kHz,L=2.5uH,ESR=20mΩ,R1=56KΩ,R2=9.1kΩ
-6 3
⊿Iripple=(20V-5V)×5V/(2.5×10 H×20V×300×10 Hz)=5[A]
-3
⊿VOUT=5A×20×10 Ω=0.1[V]
VOUT=(51kΩ+9.1kΩ)/9.1kΩ+1/2×0.1V=5.057[V]

Select (R1 + R2) under 100KΩ(recommend)

VIN VIN

H3REG R Q SLLM
Output voltage
CONTROLLA Driver
S
SLLM Circuit

FB

VIN
R1
R2

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BD9528MUV Technical Note

6. Setting over current protection

VIN

Detecting the ON resistance (between SW and PGND

L voltage) of MOSFET at low side, it set the over current
VOUT voltage protection.
SW
Over current reference voltage (ILIM_ref) is determined as in
formula(12) below.
Co

PGND 10×103
RILIM ILIM_REF = [A]・・・(12)
RILIM[KΩ]×RON[mΩ]

(RILIM: Resistance for setting of over current voltage protection value[kΩ]

RON: Low side ON resistance value of FET[mΩ])
However, the value, which set the over current protection actually, is
determined by the formula (13) below.
Coil current
1
Iocp Iocp= ILIM_ref + △IL
2
1 I × Vo ・・・(13)
ILIM_ref = ILIM_ref + × VIN - Vo ×
2 L f VIN
(△IL：Coil ripple current[A], VIN：Input voltage[V], Vo：Output voltage[V]
ｆ：Switching frequency[HZ], L：Coil inductance[H])
(Example)
If load current 5A want to be realized with VIN=6～19V, VOUT=5V, ｆ=400kHZ, L=2.5uH, RON=20mΩ, the formula would be
below.
10k 1 I × Vo ＞ 5
Iocp= + × VIN - Vo ×
RILIM[kΩ] ×RON[mΩ] 2 L f VIN
When VIN=6V, Iocp will be minimum(this is because the ripple current is also minimum) so that if each condition is input,
the formula will be the following: RILIM＜109.1[kΩ].
※To design the actual board, please consider enough margin for FET ON resistor dispersion, Coil inductor dispersion, IC over
current reference value dispersion, frequency dispersion.

7. Relation between output voltage and TON time

The BD9528MUV, both 1ch and 2ch, are high efficiency synchronous regulator controller with frequency variable.
TON time varies with Input voltage [VIN], output voltage [VOUT], and RFS of FS pin resistance.
TON time is calculated with the following formula:
VOUT・RFS
TON =k [nsec]・・・(14)
VIN
From TON time above, frequency on application condition is following:
VOUT 1
[kHz]・・・(15)
Frequency = ×
VIN Ton
However, real-life considerations (such as the external MOSFET gate capacitor and switching speed) must be factored in
as they affect the overall switching rise and fall time, so please confirm in reality by the instrument.

3.5
2.5 1
VIN=7V VIN=7V
3 0.9
VIN=12V VIN=12V VIN=7V
2 0.8
VIN=21V VIN=21V
2.5 VIN=12V
0.7
VIN=21V
ontime[us]
ontime[us]

0.6
ontime[us]

2 1.5
0.5
1.5
1 0.4
1 0.3
0.5 0.2
0.5
0.1
0 0 0
0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120
RFS[kΩ] RFS[kΩ] RFS[kΩ]

RFS – ontime(VOUT=5V) RFS – ontime(VOUT=3.3V) RFS – ontime(VOUT=1V)

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BD9528MUV Technical Note

8. Relation between output voltage and frequency

Because the BD9528MUV is TON time focused regulator controller, if output current is up, switching loss of Coil, MOSFET
and output capacitor will increase, and frequency will be fast.
Loss of each Coil, MOSFET and output capacitor are below.
2
① Coil loss = IOUT × DCR
VOUT
2
② MOSFET(High Side) loss = IOUT × Ronh ×
VIN
2 VOUT
③ MOSFET(Low Side) loss = IOUT × Ronl × (1- )
VIN

(Ronh : ON resistance of high side MOSFET, Ronl : ON resistance of low side MOSFET,
ESR : Output capacitor equivalent cascade resistance)

Regarding those loss above and frequency formula, it is determined below.

VIN × IOUT × TON

T (=1/Freq) = ・・・(16)
VOUT × IOUT + ① + ② + ③

However, real-life considerations (such as parasitic resistance element of Layout pattern) must be factored in as they affect
the loss, please confirm in reality by the instrument.

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BD9528MUV Technical Note

●I/O Equivalent Circuit

1, 24pin (SW2, SW1) 2, 23pin (HG2, HG1) 3, 22pin (BOOT2, BOOT1)

BOOT BOOT
BOOT
HG

HG

SW
SW

4, 21pin (EN2, EN1) 5, 20pin (PGOOD2, PGOOD1) 6, 19pin (SS2, SS1)

REG1

12pin (REF) 11, 14pin (FB2, FB1) 10, 15pin (FS2, FS1)
REG1

16, 18pin (MCTL2, MCTL1) 9pin (CTL) 26, 31pin (LG1, LG2)
VIN

REG1

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BD9528MUV Technical Note

●I/O Equivalent Circuit

7, 27pin (Vo2, Vo1) 28pin (REG2) 29pin (REG1)

REG1
VIN VIN

30pin (VIN) 8, 17pin (ILIM2, ILIM1)

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BD9528MUV Technical Note

●Evaluation Board Circuit (Vo1=5V/8A f1=300kHz Vo2=3.3V/8A f2=300kHz)

VIN VIN VIN
7V～28V
BD9528MUV
R1
30
VIN
VIN CTL R9
C1 22
CTL R2 BOOT1 C9 C10
9
CTL R10
C7
REG1 EN1 23 Q2
HG1 SW1 VO1
EN1 R3 L1
21 24
EN1 SW1
REG1 EN2 C13 C14 C15 C16 C17
D1
EN2 R4 C23
4 R17
EN2 26
R11 Q1
REG1
LG1
29
5V REG1
C2 25
PGND1
REG2
3.3V 28 14
REG2 FB1 C24
C3
R18

12
REF Vo1
27
C4 VIN VIN

19
SS1 R12
3
BOOT2
6 SS2 C8
R13 C11 C12
2 Q4
C5 C6 HG2 VO2
SW2
L2
1
17
ILIM1 SW2
C18 C19 C20 C21 C22
R5 R14
Q3 R19 C25
31 D2
8
LG2
ILIM2 32
PGND2
R6
11
FB2
15 C26
FS1 R20
R7
7
Vo2 REG1 PGOOD1
10
FS2
R15
R8
MCTL1 PGOOD1 20
REG1 PGOOD2
18
MCTL1
R28 R16
5
PGOOD2
MCTL2

16
MCTL2 AGND
R27
13

DESIGNATION RATING PART No. COMPANY DESIGNATION RATING PART No. COMPANY
R1 0Ω - - C7 0.47uF(10V) GRM188B11A474KD MURATA
R2 - - - C8 0.47uF(10V) GRM188B11A474KD MURATA
R3 0Ω - - C9 10uF(25V) CM32XR7106M25A KYOCERA
R4 0Ω - - C10 - - -
R5 68kΩ MCR03 ROHM C11 10uF(25V) CM32XR7106M25A KYOCERA
R6 68kΩ MCR03 ROHM C12 - - -
R7 75kΩ MCR03 ROHM C13 330uF 6TPE330MI SANYO
R8 75kΩ MCR03 ROHM C14 - - -
R9 0Ω - - C15 - - -
R10 0Ω - - C16 - - -
R11 0Ω - - C17 - - -
R12 0Ω - - C18 330uF 6TPE330MI SANYO
R13 0Ω - - C19 - - -
R14 0Ω - - C20 - - -
R15 100kΩ MCR03 ROHM C21 - - -
R16 100kΩ MCR03 ROHM C22 - - -
R17 91kΩ MCR03 ROHM C23 - - -
R18 15kΩ MCR03 ROHM C24 - - -
R19 30kΩ MCR03 ROHM C25 - - -
R20 8.2kΩ MCR03 ROHM C26 - - -
R27 0Ω - - D1 Diode RSX501L-20 ROHM
R28 0Ω - - D2 Diode RSX501L-20 ROHM
C1 10uF(25V) CM32X7R106M25A KYOCERA L1 2.5uH CDEP105NP-2R5MC-32 Sumida
C2 10uF(6.3V) GRM21BB10J106KD MURATA L2 2.5uH CDEP105NP-2R5MC-32 Sumida
C3 10uF(6.3V) GRM21BB10J106KD MURATA Q1 FET uPA2709 NEC
C4 0.1uF(6.3V) GRM21BB10J104KD MURATA Q2 FET uPA2709 NEC
C5 2200pF(50V) GRM188B11H102KD MURATA Q3 FET uPA2709 NEC
C6 2200pF(50V) GRM188B11H102KD MURATA Q4 FET uPA2709 NEC
U1 - BD9528MUV ROHM

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BD9528MUV Technical Note

●Evaluation Board Circuit for Low input voltage(Vo1=5V/8A f1=300kHz Vo2=3.3V/8A f2=300kHz)
VIN VIN VIN
6V～28V
BD9528MUV
R1
30
VIN
VIN CTL R9
C1 22
CTL R2 BOOT1 C9 C10
9
CTL R10
C7
REG1 EN1 23 Q2
HG1 SW1 VO1
EN1 R3 L1
21 24
EN1 SW1
REG1 EN2 C13 C14 C15 C16 C17
D1
EN2 R4 C23
4 R17
EN2 26
R11 Q1
REG1
LG1
29
5V REG1
C2 25
PGND1
REG2
3.3V 28 14
REG2 FB1 C24
C3
R18

12
REF Vo1
27
C4 VIN VIN

19
SS1 R12
3
BOOT2
6 SS2 C8
R13 C11 C12
2 Q4
C5 C6 HG2 VO2
SW2
L2
1
17
ILIM1 SW2
C18 C19 C20 C21 C22
R5 R14
Q3 R19 C25
31 D2
8
LG2
ILIM2 32
PGND2
R6
11
FB2
15 C26
FS1 R20
R7
7
Vo2 REG1 PGOOD1
10
FS2
R15
R8
MCTL1 PGOOD1 20
REG1 PGOOD2
18
MCTL1
R28 R16
5
PGOOD2
MCTL2

16
MCTL2 AGND
R27
13

DESIGNATION RATING PART No. COMPANY DESIGNATION RATING PART No. COMPANY
R1 0Ω - - C7 0.47uF(10V) GRM188B11A474KD MURATA
R2 - - - C8 0.47uF(10V) GRM188B11A474KD MURATA
R3 0Ω - - C9 10uF(25V) CM32XR7106M25A KYOCERA
R4 0Ω - - C10 - - -
R5 68kΩ MCR03 ROHM C11 10uF(25V) CM32XR7106M25A KYOCERA
R6 68kΩ MCR03 ROHM C12 - - -
R7 75kΩ MCR03 ROHM C13 330uF 6TPB330ML SANYO
R8 75kΩ MCR03 ROHM C14 - - -
R9 0Ω - - C15 - - -
R10 10Ω - - C16 - - -
R11 10Ω - - C17 - - -
R12 0Ω - - C18 330uF 6TPE330MI SANYO
R13 10Ω - - C19 - - -
R14 10Ω - - C20 - - -
R15 100kΩ MCR03 ROHM C21 - - -
R16 100kΩ MCR03 ROHM C22 - - -
R17 56kΩ MCR03 ROHM C23 10pF(50V) - -
R18 9.1kΩ MCR03 ROHM C24 - - -
R19 30kΩ MCR03 ROHM C25 - - -
R20 8.2kΩ MCR03 ROHM C26 - - -
R27 0Ω - - D1 Diode RSX501L-20 ROHM
R28 0Ω - - D2 Diode RSX501L-20 ROHM
C1 10uF(25V) CM32X7R106M25A KYOCERA L1 2.5uH CDEP105NP-2R5MC-32 Sumida
C2 10uF(6.3V) GRM21BB10J106KD MURATA L2 2.5uH CDEP105NP-2R5MC-32 Sumida
C3 10uF(6.3V) GRM21BB10J106KD MURATA Q1 FET uPA2709 NEC
C4 0.1uF(6.3V) GRM21BB10J104KD MURATA Q2 FET uPA2709 NEC
C5 2200pF(50V) GRM188B11H102KD MURATA Q3 FET uPA2709 NEC
C6 2200pF(50V) GRM188B11H102KD MURATA Q4 FET uPA2709 NEC
U1 - BD9528MUV ROHM

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BD9528MUV Technical Note

●Handling method of unused pin during using only DC/DC 1ch

If using only 1ch DC/DC and 2ch pin is set to be off at all times, please manage the unused pin as diagram below.

PIN No, PIN name Management

1 SW2 GND
2 HG2 Open
3 BOOT2 Open
4 EN2 GND
5 PGOOD2 GND
6 SS2 GND
7 Vo2 GND
8 ILIM1 GND
10 FB2 GND
11 FS2 GND
31 LG2 Open

VIN VIN VIN

12V
BD9528MUV
R1
30
VIN
VIN CTL R9
C1 22
CTL R2 BOOT1 C9 C10
9
CTL R10
C7
REG1 EN1 23 Q2
HG1 SW1 VO1
EN1 R3 L1
21 24
EN1 SW1
C13 C14 C15 C16 C17
D1
C23
4 R17
EN2 26
R11 Q1
REG1
LG1
29
5V REG1
C2 25
PGND1
REG2
3.3V 28 14
REG2 FB1 C24
C3
R18

12
REF Vo1
27
C4

19
SS1
3
BOOT2
6 SS2
2
C5 HG2
1
17
ILIM1 SW2
R5

8
LG2
ILIM2 32
PGND2
10
FB2
15
FS1
R7
7
Vo2 REG1 PGOOD1
10
FS2
R15
MCTL1 PGOOD1 20

18
MCTL1
R28
5
PGOOD2
MCTL2

16
MCTL2 AGND
R27
13

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BD9528MUV Technical Note

●Example of PCB layout

L Vo1

Co
⑥
③ ⑤
L-FET
(CH1) ‘Silent’GND

(CH1) High current GND

C
C

R
H-FET

④
Cin

BOOT1

SS1
SW1

HG1

EN1

PGOOD1

ILMI1
MCTL1
PGND1
LG1
MCTL2
FS1
R
Vo1 FB1 R

VIN ①
REG2

REG1

VIN
AGND

REF

FB2
R
R
C

LG2 FS2
PGOOD2
BOOT2

PGND2

ILIM2
CTL
Cin

SW2

HG2

EN2

SS2

Vo2

R
H-FET R
②
C
C

(CH2)
High current GND

⑤
‘Silent’GND
L-FET
(CH2)

③
⑥
Co
L Vo2

①Because high pulse current rush into power loop, consisted of input capacitor Cin, Output inductor L, and Output capacitor
Co, this part layout should be built, including GND pattern, at parts side (upper side). Also ,please avoid to draw via formation in
power loop line. (The reason is that it will be a factor of noise because via oneself holds some nH parasitic inductance)
②FB pin has comparatively high impedance, so floating capacity should be minimum as possible. And feedback wiring from
output should be taken properly, and put on shield, not going through around L (because of magnetic). Please be careful in
drawing)
③Trace from SW node pin to inductor should be cut short . And both inductor element pattern should be kept away. (Closer
wiring has SW node noise influence Vo by parasitic capacity between wiring ). This layout example shows that SW node is
outside, but if the application board will be like that , SW node should be shielding, and consider the influence to other circuit.
④Input capacitor Cin should be placed cloase to IC with low inductance and low impedance . If that is difficult, please place a
capacitor for high frequency removal with PKG size small like 0.1uF (ESL small).
⑤2 layer and 3 layer are plain GND, so connect from parts side GND to plain GND by low impedance with many via as possible.
Inner GND is only for shielding, so that not to form loop for high current .
⑥Please take GND pattern space widely, and design layout to be able to increase radiation efficiency.
⑦FS pin nad ILIM pin has high impedance. External resistor should be connected to “Silent GND”.

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BD9528MUV Technical Note

Input current A
Input current B
Vin

SW pin voltage
DC/DC Inductor current

H3Reg Vout
controller

Feed back line

Power GND Power GND

GND

Analog GND Output current GND Output current GND

This part is shortened.

Vin
Current leveled Pulsed current flows by
current
current

By capacitor Charger ON/OFF of the switch

current

Cin

t t
Input current A Input current B

Noise output !!
This part is shortened. The noise has decreased
by LC filter
L
SW Vout
Inductor ripple current
Voltage

current

Vin
Cout
Output current

0V t t
SW pin voltage Inductor current

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BD9528MUV Technical Note

The influence of inductor is noted

The impedance of the output is low

= It may be long

L
SW Vout

FB Cout

The impedance of this line is high

This distance is shorted

as much as possible
The impedance of FB pin is higher

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BD9528MUV Technical Note

●Notes for use

1. This integrated circuit is a monolithic IC, which (as shown in the figure below), has P+ isolation in the P substrate and
between the various pins. A P-N junction is formed from this P layer and N layer of each pin, with the type of junction
depending on the relation between each potential, as follows:
 When GND＞ element A＞ element B, the P-N junction is a diode.
 When element B＞GND element A, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference
among circuits, as well as operating malfunctions and physical damage. Therefore, be careful to avoid methods by which
parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an input pin.

Resistor Transistor (NPN)

Pin A Pin B B Pin B
C
E
Pin A
B C
N N N
+ + P+ +
P P P Parasitic P P
N N N E
element
P substrate P substrate Parasitic
GND
GND GND GND
Parasitic element Parasitic element Other adjacent elements

2. In some modes of operation, power supply voltage and pin voltage are reversed, giving rise to possible internal circuit
damage. For example, when the external capacitor is charged, the electric charge can cause a VCC short circuit to the
GND. In order to avoid these problems, inserting a VCC series countercurrent prevention diode or bypass diode between
the various pins and the VCC is recommended.

Bypass diode

Counter current prevention diode

VCC

Pin

3. Absolute maximum rating

Although the quality of this IC is rigorously controlled, the IC may be destroyed when applied voltage or operating temperature
exceeds its absolute maximum rating. Because short mode or open mode cannot be specified when the IC is destroyed, it is important
to take physical safety measures such as fusing if a special mode in excess of absolute rating limits is to be implemented.

4.GND potential
Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the operating
mode.

5. Thermal design
In order to build sufficient margin into the thermal design, give proper consideration to the allowable loss (Power Dissipation)
in actual operation.

6. Short-circuits between pins and incorrect mounting position

When mounting the IC onto the circuit board, be extremely careful about the orientation and position of the IC. The IC may
be destroyed if it is incorrectly positioned for mounting. Do not short-circuit between any output pin and supply pin or ground,
or between the output pins themselves. Accidental attachment of small objects on these pins will cause shorts and may
damage the IC.

7. Operation in strong electromagnetic fields

Use in strong electromagnetic fields may cause malfunctions. Use extreme caution with electromagnetic fields.

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BD9528MUV Technical Note

8. Thermal shutdown circuit

This IC is provided with a built-in thermal shutdown (TSD) circuit, which is activated when the operating temperature reaches
175℃ (standard value), and has a hysteresis range of -15℃ (standard value). When the IC chip temperature rises to the
threshold, all the inputs automatically turn OFF. Note that the TSD circuit is provided for the exclusive purpose shutting down
the IC in the presence of extreme heat, and is not designed to protect the IC per se or guarantee performance when or after
extreme heat conditions occur. Therefore, do not operate the IC with the expectation of continued use or subsequent
operation once the TSD is activated.

9. Capacitor between output and GND

When a larger capacitor is connected between the output and GND, Vcc or VIN shorted with the GND or 0V line – for any
reason – may cause the charged capacitor current to flow to the output, possibly destroying the IC. Do not connect a
capacitor larger than 1000uF between the output and GND.

10. Precautions for board inspection

Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be certain
to use proper discharge procedure before each process of the operation. To prevent electrostatic accumulation and
discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage, and
continue observing ESD-prevention procedures in all handling, transfer and storage operations. Before attempting to
connect components to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply is
OFF before removing any component connected to the test setup.

11. GND wiring pattern

When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming
from the wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way,
care must be taken to avoid wiring pattern fluctuations in any connected external component GND.

●Thermal Derating Curve

◎ VQFN032V5050

[mW]

1000

74.2mm×74.2mm×1.6mm Glass-epoxy PCB

880mW θj-a=142.0℃/W
800
Power Dissipation [Pd]

600

IC Only θj-a=328.9℃/W

400
380mW

200

0 25 50 75 100 125 150 [℃]

Ambient Temperature [Ta]

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32/33 2010.03 - Rev.A
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BD9528MUV Technical Note

●Ordering part number

B D 9 5 2 8 M U V - E 2

Part No. Part No. Package Packaging and forming specification

MUV: VQFN032V5050 E2: Embossed tape and reel

VQFN032V5050
<Tape and Reel information>
5.0±0.1
Tape Embossed carrier tape
5.0 ± 0.1

Quantity 2500pcs
E2
Direction
1PIN MARK The direction is the 1pin of product is at the upper left when you hold
of feed ( reel on the left hand and you pull out the tape on the right hand )
1.0MAX

S
(0.22)
+0.03
0.02 -0.02

0.08 S
3.4±0.1
C0.2
1 8
32 9
0.4 ± 0.1

3.4 ± 0.1

25 16
24 17
0.75
+0.05 1pin Direction of feed
0.5 0.25 -0.04

(Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity.

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 Notice

Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.

The content specified herein is subject to change for improvement without notice.

The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.

The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
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The Products specified in this document are intended to be used with general-use electronic
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Please be sure to implement in your equipment using the Products safety measures to guard
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R1010A