Zero-Drift, Single-Supply,

a Rail-to-Rail Input/Output
Operational Amplifiers
AD8551/AD8552/AD8554
FEATURES PIN CONFIGURATIONS
Low Offset Voltage: 1 ␮V
Input Offset Drift: 0.005 ␮V/ⴗC 8-Lead MSOP 8-Lead SOIC
Rail-to-Rail Input and Output Swing (RM Suffix) (R Suffix)
+5 V/+2.7 V Single-Supply Operation
NC 1 8 NC
High Gain, CMRR, PSRR: 130 dB 2IN A V+ NC 1 8 NC
Ultralow Input Bias Current: 20 pA 1IN A AD8551 OUT A
2IN A 2 7 V+
V2 NC
Low Supply Current: 700 ␮A/Op Amp 4 5
+IN A 3
AD8551
6 OUT A
Overload Recovery Time: 50 ␮s NC = NO CONNECT
V2 4 5 NC
No External Capacitors Required
NC = NO CONNECT
APPLICATIONS
Temperature Sensors
Pressure Sensors 8-Lead TSSOP 8-Lead SOIC
Precision Current Sensing (RU Suffix) (R Suffix)
Strain Gage Amplifiers
Medical Instrumentation OUT A 1 8 V+
2IN A OUT B OUT A 1 8 V+
Thermocouple Amplifiers +IN A
AD8552 2IN B
V2 4 5 +IN B 2IN A 2 7 OUT B
AD8552
+IN A 3 6 2IN B
GENERAL DESCRIPTION
V2 4 5 +IN B
This new family of amplifiers has ultralow offset, drift and bias
current. The AD8551, AD8552 and AD8554 are single, dual and
quad amplifiers featuring rail-to-rail input and output swings. All
are guaranteed to operate from +2.7 V to +5 V single supply.
14-Lead TSSOP 14-Lead SOIC
The AD855x family provides the benefits previously found only (R Suffix)
(RU Suffix)
in expensive autozeroing or chopper-stabilized amplifiers. Using
Analog Devices’ new topology these new zero-drift amplifiers OUT A 1 14 OUT D
2IN A 2IN D OUT A 1 OUT D
combine low cost with high accuracy. No external capacitors are 14
1IN A 1IN D
required. V1 AD8554 2IN A 2 13 2IN D
V2
1IN B 1IN C
With an offset voltage of only 1 µV and drift of 0.005 µV/°C,
+IN A 3 12 +IN D
2IN B 2IN C
OUT B 7 8 OUT C V+ 4 AD8554 11 V2
the AD8551 is perfectly suited for applications where error
+IN B 5 10 +IN C
sources cannot be tolerated. Temperature, position and pres-
sure sensors, medical equipment and strain gage amplifiers 2IN B 6 9 2IN C

benefit greatly from nearly zero drift over their operating OUT B 7 8 OUT C
temperature range. The rail-to-rail input and output swings
provided by the AD855x family make both high-side and low-
side sensing easy.
The AD855x family is specified for the extended industrial/
automotive (–40°C to +125°C) temperature range. The AD8551
single is available in 8-lead MSOP and narrow 8-lead SOIC
packages. The AD8552 dual amplifier is available in 8-lead
narrow SO and 8-lead TSSOP surface mount packages. The
AD8554 quad is available in narrow 14-lead SOIC and 14-lead
TSSOP packages.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999

This datasheet has been downloaded from http://www.digchip.com at this page

AD8551/AD8552/AD8554–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V S = +5 V, VCM = +2.5 V, V O = +2.5 V, TA = +25ⴗC unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS␣
Offset Voltage VOS 1 5 µV
–40°C ≤ TA ≤ +125°C 10 µV
Input Bias Current IB 10 50 pA
–40°C ≤ TA ≤ +125°C 1.0 1.5 nA
Input Offset Current IOS 20 70 pA
–40°C ≤ TA ≤ +125°C 150 200 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to +5 V 120 140 dB
–40°C ≤ TA ≤ +125°C 115 130 dB
Large Signal Voltage Gain1 AVO RL = 10 kΩ, VO = +0.3 V to +4.7 V 125 145 dB
–40°C ≤ TA ≤ +125°C 120 135 dB
Offset Voltage Drift ∆VOS /∆T –40°C ≤ TA ≤ +125°C 0.005 0.04 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 4.99 4.998 V
–40°C to +125°C 4.99 4.997 V
RL = 10 kΩ to GND 4.95 4.98 V
–40°C to +125°C 4.95 4.975 V
Output Voltage Low VOL RL = 100 kΩ to V+ 1 10 mV
–40°C to +125°C 2 10 mV
RL = 10 kΩ to V+ 10 30 mV
–40°C to +125°C 15 30 mV
Short Circuit Limit ISC ± 25 ± 50 mA
–40°C to +125°C ± 40 mA
Output Current IO ± 30 mA
–40°C to +125°C ± 15 mA
POWER SUPPLY␣
Power Supply Rejection Ratio PSRR VS = +2.7 V to +5.5 V 120 130 dB
–40°C ≤ TA ≤ +125°C 115 130 dB
Supply Current/Amplifier ISY VO = 0 V 850 975 µA
–40°C ≤ TA ≤ +125°C 1,000 1,075 µA
DYNAMIC PERFORMANCE␣
Slew Rate SR RL = 10 kΩ 0.4 V/µs
Overload Recovery Time 0.05 0.3 ms
Gain Bandwidth Product GBP 1.5 MHz
NOISE PERFORMANCE␣
Voltage Noise en p-p 0 Hz to 10 Hz 1.0 µV p-p
en p-p 0 Hz to 1 Hz 0.32 µV p-p
Voltage Noise Density en f = 1 kHz 42 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz
NOTE
1
Gain testing is highly dependent upon test bandwidth.
Specifications subject to change without notice.

–2– REV. 0
 AD8551/AD8552/AD8554
ELECTRICAL CHARACTERISTICS (V S = +2.7 V, VCM = +1.35 V, VO = +1.35 V, TA = +25ⴗC unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS␣
Offset Voltage VOS 1 5 µV
–40°C ≤ TA ≤ +125°C 10 µV
Input Bias Current IB 10 50 pA
–40°C ≤ TA ≤ +125°C 1.0 1.5 nA
Input Offset Current IOS 10 50 pA
–40°C ≤ TA ≤ +125°C 150 200 pA
Input Voltage Range 0 2.7 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to +2.7 V 115 130 dB
–40°C ≤ TA ≤ +125°C 110 130 dB
Large Signal Voltage Gain1 AVO RL = 10 kΩ, VO = +0.3 V to +2.4 V 110 140 dB
–40°C ≤ TA ≤ +125°C 105 130 dB
Offset Voltage Drift ∆VOS /∆T –40°C ≤ TA ≤ +125°C 0.005 0.04 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 2.685 2.697 V
–40°C to +125°C 2.685 2.696 V
RL = 10 kΩ to GND 2.67 2.68 V
–40°C to +125°C 2.67 2.675 V
Output Voltage Low VOL RL = 100 kΩ to V+ 1 10 mV
–40°C to +125°C 2 10 mV
RL = 10 kΩ to V+ 10 20 mV
–40°C to +125°C 15 20 mV
Short Circuit Limit ISC ± 10 ± 15 mA
–40°C to +125°C ± 10 mA
Output Current IO ± 10 mA
–40°C to +125°C ±5 mA
POWER SUPPLY␣
Power Supply Rejection Ratio PSRR VS = +2.7 V to +5.5 V 120 130 dB
–40°C ≤ TA ≤ +125°C 115 130 dB
Supply Current/Amplifier ISY VO = 0 V 750 900 µA
–40°C ≤ TA ≤ +125°C 950 1,000 µA
DYNAMIC PERFORMANCE␣
Slew Rate SR RL = 10 kΩ 0.5 V/µs
Overload Recovery Time 0.05 ms
Gain Bandwidth Product GBP 1 MHz
NOISE PERFORMANCE␣
Voltage Noise en p-p 0 Hz to 10 Hz 1.6 µV p-p
Voltage Noise Density en f = 1 kHz 75 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz
NOTE
1
Gain testing is highly dependent upon test bandwidth.
Specifications subject to change without notice.

REV. 0 –3–
AD8551/AD8552/AD8554
1
ABSOLUTE MAXIMUM RATINGS Package Type ␪JA1 ␪JC Units
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Input Voltage . . . . . . . . .2. . . . . . . . . . . . . GND to VS + 0.3 V 8-Lead MSOP (RM) 190 44 °C/W
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 5.0 V 8-Lead TSSOP (RU) 240 43 °C/W
ESD(Human Body Model) . . . . . . . . . . . . . . . . . . . . . 2,000 V 8-Lead SOIC (R) 158 43 °C/W
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite 14-Lead TSSOP (RU) 180 36 °C/W
Storage Temperature Range 14-Lead SOIC (R) 120 36 °C/W
RM, RU and R Packages . . . . . . . . . . . . . –65°C to +150°C NOTE
Operating Temperature Range 1
θ JA is specified for worst case conditions, i.e., θ JA is specified for device in socket
AD8551A/AD8552A/AD8554A . . . . . . . . –40°C to +125°C for P-DIP packages, θ JA is specified for device soldered in circuit board for
Junction Temperature Range SOIC and TSSOP packages.
RM, RU and R Packages . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option Brand1
AD8551ARM2 –40°C to +125°C 8-Lead MSOP RM-8 AHA
AD8551AR –40°C to +125°C 8-Lead SOIC SO-8
AD8552ARU3 –40°C to +125°C 8-Lead TSSOP RU-8
AD8552AR –40°C to +125°C 8-Lead SOIC SO-8
AD8554ARU3 –40°C to +125°C 14-Lead TSSOP RU-14
AD8554AR –40°C to +125°C 14-Lead SOIC SO-14
NOTES
1
Due to package size limitations, these characters represent the part number.
2
Available in reels only. 1,000 or 2,500 pieces per reel.
3
Available in reels only. 2,500 pieces per reel.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD8551/AD8552/AD8554 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. 0
 Typical Performance Characteristics– AD8551/AD8552/AD8554
180 50 1,500
VSY = +2.7V
VCM = +1.35V VSY = +5V VSY = +5V
160 40
TA = +258C TA = 2408C, +258C, +858C 1,000 TA = +1258C

INPUT BIAS CURRENT – pA

INPUT BIAS CURRENT – pA

NUMBER OF AMPLIFIERS

140
30
+858C 500
120
20
100 0
10
80 +258C 2500
0
60
21,000
210
40
2408C
220 21,500
20

0 230 22,000
22.5 21.5 20.5 0.5 1.5 2.5 0 1 2 3 4 5 0 1 2 3 4 5
OFFSET VOLTAGE – mV INPUT COMMON-MODE VOLTAGE – V INPUT COMMON-MODE VOLTAGE – V

Figure 1. Input Offset Voltage Figure 2. Input Bias Current vs. Figure 3. Input Bias Current vs.
Distribution at +2.7 V Common-Mode Voltage Common-Mode Voltage

180 12 10k
VSY = +5V
VSY = +5V VSY = +5V
160 VCM = +2.5V
VCM = +2.5V TA = +258C
TA = +258C 10
TA = 2408C TO +1258C 1k
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

140

OUTPUT VOLTAGE – mV
120 8
100
100
6
80 SOURCE
10 SINK
60 4

40 1
2
20

0 0 0.1
22.5 21.5 20.5 0.5 1.5 2.5 0 1 2 3 4 5 6 0.0001 0.001 0.01 0.1 1 10 100
OFFSET VOLTAGE – mV INPUT OFFSET DRIFT – nV/8C LOAD CURRENT – mA

Figure 4. Input Offset Voltage Figure 5. Input Offset Voltage Drift Figure 6. Output Voltage to Supply
Distribution at +5 V Distribution at +5 V Rail vs. Output Current at +5 V

10k 0 1.0
VSY = +2.7V VCM = +2.5V
TA = +258C +5V
VSY = +5V
INPUT BIAS CURRENT – pA

1k 0.8
2250
OUTPUT VOLTAGE – mV

SUPPLY CURRENT – mA

+2.7V

100 0.6
2500
SOURCE SINK
10 0.4

2750
1 0.2

0.1 21000 0
0.0001 0.001 0.01 0.1 1 10 100 275 250 225 0 25 50 75 100 125 150 275 250 225 0 25 50 75 100 125 150
LOAD CURRENT – mA TEMPERATURE – 8C TEMPERATURE – 8C

Figure 7. Output Voltage to Supply Figure 8. Bias Current vs. Temperature Figure 9. Supply Current vs.
Rail vs. Output Current at +2.7 V Temperature

REV. 0 –5–
AD8551/AD8552/AD8554
800 60 60
SUPPLY CURRENT PER AMPLIFIER – mA

TA = +258C VSY = +2.7V VSY = +5V

50 CL = 0pF 50 CL = 0pF
700
RL = RL =
40 0 40 0

PHASE SHIFT – Degrees

PHASE SHIFT – Degrees

OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
600
30 45 30 45
500 20 90
20 90

400 10 135 10 135

0 180 0 180
300
210 225 210 225
200
220 270 220 270
100 230 230

0 240 240
0 1 2 3 4 5 6 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
SUPPLY VOLTAGE – V FREQUENCY – Hz FREQUENCY – Hz

Figure 10. Supply Current vs. Figure 11. Open-Loop Gain and Figure 12. Open-Loop Gain and
Supply Voltage Phase Shift vs. Frequency at +2.7 V Phase Shift vs. Frequency at +5 V

60 60 300
VSY = +2.7V VSY = +5V VSY = +2.7V
50 50 270
CL = 0pF CL = 0pF
40 RL = 2kV 40 RL = 2kV 240
CLOSED-LOOP GAIN – dB

OUTPUT IMPEDANCE – V
CLOSED-LOOP GAIN – dB

AV = 2100 AV = 2100
30 30 210

20 20 180
AV = 210 AV = 210
10 10 150

0 0 120 AV = 100
AV = +1 AV = +1
210 210 90
AV = 10
220 220 60

230 230 30 AV = 1
240 240 0
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

Figure 13. Closed Loop Gain vs. Figure 14. Closed Loop Gain vs. Figure 15. Output Impedance vs.
Frequency at +2.7 V Frequency at +5 V Frequency at +2.7 V

300

270 VSY = +5V VSY = +2.7V VSY = +5V

CL = 300pF CL = 300pF
240 RL = 2kV RL = 2kV
OUTPUT IMPEDANCE – V

AV = +1 AV = +1
210

180

150

120 AV = 100
90

60 AV = 10
2ms 500mV 5ms 1V
30 AV = 1
0
100 1k 10k 100k 1M 10M
FREQUENCY – Hz

Figure 16. Output Impedance vs. Figure 17. Large Signal Transient Figure 18. Large Signal Transient
Frequency at +5 V Response at +2.7 V Response at +5 V

–6– REV. 0
 AD8551/AD8552/AD8554
50
VSY = 61.35V VSY = 62.5V
45 VSY = 61.35V
CL = 50pF CL = 50pF

SMALL SIGNAL OVERSHOOT – %

RL = RL = 2kV
RL = 40 TA = +258C
AV = +1 AV = +1
35

30
+OS
25
2OS
20

15

5ms 50mV 10
5ms 50mV
5

0
10 100 1k 10k
CAPACITANCE – pF

Figure 19. Small Signal Transient Figure 20. Small Signal Transient Figure 21. Small Signal Overshoot
Response at +2.7 V Response at +5 V vs. Load Capacitance at +2.7 V

45

40 VSY = 62.5V VIN

0V
SMALL SIGNAL OVERSHOOT – %

RL = 2kV
35 TA = +258C VIN 0V
VSY = 62.5V VSY = 62.5V
30 VIN = 2200mV p-p VIN = +200mV p-p
(RET TO GND) (RET TO GND)
25 CL = 0pF 0V CL = 0pF
+OS 2OS VOUT RL = 10kV RL = 10kV
20 AV = 2100 AV = 2100

15
VOUT
10 0V
20ms 1V 20ms 1V
5
BOTTOM SCALE: 1V/DIV BOTTOM SCALE: 1V/DIV
0 TOP SCALE: 200mV/DIV TOP SCALE: 200mV/DIV
10 100 1k 10k
CAPACITANCE – pF

Figure 22. Small Signal Overshoot Figure 23. Positive Overvoltage Figure 24. Negative Overvoltage
vs. Load Capacitance at +5 V Recovery Recovery

140 140
VSY = +2.7V VSY = +5V
VS = 62.5V
120 120
RL = 2kV
AV = 2100
VIN = 60mV p-p 100 100
CMRR – dB
CMRR – dB

80 80

60 60

40 40

200ms 1V 20
20

0 0
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz

Figure 25. No Phase Reversal Figure 26. CMRR vs. Frequency Figure 27. CMRR vs. Frequency
at +2.7 V at +5 V

REV. 0 –7–
AD8551/AD8552/AD8554
140 140 3.0
VSY = 61.35V VSY = 62.5V
120 120
2.5
VSY = 61.35V

OUTPUT SWING – V p-p

100 100 RL = 2kV
2.0 AV = +1

PSRR – dB
PSRR – dB

THD+N < 1%
80 80 TA = +258C
+PSRR 1.5
60 60
+PSRR 2PSRR
2PSRR 1.0
40 40

20 0.5
20

0 0 0
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

Figure 28. PSRR vs. Frequency Figure 29. PSRR vs. Frequency Figure 30. Maximum Output Swing
at ± 1.35 V at ± 2.5 V vs. Frequency at +2.7 V

5.5
VSY = 62.5V VSY = 61.35V VSY = 62.5V
5.0 AV = 10,000
RL = 2kV AV = 10,000
4.5 AV = +1
OUTPUT SWING – V p-p

THD+N < 1%
4.0
TA = +258C
3.5
3.0 0V

2.5
2.0
1.5
1.0 1s 2mV 1s 2mV

0.5
0
100 1k 10k 100k 1M
FREQUENCY – Hz

Figure 31. Maximum Output Swing Figure 32. 0.1 Hz to 10 Hz Noise Figure 33. 0.1 Hz to 10 Hz Noise at +5 V
vs. Frequency at +5 V at +2.7 V

VSY = +2.7V VSY = +5V

VSY = +2.7V 112 91
182 RS = 0V RS = 0V
RS = 0V
156 96 78
en – nV/ Hz

en – nV/ Hz

80 65
en – nV/ Hz

130

104 64 52

78 48 39

52 32 26

26 16 13

0 5 10 15 20 25 0 0.5 1.0 1.5 2.0 2.5

0 0.5 1.0 1.5 2.0 2.5
FREQUENCY – kHz FREQUENCY – kHz
FREQUENCY – kHz

Figure 34. Voltage Noise Density at Figure 35. Voltage Noise Density at Figure 36. Voltage Noise Density at
+2.7 V from 0 Hz to 2.5 kHz +2.7 V from 0 Hz to 25 kHz +5 V from 0 Hz to 2.5 kHz

–8– REV. 0
 AD8551/AD8552/AD8554
150
VSY = ±5V VSY = +5V VSY = +2.7V TO +5.5V
112 168

POWER SUPPLY REJECTION – dB

RS = 0V RS = 0V
145
96 144
en – nV/ Hz

en – nV/ Hz
80 120
140
64 96

48 72
135
32 48

16 24 130

0 5 10 15 20 25 0 5 10
FREQUENCY – kHz FREQUENCY – Hz 125
275 250 225 0 25 50 75 100 125 150
TEMPERATURE – 8C

Figure 37. Voltage Noise Density Figure 38. Voltage Noise Density Figure 39. Power-Supply Rejection
at +5 V from 0 Hz to 25 kHz at +5 V from 0 Hz to 10 Hz vs. Temperature

50 100 250
40 VSY = +2.7V 80 VSY = +5.0V 225 VSY = +5.0V
SHORT-CIRCUIT CURRENT – mA
SHORT-CIRCUIT CURRENT – mA

OUTPUT VOLTAGE SWING – mV

30 60 200
ISC2 ISC2
20 40 175
10 20 150
RL = 1kV
0 0 125

210 220 100

ISC+
220 ISC+ 240 75

230 260 50
RL = 100kV
240 280 25 RL = 10kV
250 2100 0
275 250 225 0 25 50 75 100 125 150 275 250 225 0 25 50 75 100 125 150 275 250 225 0 25 50 75 100 125 150
TEMPERATURE – 8C TEMPERATURE – 8C TEMPERATURE – 8C

Figure 40. Output Short-Circuit Figure 41. Output Short-Circuit Figure 42. Output Voltage to
Current vs. Temperature Current vs. Temperature Supply Rail vs. Temperature

250

225 VSY = +5.0V

OUTPUT VOLTAGE SWING – mV

200

175
RL = 1kV
150
125

100

75

50
RL = 100kV
25 RL = 10kV
0
275 250 225 0 25 50 75 100 125 150
TEMPERATURE – 8C

Figure 43. Output Voltage to Supply

Rail vs. Temperature

REV. 0 –9–
AD8551/AD8552/AD8554
FUNCTIONAL DESCRIPTION As noted in the previous section on amplifier architecture, each
The AD855x family of amplifiers are high precision rail-to-rail AD855x op amp contains two internal amplifiers. One is used as
operational amplifiers that can be run from a single supply volt- the primary amplifier, the other as an autocorrection, or nulling,
age. Their typical offset voltage of less than 1 µV allows these amplifier. Each amplifier has an associated input offset voltage,
amplifiers to be easily configured for high gains without risk of which can be modeled as a dc voltage source in series with the
excessive output voltage errors. The extremely small tempera- noninverting input. In Figures 44 and 45 these are labeled as
ture drift of 5 nV/°C ensures a minimum of offset voltage error VOSX, where x denotes the amplifier associated with the offset; A
over its entire temperature range of –40°C to +125°C, making for the nulling amplifier, B for the primary amplifier. The open-
the AD855x amplifiers ideal for a variety of sensitive measure- loop gain for the +IN and –IN inputs of each amplifier is given
ment applications in harsh operating environments such as as AX . Both amplifiers also have a third voltage input with an
under-hood and braking/suspension systems in automobiles. associated open-loop gain of BX .
The AD855x family are CMOS amplifiers and achieve their There are two modes of operation determined by the action of
high degree of precision through autozero stabilization. This two sets of switches in the amplifier: An autozero phase and an
autocorrection topology allows the AD855x to maintain its low amplification phase.
offset voltage over a wide temperature range and over its operat- Autozero Phase
ing lifetime. In this phase, all φA switches are closed and all φB switches are
Amplifier Architecture opened. Here, the nulling amplifier is taken out of the gain loop
Each AD855x op amp consists of two amplifiers, a main amplifier by shorting its two inputs together. Of course, there is a degree of
and a secondary amplifier, used to correct the offset voltage of the offset voltage, shown as VOSA, inherent in the nulling amplifier
main amplifier. Both consist of a rail-to-rail input stage, allowing which maintains a potential difference between the +IN and –IN
the input common-mode voltage range to reach both supply rails. inputs. The nulling amplifier feedback loop is closed through φA2
The input stage consists of an NMOS differential pair operating and VOSA appears at the output of the nulling amp and on CM1,
concurrently with a parallel PMOS differential pair. The outputs an internal capacitor in the AD855x. Mathematically, we can ex-
from the differential input stages are combined in another gain press this in the time domain as:

[] [] []
stage whose output is used to drive a rail-to-rail output stage.
VOA t = AAVOSA t − BAVOA t (1)
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output which can be expressed as,
voltage range is limited by the drain to source resistance of these
transistors. As the amplifier is required to source or sink more []
VOA t =
[]
AAVOSA t
(2)
output current, the rDS of these transistors increases, raising the 1 + BA
voltage drop across these transistors. Simply put, the output volt- This shows us that the offset voltage of the nulling amplifier
age will not swing as close to the rail under heavy output current times a gain factor appears at the output of the nulling amplifier
conditions as it will with light output current. This is a character- and thus on the CM1 capacitor.
istic of all rail-to-rail output amplifiers. Figures 6 and 7 show how
close the output voltage can get to the rails with a given output VIN+
current. The output of the AD855x is short circuit protected to AB VOUT
VIN2
approximately 50 mA of current. BB
FB
The AD855x amplifiers have exceptional gain, yielding greater VOSA
VOA
FB CM2
than 120 dB of open-loop gain with a load of 2 kΩ. Because the FA +
output transistors are configured in a common-source configu- AA VNB
ration, the gain of the output stage, and thus the open-loop gain
of the amplifier, is dependent on the load resistance. Open-loop 2BA FA CM1
gain will decrease with smaller load resistances. This is another
characteristic of rail-to-rail output amplifiers. VNA

Basic Autozero Amplifier Theory Figure 44. Autozero Phase of the AD855x
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for over 15 years and some Amplification Phase
improvements have been made over time. The AD855x design When the φB switches close and the φA switches open for the
offers a number of significant performance improvements over amplification phase, this offset voltage remains on CM1 and
older versions while attaining a very substantial reduction in de- essentially corrects any error from the nulling amplifier. The
vice cost. This section offers a simplified explanation of how the voltage across CM1 is designated as VNA. Let us also designate
AD855x is able to offer extremely low offset voltages and high VIN as the potential difference between the two inputs to the
open-loop gains. primary amplifier, or VIN = (VIN+ – VIN–). Now the output of the
nulling amplifier can be expressed as:

[] ( [] [ ])
VOA t = AA VIN t − VOSA t − BAVNA t [] (3)

–10– REV. 0
 AD8551/AD8552/AD8554
VIN+ Combining terms,
AB VOUT

[] []
VOUT t = VIN t ( AB + AABB ) +
VIN2
AABBVOSA
BB
+ ABVOSB (10)
FB
FB CM2 1 + BA
FA VOSA VOA
+
The AD855x architecture is optimized in such a way that
AA VNB
AA␣ =␣ A B and BA␣ =␣ B B and B A␣ >>␣ 1. Also, the gain product of
2BA
AABB is much greater than AB . These allow Equation 10 to be
FA CM1 simplified to:
VNA [] []
VOUT t ≈ VIN t AABA + AA (VOSA + VOSB ) (11)

Figure 45. Output Phase of the Amplifier Most obvious is the gain product of both the primary and nulling
Because φA is now open and there is no place for CM1 to dis- amplifiers. This AABA term is what gives the AD855x its extremely
charge, the voltage VNA at the present time t is equal to the high open-loop gain. To understand how VOSA and VOSB relate to
voltage at the output of the nulling amp VOA at the time when the overall effective input offset voltage of the complete amplifier,
φA was closed. If we call the period of the autocorrection we should set up the generic amplifier equation of:
switching frequency TS, then the amplifier switches between
phases every 0.5␣ ⫻␣ TS. Therefore, in the amplification phase:
(
VOUT = k × VIN + VOS , EFF ) (12)

Where k is the open-loop gain of an amplifier and VOS, EFF is its

effective offset voltage. Putting Equation 12 into the form of
 1 
[]
VNA t = VNA t − TS  (4)
Equation 11 gives us:
 2 
[] []
VOUT t ≈ VIN t AABA + VOS , EFF AA BA (13)
And substituting Equation 4 and Equation 2 into Equation 3 yields:
And from here, it is easy to see that:
VOSA + VOSB
 1  VOS , EFF ≈ (14)
AABAVOSA t − TS  BA
[]
VOA t = AAVIN t + AAVOSA [] [] t −  2 
1 + BA
(5) Thus, the offset voltages of both the primary and nulling ampli-
fiers are reduced by the gain factor BA. This takes a typical input
For the sake of simplification, let us assume that the autocorrection offset voltage from several millivolts down to an effective input
frequency is much faster than any potential change in VOSA or offset voltage of submicrovolts. This autocorrection scheme is
VOSB. This is a good assumption since changes in offset voltage are what makes the AD855x family of amplifiers among the most
a function of temperature variation or long-term wear time, both of precise amplifiers in the world.
which are much slower than the auto-zero clock frequency of the High Gain, CMRR, PSRR
AD855x. This effectively makes VOS time invariant and we can re- Common-mode and power supply rejection are indications of
arrange Equation 5 and rewrite it as: the amount of offset voltage an amplifier has as a result of a
AA (1 + BA ) VOSA − AABAVOSA change in its input common-mode or power supply voltages. As
[]
VOA t = AAVIN t + [] 1 + BA
(6) shown in the previous section, the autocorrection architecture of
the AD855x allows it to quite effectively minimize offset volt-
or, ages. The technique also corrects for offset errors caused by
common-mode voltage swings and power supply variations.
 
[] V
VOA t = AA VIN t + OSA 

[]
1 + BA 
(7)
This results in superb CMRR and PSRR figures in excess of
130 dB. Because the autocorrection occurs continuously, these
figures can be maintained across the device’s entire temperature
We can already get a feel for the autozeroing in action. Note the range, from –40°C to +125°C.
VOS term is reduced by a 1 + B A factor. This shows how the
Maximizing Performance Through Proper Layout
nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Now the primary To achieve the maximum performance of the extremely high
amplifier output voltage is the voltage at the output of the input impedance and low offset voltage of the AD855x, care
AD855x amplifier. It is equal to: should be taken in the circuit board layout. The PC board sur-
face must remain clean and free of moisture to avoid leakage
[] ( []
VOUT t = AB VIN t + VOSB + BBVNB ) (8) currents between adjacent traces. Surface coating of the circuit
board will reduce surface moisture and provide a humidity
In the amplification phase, VOA = VNB, so this can be rewritten as: barrier, reducing parasitic resistance on the board. The use of
guard rings around the amplifier inputs will further reduce leak-
  
[] [] V
VOUT t = ABVIN t + ABVOSB + BB  AA VIN t + OSA   (9)
 +
[] age currents. Figure 46 shows how the guard ring should be
 1 B A 
 configured and Figure 47 shows the top view of how a surface
mount layout can be arranged. The guard ring does not need to

REV. 0 –11–
AD8551/AD8552/AD8554
be a specific width, but it should form a continuous loop around COMPONENT
LEAD
both inputs. By setting the guard ring voltage equal to the volt-
age at the noninverting input, parasitic capacitance is minimized VSC1
+ SURFACE MOUNT +
VSC2
SOLDER
as well. For further reduction of leakage currents, components 2 COMPONENT 2
VTS1 VTS2
+ +
can be mounted to the PC board using Teflon standoff insulators. 2 2

PC BOARD

TA1 TA2
COPPER IF TA1 fi TA2, THEN
VOUT TRACE
VOUT VTS1 + VSC1 fi VTS2 + VSC2
VIN VIN
AD8552 AD8552
Figure 48. Mismatch in Seebeck Voltages Causes a
Thermoelectric Voltage Error

RF
VIN
VOUT
R1
AD8552
VOUT
VIN
RS = R1 AD855x
Figure 46. Guard Ring Layout and Connections to Reduce AV = 1 + (RF /R1)
PC Board Leakage Currents NOTE: RS SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES
V+
R1 R2 Figure 49. Using Dummy Components to Cancel
AD8552
VIN1
R2 R1 Thermoelectric Voltage Errors
VIN2 1/f Noise Characteristics
Another advantage of autozero amplifiers is their ability to cancel
GUARD GUARD flicker noise. Flicker noise, also known as 1/f noise, is noise inher-
RING VREF
RING
VREF ent in the physics of semiconductor devices and increases 3 dB
V2 for every octave decrease in frequency. The 1/f corner frequency
of an amplifier is the frequency at which the flicker noise is equal
Figure 47. Top View of AD8552 SOIC Layout with to the broadband noise of the amplifier. At lower frequencies,
Guard Rings flicker noise dominates, causing higher degrees of error for sub-
Other potential sources of offset error are thermoelectric voltages Hertz frequencies or dc precision applications.
on the circuit board. This voltage, also called Seebeck voltage, Because the AD855x amplifiers are self-correcting op amps,
occurs at the junction of two dissimilar metals and is proportional they do not have increasing flicker noise at lower frequencies.
to the temperature of the junction. The most common metallic In essence, low frequency noise is treated as a slowly varying
junctions on a circuit board are solder-to-board trace and solder- offset error and is greatly reduced as a result of autocorrection.
to-component lead. Figure 48 shows a cross-section diagram view The correction becomes more effective as the noise frequency
of the thermal voltage error sources. If the temperature of the PC approaches dc, offsetting the tendency of the noise to increase
board at one end of the component (TA1) is different from the exponentially as frequency decreases. This allows the AD855x
temperature at the other end (TA2), the Seebeck voltages will not to have lower noise near dc than standard low-noise amplifiers
be equal, resulting in a thermal voltage error. that are susceptible to 1/f noise.
This thermocouple error can be reduced by using dummy com- Intermodulation Distortion
ponents to match the thermoelectric error source. Placing the The AD855x can be used as a conventional op amp for gain/
dummy component as close as possible to its partner will ensure bandwidth combinations up to 1.5 MHz. The autozero correc-
both Seebeck voltages are equal, thus canceling the thermo- tion frequency of the device is fixed at 4 kHz. Although a trace
couple error. Maintaining a constant ambient temperature on amount of this frequency will feed through to the output, the
the circuit board will further reduce this error. The use of a amplifier can be used at much higher frequencies. Figure 50
ground plane will help distribute heat throughout the board and shows the spectral output of the AD8552 with the amplifier
will also reduce EMI noise pickup. configured for unity gain and the input grounded.
The 4 kHz autozero clock frequency appears at the output with
less than 2 µV of amplitude. Harmonics are also present, but at
reduced levels from the fundamental autozero clock frequency.
The amplitude of the clock frequency feedthrough is proportional
to the closed-loop gain of the amplifier. Like other autocorrection
amplifiers, at higher gains there will be more clock frequency
feedthrough. Figure 51 shows the spectral output with the ampli-
fier configured for a gain of 60 dB.

–12– REV. 0
 AD8551/AD8552/AD8554
0 0
OUTPUT SIGNAL VSY = +5V
VSY = +5V 1Vrms @ 200Hz AV = +60dB
220
AV = 0dB 220

240
240
OUTPUT SIGNAL

OUTPUT SIGNAL
260
260
280

280 IMD < 100mVrms

2100

2100
2120

2140 2120
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
FREQUENCY – kHz FREQUENCY – kHz

Figure 50. Spectral Analysis of AD855x Output in Unity Figure 52. Spectral Analysis of AD855x in High Gain with
Gain Configuration a 1 mV Input Signal
For most low frequency applications, the small amount of auto-
0
zero clock frequency feedthrough will not affect the precision of the
VSY = +5V measurement system. Should it be desired, the clock frequency
220
AV = +60dB feedthrough can be reduced through the use of a feedback capaci-
240
tor around the amplifier. However, this will reduce the bandwidth
of the amplifier. Figures 53a and 53b show a configuration for
OUTPUT SIGNAL

260 reducing the clock feedthrough and the corresponding spectral

analysis at the output. The –3 dB bandwidth of this configuration
280 is 480 Hz.
3.3nF
2100
100kV
2120
100V

2140
0 1 2 3 4 5 6 7 8 9 10 VIN = 1mV rms
FREQUENCY – kHz @ 200Hz

Figure 51. Spectral Analysis of AD855x Output with

+60 dB Gain Figure 53a. Reducing Autocorrection Clock Noise with a
When an input signal is applied, the output will contain some Feedback Capacitor
degree of Intermodulation Distortion (IMD). This is another
0
characteristic feature of all autocorrection amplifiers. IMD will VSY = +5V
show up as sum and difference frequencies between the input sig- AV = +60dB
nal and the 4 kHz clock frequency (and its harmonics) and is at a 220

level similar to or less than the clock feedthrough at the output.

The IMD is also proportional to the closed loop gain of the ampli- 240
OUTPUT SIGNAL

fier. Figure 52 shows the spectral output of an AD8552 configured

as a high gain stage (+60 dB) with a 1 mV input signal applied. 260
The relative levels of all IMD products and harmonic distortion
add up to produce an output error of –60 dB relative to the input 280
signal. At unity gain, these would add up to only –120 dB relative
to the input signal.
2100

2120
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY – kHz

Figure 53b. Spectral Analysis Using a Feedback Capacitor

REV. 0 –13–
AD8551/AD8552/AD8554
Broadband and External Resistor Noise Considerations Input Overvoltage Protection
The total broadband noise output from any amplifier is primarily Although the AD855x is a rail-to-rail input amplifier, care should
a function of three types of noise: Input voltage noise from the be taken to ensure that the potential difference between the in-
amplifier, input current noise from the amplifier and Johnson puts does not exceed +5 V. Under normal operating conditions,
noise from the external resistors used around the amplifier. Input the amplifier will correct its output to ensure the two inputs are at
voltage noise, or en, is strictly a function of the amplifier used. the same voltage. However, if the device is configured as a com-
The Johnson noise from a resistor is a function of the resistance parator, or is under some unusual operating condition, the input
and the temperature. Input current noise, or in, creates an equiva- voltages may be forced to different potentials. This could cause
lent voltage noise proportional to the resistors used around the excessive current to flow through internal diodes in the AD855x
amplifier. These noise sources are not correlated with each other used to protect the input stage against overvoltage.
and their combined noise sums in a root-squared-sum fashion. If either input exceeds either supply rail by more than 0.3 V, large
The full equation is given as: amounts of current will begin to flow through the ESD protection
1 diodes in the amplifier. These diodes are connected between the
e n, TOTAL = e n + 4kTrS + (inrS ) 
2 2 2
(15) inputs and each supply rail to protect the input transistors against
  an electrostatic discharge event and are normally reverse-biased.
Where, en = The input voltage noise of the amplifier, However, if the input voltage exceeds the supply voltage, these
in = The input current noise of the amplifier, ESD diodes will become forward-biased. Without current limit-
rS = Source resistance connected to the noninverting ing, excessive amounts of current could flow through these diodes
terminal, causing permanent damage to the device. If inputs are subject to
k = Boltzmann’s constant (1.38 ⫻ 10-23 J/K) overvoltage, appropriate series resistors should be inserted to
T = Ambient temperature in Kelvin (K = 273.15 + °C) limit the diode current to less than 2 mA maximum.
The input voltage noise density, en of the AD855x is 42 nV/√Hz, Output Phase Reversal
and the input noise, in, is 2 fA/√Hz. The en, TOTAL will be domi- Output phase reversal occurs in some amplifiers when the input
nated by input voltage noise provided the source resistance is less common-mode voltage range is exceeded. As common-mode volt-
than 106 kΩ. With source resistance greater than 106 kΩ, the age is moved outside of the common-mode range, the outputs of
overall noise of the system will be dominated by the Johnson these amplifiers will suddenly jump in the opposite direction to the
noise of the resistor itself. supply rail. This is the result of the differential input pair shutting
down, causing a radical shifting of internal voltages which results in
Because the input current noise of the AD855x is very small, in
the erratic output behavior.
does not become a dominant term unless rS is greater than 4 GΩ,
which is an impractical value of source resistance. The AD855x amplifier has been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
The total noise, en, TOTAL, is expressed in volts per square-root
within the supply voltages. If one or both inputs could exceed
Hertz, and the equivalent rms noise over a certain bandwidth
either supply voltage, a resistor should be placed in series with
can be found as:
the input to limit the current to less than 2 mA. This will ensure
e n = e n, TOTAL × BW (16) the output will not reverse its phase.
Capacitive Load Drive
Where BW is the bandwidth of interest in Hertz.
The AD855x has excellent capacitive load driving capabilities
For a complete treatise on circuit noise analysis, please refer to the and can safely drive up to 10 nF from a single +5 V supply.
1995 Linear Design Seminar book available from Analog Devices. Although the device is stable, capacitive loading will limit the
Output Overdrive Recovery bandwidth of the amplifier. Capacitive loads will also increase
The AD855x amplifiers have an excellent overdrive recovery of the amount of overshoot and ringing at the output. An R-C
only 200 µs from either supply rail. This characteristic is particu- snubber network, Figure 54, can be used to compensate the
larly difficult for autocorrection amplifiers, as the nulling amplifier amplifier against capacitive load ringing and overshoot.
requires a nontrivial amount of time to error correct the main am-
plifier back to a valid output. Figure 23 and Figure 24 show the +5V

positive and negative overdrive recovery time for the AD855x.

The output overdrive recovery for an autocorrection amplifier is AD855x VOUT
VIN RX
defined as the time it takes for the output to correct to its final 200mV p-p 60V
CL
voltage from an overload state. It is measured by placing the CX 4.7nF
amplifier in a high gain configuration with an input signal that 0.47mF

forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
Figure 54. Snubber Network Configuration for Driving
to half-way between the supplies. The time from the input signal
Capacitive Loads
step-down to the output settling to within 100 µV of its final
value is the overdrive recovery time. Most competitors’ auto- Although the snubber will not recover the loss of amplifier band-
correction amplifiers require a number of autozero clock cycles width from the load capacitance, it will allow the amplifier to drive
to recover from output overdrive and some can take several larger values of capacitance while maintaining a minimum of
milliseconds for the output to settle properly. overshoot and ringing. Figure 55 shows the output of an AD855x
driving a 1 nF capacitor with and without a snubber network.

–14– REV. 0
 AD8551/AD8552/AD8554
10ms VSY = 0V TO +5V
100kV

WITH
SNUBBER
VOUT
100kV
AD855x

Figure 56b. AD855x Test Circuit for Turn-On Time

WITHOUT
SNUBBER
APPLICATIONS
VSY = +5V A +5 V Precision Strain-Gage Circuit
CLOAD = 4.7nF 100mV
The extremely low offset voltage of the AD8552 makes it an
ideal amplifier for any application requiring accuracy with high
Figure 55. Overshoot and Ringing are Substantially gains, such as a weigh scale or strain-gage. Figure 57 shows a
Reduced Using a Snubber Network configuration for a single supply, precision strain-gage measure-
The optimum value for the resistor and capacitor is a function of ment system.
the load capacitance and is best determined empirically since A REF192 provides a +2.5 V precision reference voltage for A2.
actual CLOAD will include stray capacitances and may differ sub- The A2 amplifier boosts this voltage to provide a +4.0 V reference
stantially from the nominal capacitive load. Table I shows some for the top of the strain-gage resistor bridge. Q1 provides the cur-
snubber network values that can be used as starting points. rent drive for the 350 Ω bridge network. A1 is used to amplify the
output of the bridge with the full-scale output voltage equal to:
Table I. Snubber Network Values for Driving Capacitive Loads
2 × (R1 + R2 )
CLOAD RX CX (17)
RB
1 nF 200 Ω 1 nF
Where RB is the resistance of the load cell. Using the values given
4.7 nF 60 Ω 0.47 µF
in Figure 57, the output voltage will linearly vary from 0 V with
10 nF 20 Ω 10 µF
no strain to +4.0 V under full strain.
Power-Up Behavior
On power-up, the AD855x will settle to a valid output within 5 µs. +5V 2

Figure 56a shows an oscilloscope photo of the output of the ampli- Q1

1kV
+2.5V
REF192
3
2N2222 6
fier along with the power supply voltage, and Figure 56b shows OR
A2
AD8552-B 4
the test circuit. With the amplifier configured for unity gain, the EQUIVALENT
device takes approximately 5 µs to settle to its final output voltage. +4.0V
12.0kV 20kV

This turn-on response time is much faster than most other auto- R1 R2
correction amplifiers, which can take hundreds of microseconds or 17.4kV 100V
longer for their output to settle.
40mV A1 VOUT
350V FULL-SCALE
0V TO +4.0V
LOAD AD8552-A
CELL R3 R4
VOUT 17.4kV 100V

NOTE: USE 0.1% TOLERANCE RESISTORS.

0V
Figure 57. A +5 V Precision Strain-Gage Amplifier
+3 V Instrumentation Amplifier
V+ The high common-mode rejection, high open-loop gain, and
0V operation down to +3 V of supply voltage makes the AD855x
5ms 1V
an excellent choice of op amp for discrete single supply instru-
mentation amplifiers. The common-mode rejection ratio of
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV the AD855x is greater than 120 dB, but the CMRR of the sys-
tem is also a function of the external resistor tolerances. The
Figure 56a. AD855x Output Behavior on Power-Up gain of the difference amplifier shown in Figure 58 is given as:
 R4   R1   R2 
VOUT = V 1  1 +  − V 2  (18)
 R3 + R4   R2   R1 

REV. 0 –15–
AD8551/AD8552/AD8554
R2 A High Accuracy Thermocouple Amplifier
Figure 60 shows a K-type thermocouple amplifier configuration
R1 with cold-junction compensation. Even from a +5 V supply, the
V2
VOUT AD8551 can provide enough accuracy to achieve a resolution
V1
R3 AD855x of better than 0.02°C from 0°C to 500°C. D1 is used as a
R4
temperature measuring device to correct the cold-junction error
R4 R R from the thermocouple and should be placed as close as possible
IF = 2 , THEN VOUT = 2 3 (V1 2 V2)
R3 R1 R1 to the two terminating junctions. With the thermocouple mea-
suring tip immersed in a zero-degree ice bath, R6 should be
Figure 58. Using the AD855x as a Difference Amplifier
adjusted until the output is at 0 V.
In an ideal difference amplifier, the ratio of the resistors are set
Using the values shown in Figure 60, the output voltage will
exactly equal to:
track temperature at 10 mV/°C. For a wider range of tempera-
R2 R4 ture measurement, R9 can be decreased to 62 kΩ. This will
AV = = (19) create a 5 mV/°C change at the output, allowing measurements
R1 R3
of up to 1000°C.
Which sets the output voltage of the system to:
VOUT = AV (V 1 − V 2) (20) +5.000V
+12V 2 REF02EZ 6
R9
0.1mF
Due to finite component tolerance the ratio between the four 4
R1 R5 124kV
resistors will not be exactly equal, and any mismatch results in a 10.7kV 40.2kV
+5V
1N4148 10mF
reduction of common-mode rejection from the system. Referring +
to Figure 58, the exact common-mode rejection ratio can be ex- D1
0.1mF
pressed as: R2 R8
– – 2.74kV 453V 8
R R + 2R2R4 + R2R3 K-TYPE
2 1
CMRR = 1 4 (21)
THERMOCOUPLE + +
2R1R4 − 2R2R3 40.7mV/8C R6
AD8551
200V 3 4
R4 R3
In the 3 op amp instrumentation amplifier configuration shown 5.62kV 53.6V
0V TO 5.00V
(08C TO 5008C)
in Figure 59, the output difference amplifier is set to unity gain
with all four resistors equal in value. If the tolerance of the resis-
tors used in the circuit is given as δ, the worst-case CMRR of Figure 60. A Precision K-Type Thermocouple Amplifier
the instrumentation amplifier will be: with Cold-Junction Compensation

1 Precision Current Meter

CMRRMIN = (22) Because of its low input bias current and superb offset voltage at
2δ single supply voltages, the AD855x is an excellent amplifier for
precision current monitoring. Its rail-to-rail input allows the
AD8554-A
V2 R amplifier to be used as either a high-side or low-side current
monitor. Using both amplifiers in the AD8552 provides a simple
R R method to monitor both current supply and return paths for
RG VOUT load or fault detection.
R R AD8554-C Figure 61 shows a high-side current monitor configuration. Here,
R
the input common-mode voltage of the amplifier will be at or near
V1 RTRIM the positive supply voltage. The amplifier’s rail-to-rail input provides
AD8554-B a precise measurement even with the input common-mode voltage at
VOUT = 1 +
2R
(V1 2 V2) the supply voltage. The CMOS input structure does not draw any
RG
input bias current, ensuring a minimum of measurement error.
Figure 59. A Discrete Instrumentation Amplifier The 0.1 Ω resistor creates a voltage drop to the noninverting
Configuration input of the AD855x. The amplifier’s output is corrected until
Thus, using 1% tolerance resistors would result in a worst-case this voltage appears at the inverting input. This creates a current
system CMRR of 0.02, or 34 dB. Therefore either high precision through R1, which in turn flows through R2. The Monitor Output
resistors or an additional trimming resistor, as shown in Figure is given by:
59, should be used to achieve high common-mode rejection. The R 
value of this trimming resistor should be equal to the value of R Monitor Output = R2 ×  SENSE  × I L (23)
multiplied by its tolerance. For example, using 10 kΩ resistors  R1 
with 1% tolerance would require a series trimming resistor equal to Using the components shown in Figure 61, the Monitor Output
100 Ω. transfer function is 2.5␣ V/A.

–16– REV. 0
 AD8551/AD8552/AD8554
Figure 62 shows the low-side monitor equivalent. In this circuit, SPICE Model
the input common-mode voltage to the AD8552 will be at or near The SPICE macro-model for the AD855x amplifier is given in
ground. Again, a 0.1 Ω resistor provides a voltage drop propor- Listing 1. This model simulates the typical specifications for the
tional to the return current. The output voltage is given as: AD855x, and it can be downloaded from the Analog Devices
website at http://www.analog.com. The schematic of the
R 
VOUT = V + − 2 × RSENSE × I L  (24)
macro-model is shown in Figure 63.
 R1  Transistors M1 through M4 simulate the rail-to-rail input differ-
For the component values shown in Figure 62, the output trans- ential pairs in the AD855x amplifier. The EOS voltage source in
fer function decreases from V+ at –2.5 V/A. series with the noninverting input establishes not only the 1 µV
offset voltage, but is also used to establish common-mode and
RSENSE IL power supply rejection ratios and input voltage noise. The dif-
+3V
0.1V
V+
ferential voltages from nodes 14 to 16 and nodes 17 to 18 are
+3V
reflected to E1, which is used to simulate a secondary pole-zero
0.1mF combination in the open-loop gain of the amplifier.
R1
3 8
100V The voltage at node 32 is then reflected to G1, which adds an
1/2 1
AD8552 additional gain stage and, in conjunction with CF, establishes
2
4
the slew rate of the model at 0.5 V/µs. M5 and M6 are in a
S common-source configuration, similar to the output stage of the
M1 G
Si9433 AD855x amplifier. EG1 and EG2 fix the quiescent current in
D these two transistors at 100 µA, and also help accurately simu-
MONITOR
OUTPUT R2 late the VOUT vs. IOUT characteristic of the amplifier.
2.49kV
The network around ECM1 creates the common-mode voltage
error, with CCM1 setting the corner frequency for the CMRR
Figure 61. A High-Side Load Current Monitor roll-off. The power supply rejection error is created by the
network around EPS1, with CPS3 establishing the corner fre-
V+
quency for the PSRR roll-off. The two current loops around
R2
nodes 80 and 81 are used to create a 42 nV/√Hz noise figure
2.49kV across RN2. All three of these error sources are reflected to the
VOUT input of the op amp model through EOS. Finally, GSY is used
Q1
to accurately model the supply current versus supply voltage in-
V+ crease in the AD855x.
This macro-model has been designed to accurately simulate a
number of specifications exhibited by the AD855x amplifier,
R1
100V
1/2 AD8552 and is one of the most true-to-life macro-models available for
0.1V any op amp. It is optimized for operation at +27°C. Although
RETURN TO
RSENSE GROUND the model will function at different temperatures, it may lose
accuracy with respect to the actual behavior of the AD855x.
Figure 62. A Low-Side Load Current Monitor
Precision Voltage Comparator
The AD855x can be operated open-loop and used as a precision
comparator. The AD855x has less than 50 µV of offset voltage
when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the de-
vice has a propagation delay of 15 µs on the rising edge and
8 µs on the falling edge.
Care should be taken to ensure the maximum differential volt-
age of the device is not exceeded. For more information, please
refer to the section on Input Overvoltage Protection.

REV. 0 –17–
AD8551/AD8552/AD8554

99 CCM1

21 22
D1
9 RCM1
I1 +
V1 RCM2
ECM1 2

8 99
98

RC7 RC8 80 81
C2
+
17 18
VN1 RN1 HN 2 RN2
RC3 RC4
M1 11 12 M2
7
1 M3 M4 2
98
2 + 10
EOS 99
CPS3
D2 99 CPS1
RC1 I2 RC2
13 70
V1
RPS1 72 73
RPS3
GSY 0 2
50 EPS1 RPS4
RPS2 +
14 16
71
C1 50 CPS2
RC5 RC6 98
50 99

+
50
98 EG1
2 2
EVP M5
46
C2 + 97
D3 CF
30
45
D4
31 32 G1 R1 + 51
R2 47
+ EVN 2 + M6
E1 R3 EG2
2 98
2
98
+ 98 50
EREF
2
0

Figure 63. Schematic of the AD855x SPICE Macro-Model

–18– REV. 0
 AD8551/AD8552/AD8554
SPICE macro-model for the AD855x * VOLTAGE NOISE REFERENCE OF 42nV/rt(Hz)
* AD8552 SPICE Macro-model *
* Typical Values VN1 80 98 0
* 7/99, Ver. 1.0 RN1 80 98 16.45E-3
* TAM / ADSC HN 81 98 VN1 42
* RN2 81 98 1
* Copyright 1999 by Analog Devices *
* * INTERNAL VOLTAGE REFERENCE
* Refer to “README.DOC” file for License *
* Statement. Use of this model indicates EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
* your acceptance of the terms and GSY 99 50 (99,50) 48E-6
* provisions in the License Statement. EVP 97 98 (99,50) 0.5
* EVN 51 98 (50,99) 0.5
* Node Assignments *
* noninverting input * LHP ZERO AT 7MHz, POLE AT 50MHz
* | inverting input *
* | | positive supply E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
* | | | negative supply R2 32 33 3.7E+3
* | | | | output R3 33 98 22.74E+3
* | | | | | C3 32 33 1E-12
* | | | | | *
.SUBCKT AD8552 1 2 99 50 45 * GAIN STAGE
* *
* INPUT STAGE G1 98 30 (33,98) 22.7E-6
* R1 30 98 259.1E+6
M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 CF 45 30 45.4E-12
M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 D3 30 97 DX
M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 D4 51 30 DX
M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 *
RC1 4 14 9E+3 * OUTPUT STAGE
RC2 6 16 9E+3 *
RC3 17 11 9E+3 M5 45 46 99 99 POX L=1E-6 W=1.111E-3
RC4 18 12 9E+3 M6 45 47 50 50 NOX L=1E-6 W=1.6E-3
RC5 14 50 1E+3 EG1 99 46 POLY(1) (98,30) 1.1936 1
RC6 16 50 1E+3 EG2 47 50 POLY(1) (30,98) 1.2324 1
RC7 99 17 1E+3 *
RC8 99 18 1E+3 * MODELS
C1 14 16 30E-12 *
C2 17 18 30E-12 .MODEL POX PMOS (LEVEL=2,KP=10E-6,
I1 99 8 100E-6
I2 10 50 100E-6 + VTO=-1,LAMBDA=0.001,RD=8)
V1 99 9 0.3 .MODEL NOX NMOS (LEVEL=2,KP=10E-6,
V2 13 50 0.3 + VTO=1,LAMBDA=0.001,RD=5)
D1 8 9 DX .MODEL PIX PMOS (LEVEL=2,KP=100E-6,
D2 13 10 DX + VTO=-1,LAMBDA=0.01)
EOS 7 1 POLY(3) (22,98) (73,98) (81,98)
+ 1E-6 1 1 1 .MODEL NIX NMOS (LEVEL=2,KP=100E-6,
IOS 1 2 2.5E-12 + VTO=1,LAMBDA=0.01)
* .MODEL DX D(IS=1E-14,RS=5)
* CMRR 120dB, ZERO AT 20Hz .ENDS AD8552
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70 0 1E+6
RPS2 71 0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16

REV. 0 –19–
AD8551/AD8552/AD8554
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead MSOP 8-Lead SOIC

(RM Suffix) (R Suffix)

C3688–8–10/99
0.1968 (5.00)
0.122 (3.10)
0.114 (2.90) 0.1890 (4.80)

8 5
8 5 0.1574 (4.00) 0.2440 (6.20)
0.122 (3.10) 0.199 (5.05) 0.1497 (3.80) 1 4 0.2284 (5.80)
0.114 (2.90) 0.187 (4.75)
1 4
PIN 1 0.0688 (1.75) 0.0196 (0.50)
x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
PIN 1
0.0040 (0.10)
0.0256 (0.65) BSC
0.120 (3.05) 0.120 (3.05) 8°
0.112 (2.84) 0.112 (2.84) 0.0500 0.0192 (0.49) 0° 0.0500 (1.27)
SEATING (1.27) 0.0098 (0.25)
0.043 (1.09)
0.006 (0.15) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 0.0160 (0.41)
0.037 (0.94)
0.002 (0.05) 338
0.018 (0.46) 278
SEATING 0.008 (0.20) 0.011 (0.28) 0.028 (0.71)
PLANE 0.003 (0.08) 0.016 (0.41)

8-Lead TSSOP 14-Lead TSSOP

(RU Suffix) (RU Suffix)

0.122 (3.10) 0.201 (5.10)

0.114 (2.90) 0.193 (4.90)

8 14 8
5
0.177 (4.50)
0.169 (4.30)
0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)

0.256 (6.50)
0.246 (6.25)
1
4 1 7

PIN 1
PIN 1
0.0256 (0.65)
0.006 (0.15) BSC 0.006 (0.15)
0.002 (0.05) 0.0433 0.002 (0.05) 0.0433
(1.10) (1.10)
MAX 0.028 (0.70) MAX
88 88 0.028 (0.70)
0.0118 (0.30) 08 0.020 (0.50) 0.0256 0.0118 (0.30) 08 0.020 (0.50)
SEATING 0.0079 (0.20) SEATING 0.0079 (0.20)
(0.65)
PLANE 0.0075 (0.19) PLANE 0.0075 (0.19)
0.0035 (0.090) BSC 0.0035 (0.090)

14-Lead SOIC
(R Suffix)

0.3444 (8.75)
0.3367 (8.55)

14 8 PRINTED IN U.S.A.
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 7 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

0.0532 (1.35) x 458
0.0098 (0.25) 0.0099 (0.25)
0.0040 (0.10)

88
0.0500 0.0192 (0.49) 08 0.0500 (1.27)
SEATING (1.27) 0.0099 (0.25)
PLANE BSC 0.0138 (0.35)
0.0075 (0.19) 0.0160 (0.41)

–20– REV. 0