library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Xilinx-specific primitive library
library UNISIM;
use UNISIM.VComponents.all;
entity my is
Port (
A : in std_logic_vector(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
--Ones : out STD_LOGIC_VECTOR(3 downto 0);
--Twos : out STD_LOGIC_VECTOR(3 downto 0)
--SF : out STD_LOGIC_VECTOR(3 downto 0)
--control_0, control_1, control_2, control_3 : out STD_LOGIC_VECTOR(2
downto 0)
pp0 : out std_logic_vector(10 downto 0);
pp1, pp2, pp3 : out std_logic_vector(8 downto 0)
);
end my;
architecture Structural of my is
-- Booth groups
signal Ones, Twos, SF : std_logic_vector(3 downto 0);
-- Control signal
signal control_0, control_1, control_2, control_3 : STD_LOGIC_VECTOR(2
downto 0);
--Necessary Signal for PP
signal A_comp8 : std_logic_vector(7 downto 0);
signal A_sig : std_logic_vector(8 downto 0);
signal A_sig_2 : std_logic_vector(8 downto 0);
signal A_sig_com : std_logic_vector(8 downto 0);
signal A_sig_com_2 : std_logic_vector(8 downto 0);
begin
-- Compute 8-bit 2's complement of A
A_comp8 <= std_logic_vector(-signed(A));
-- Compute intermediate signals
A_sig <= not A(7) & A;
A_sig_2 <= not A(7) & A(6 downto 0) & '0';
A_sig_com <= not A_comp8(7) & A_comp8;
A_sig_com_2 <= not A_comp8(7) & A_comp8(6 downto 0) & '0';
-- 3rd bit of ones and twos
LUT_o_t_3 : LUT6_2
generic map (
INIT => X"1818181866666666"
)
port map (
I0 => B(5),
I1 => B(6),
I2 => B(7),
I3 => '0',
I4 => '0',
I5 => '1',
O5 => Ones(3),
O6 => Twos(3)
);
-- 2nd bit of ones and twos
LUT_o_t_2 : LUT6_2
generic map (
INIT => X"1818181866666666"
)
port map (
I0 => B(3),
I1 => B(4),
I2 => B(5),
I3 => '0',
I4 => '0',
I5 => '1',
O5 => Ones(2),
O6 => Twos(2)
);
-- 1st bit of ones and twos
LUT_o_t_1 : LUT6_2
generic map (
INIT => X"1818181866666666"
)
port map (
I0 => B(1),
I1 => B(2),
I2 => B(3),
I3 => '0',
I4 => '0',
I5 => '1',
O5 => Ones(1),
O6 => Twos(1)
);
-- oth bit of ones and twos
LUT_o_t_0 : LUT6_2
generic map (
INIT => X"1818181866666666"
)
port map (
I0 => '0',
I1 => B(0),
I2 => B(1),
I3 => '0',
I4 => '0',
I5 => '1',
O5 => Ones(0),
O6 => Twos(0)
);
-- Sign calculatio
SF(3) <= B(7) and ( Ones(3) or Twos(3));
SF(2) <= B(5) and ( Ones(2) or Twos(2));
SF(1) <= B(3) and ( Ones(1) or Twos(1));
SF(0) <= B(0) and ( Ones(0) or Twos(0));
--Control signal
control_0 <= Ones(0) & Twos(0) & SF(0);
control_1 <= Ones(1) & Twos(1) & SF(1);
control_2 <= Ones(2) & Twos(2) & SF(2);
control_3 <= Ones(3) & Twos(3) & SF(3);
-- Generate pp0 (11 bits) based on control signals for bit 0
pp0 <=
"10000000000"
when control_0 = "000" else
A_sig_2(8) & not(A_sig_2(8)) & not(A_sig_2(8)) & A_sig_2(7 downto 0)
when control_0 = "010" else
not(A_sig_com_2(8)) & A_sig_com_2(8) & A_sig_com_2
when control_0 = "011" else
A_sig(8) & not(A_sig(8)) & not(A_sig(8)) & A_sig(7 downto 0)
when control_0 = "100" else
A_sig_com(8) & not(A_sig_com(8)) & not(A_sig_com(8)) & A_sig_com(7
downto 0) when control_0 = "101" else
(others => '0');
-- Generate pp1 (9 bits) based on control signals for bit 3
pp1 <=
"100000000" when control_1 = "000" else
A_sig_2 when control_1 = "010" else
A_sig_com_2 when control_1 = "011" else
A_sig when control_1 = "100" else
A_sig_com when control_1 = "101" else
(others => '0');
-- Generate pp2 (9 bits) based on control signals for bit 3
pp2 <=
"100000000" when control_2 = "000" else
A_sig_2 when control_2 = "010" else
A_sig_com_2 when control_2 = "011" else
A_sig when control_2 = "100" else
A_sig_com when control_2 = "101" else
(others => '0');
-- Generate pp3 (9 bits) based on control signals for bit 3
pp3 <=
"100000000" when control_3 = "000" else
A_sig_2 when control_3 = "010" else
A_sig_com_2 when control_3 = "011" else
A_sig when control_3 = "100" else
A_sig_com when control_3 = "101" else
(others => '0');
end Structural;
