AIM:
i. To experimentally test the working of IC 74138 as 3 to 8-line decoder/demultiplexer
(Demux).
ii. To realize a 4 to 16 decoder/demultiplexer using 3-to-8-line decoder ICs.
iii. To realize a combinational circuit using a decoder IC.
iv. Cascading of Mux and Demux.
DEVICES, COMPONENTS AND EQUIPMENTS REQUIRED:
SL.NO NAME SPECIFICATION QUANTITY
1 Decoder IC IC 74138 2
2 4 Input NAND Gate IC 7420 1
3 NOT Gate IC 7404 2
4 Digital Trainer Kit - 1
THEORY:
Discrete quantities of information are represented are in digital systems by binary codes.
A binary code of n bits capable of representing up to 2n distinct elements of coded information.
A decoder is a combinational circuit that converts the binary information from n input lines to a
maximum of 2n unique output lines. If the n-bit coded information has unused combinations, the
decoder may have less than 2n output. The decoder presented here are called n-to-m line
decoders, when m≤2n. In the 2-to-8 IC decoder (IC 74LS138), there are three input lines and
eight output lines. The enable input E is used to enable or disable the decoding process.
Decoding is necessary in applications such as data multiplexing, 7 segment display and memory
address decoding.
De-multiplexer performs the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
̅1 as
control of selection signals. The 74LS138 decoder can be used as a demultiplexer by using E
the data input D, holding the other two enable inputs in their active states and using CBA input
as the select in the recivers, and security monitoring systems, etc.
Decoders with enable inputs can be connected together to form a larger decoder circuit. A
4-to-16 lined decoder can be implemented using two 3-ti-8-line decoders.
A decoder provides the 2n minterms if n input variable. Since any Boolean function can
be expressed in sum-of-minterms form, a decoder that generate the minterms of the function,
together with an external OR gate that forms their logical sum provides a hardware
implementation of the function. In this way, any combinational circuit with n inputs and m
output can be implemented with an n-to-2n lined decoder and m OR gates. The procedure of
implementing a combinational circuit using decoder is illustrated by taking a full subtracter
circuit.
d (x, y, z) = ∑ (1,2,4,7)
b (x, y, z) = ∑ (1,2,3,7)
Since there are three inputs and a total of eight minterms, we need a three-to-eight-line
decoder. The decoder generates the eight minterms for x, y and z. The OR gate for output D
forms the logical sum of minterms 1,2,4 and 7. The OR gate for output B forms the logical sum
of minterms 1,2,3 and 7.
A function with a long list of minterms requires an OR gate with a large number of
inputs. A function having a list of k minterms can be expressed its complemented form F’ with
2n – k minterms a sum-of-minterms function and is equivalent to a two-level AND-OR circuit.
IC 74LS138
The 74LS138 decoders one-of-eight lines; based upon the conditions at the three binary
select inputs and the three enable inputs. Two active-low and one active-high enable inputs
reduce the need for external gates or inverts when expanding. A 24-line decoder can be
implemented with no external inverts, and a 32-line decoder requires only one inverter. An
enable input can be used as a data input for demultiplexing applications. All of these
decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its
driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-
ringing and simplify system design.
Pin Diagram:
B ̅𝟎
𝐎
C ̅𝟏
𝐎
̅𝟐
𝐎
̅𝟑
𝐎
̅𝟒
𝐎
̅𝟓
𝐎
̅𝟔
𝐎
Function Table of 3-to-8-line decoder:
- Input Binary Outputs
𝐄̅𝟏 𝐄̅𝟐 𝐄̅𝟑 C B A ̅𝟎
𝐎 ̅𝟏
𝐎 ̅𝟐
𝐎 ̅𝟑
𝐎 ̅𝟒
𝐎 ̅𝟓
𝐎 ̅𝟔
𝐎 ̅𝟕
𝐎
X X 0 X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
1 X X X X X 1 1 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 0 0 0 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0
STUDY OF 3 TO 8 LINE DECODER AS DEMULTIPLEXER
̅𝟎
𝒐
̅𝟏
𝒐
Data Input ̅𝟐
𝒐
Din
1 ̅𝟑
𝒐
0 ̅𝟒
𝒐
̅𝟕
𝒐 ̅𝟓
𝒐
̅𝟔
𝒐
Function Table of 3-to-8-line decoder as demultiplexer
Data-in Enable Address Outputs
̅̅̅
𝐄𝟏 ̅𝟐
𝑬 ̅𝟑
𝑬 C B A ̅𝟎
𝒐 ̅𝟏
𝒐 ̅𝟐
𝒐 ̅𝟑
𝒐 ̅𝟒
𝒐 ̅𝟓
𝒐 ̅𝟔
𝒐 ̅𝟕
𝒐
X X 0 X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
1 X X X X X 1 1 1 1 1 1 1 1
X 0 1 0 0 0 Din 1 1 1 1 1 1 1
X 0 1 0 0 1 1 Din 1 1 1 1 1 1
X 0 1 0 1 0 1 1 Din 1 1 1 1 1
X 0 1 0 1 1 1 1 1 Din 1 1 1 1
X 0 1 1 0 0 1 1 1 1 Din 1 1 1
X 0 1 1 0 1 1 1 1 1 1 Din 1 1
X 0 1 1 1 0 1 1 1 1 1 1 Din 1
X 0 1 1 1 1 1 1 1 1 1 1 1 Din
REALIZATION OF 4 TO 16 LINE DECODCircuit Diagram:
U2
1 15 ̅𝟎
𝒐
A Y0
2 14 ̅𝟏
𝒐
3 B Y1 13
C Y2 ̅𝟐
𝒐
12 ̅𝟑
𝒐
6 Y3 11
G1 Y4 ̅𝟒
𝒐
10 ̅𝟓
𝒐
4 Y5 9 ̅𝟔
𝒐
~G2A Y6 7 ̅𝟕
𝒐
A 5 Y7
~G2B
B
74LS138D
C
U1
1 15 ̅𝟖
𝒐
A Y0
U3A 2 14 ̅𝟗
𝒐
3 B Y1 13
C Y2 ̅𝟏𝟎
𝒐
12 ̅𝟏𝟏
𝒐
D 6 Y3 11 ̅𝟏𝟐
𝒐
G1 Y4 10 ̅𝟏𝟑
𝒐
4 Y5 9
7404N ~G2A Y6 ̅𝟏𝟒
𝒐
7 ̅𝟏𝟓
𝒐
5 Y7
~G2B
74LS138D
4 to 16 decoders using 3-to-8-line decoder
ICs
Input Output
D C B A 𝒐
̅𝟎 𝒐
̅𝟏 𝒐
̅𝟐 𝒐
̅𝟑 𝒐
̅𝟒 𝒐
̅𝟓 𝒐
̅𝟔 𝒐
̅𝟕 𝒐
̅𝟖 𝒐
̅𝟗 𝒐
̅𝟏𝟎 𝒐
̅𝟏𝟏 𝒐
̅𝟏𝟐 𝒐
̅𝟏𝟑 𝒐
̅𝟏𝟒 𝒐
̅𝟏𝟓
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FUNCTION TABLE:
0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
4 TO 16 DECODER USING 3 TO 8 LINE DECODER IC
0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
REALIZATION OF LOGIC FUNCTIONS USING DECODERS
F1 = (x, y, z) =
F2 = (x, y, z) =
X Y Z F1 F2
CASCADING OF MUX AND DEMUX
U1
1 16
A VCC
2 B 15 ̅𝟎
𝒐
Y0 14
Y1 ̅𝟏
𝒐
3 13 ̅𝟐
𝒐
C Y2 12
Max Output Data Input Y3 ̅𝟑
𝒐
11 ̅𝟒
Y4 10 𝒐
Y5 9 ̅𝟓
𝒐
Y6 7 ̅𝟔
𝒐
Y7 ̅𝟕
𝒐
74LS138D
Function Table:
Mux Demux
Max
Select lines Output Select line Demux Output
X
S2 S1 S0 A B C
PROCEDURE:
i. Refer the data sheets of the ICs and test the ICs for proper working.
ii. Give the connections as per the circuit diagram.
iii. Check the Vcc and Ground connections to the ICs
iv. Switch on the supply.
v. Verify the working of the circuit.
RESULT:
