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MCQ's

The document consists of a series of multiple-choice questions related to computer architecture and microprocessor concepts, specifically focusing on memory types, addressing modes, and processor flags. Each question provides options with correct answers indicated by checkmarks. Topics covered include virtual memory, cache memory, RISC architecture, and instruction sets in the 8085 microprocessor.

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0% found this document useful (0 votes)
14 views4 pages

MCQ's

The document consists of a series of multiple-choice questions related to computer architecture and microprocessor concepts, specifically focusing on memory types, addressing modes, and processor flags. Each question provides options with correct answers indicated by checkmarks. Topics covered include virtual memory, cache memory, RISC architecture, and instruction sets in the 8085 microprocessor.

Uploaded by

pratik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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QUESTIONS

1) Virtual memory consists of

✓a) Static RAM


b) Dynamic RAM
c) Magnetic memory
d) None of these

2) Cache memory acts between


✓a) CPU and RAM
b) RAM and ROM
c) CPU and Hard Disk
d) None of these

3) Which of the following memory is non-volatile?


a) SRAM
b) DRAM
✓c) ROM
d) All of the above

4) What does MAR stand for?


a) Main Address Register
b) Memory Access Register
c) Main Accessible Register
✓d) Memory Address Register

5) In 8085, 16-bit address bus, which can address upto?


a) 16KB
b) 32KB
✓c) 64KB
d) 128KB

6) In 8085, 16-bit address bus, which can address upto?


✓a) 16KB
b) 32KB
c) 64KB
d) 128KB

7) This signal indicates that another master is requesting the use of the address
and data buses.
a) READY
✓b) HOLD
c) HLDA
d) INTA

8) MVI K, 20H is an example of?


✓a) Immediate addressing mode
b) Register addressing mode
c) Direct addressing mode
d) Indirect addressing mode

9) 8086 has ___ address bus.


a) 16-bit
b) 18-bit
✓c) 20-bit
d) 24-bit

10) An instruction which can be used to clear lower 4 bits of addressing 8085 is
a) XOR FFH
b) OR F0H
✓c) ANI F0H
d) None of Above

11) Which of the below will not affect the status flags
✓a) JMP
b) ANI
c) OR
d) None of Above

12) If data and instruction are stored in different memories the architecture is
termed as _________
a) Von Neumann architecture
✓b) Harvard architecture
c) CICS Architectures
d) None of Above

13) Which of the following is not true in case of pipelined processor


✓a) Single cycle execution
b) Multi Cycle execution
c) None

14) The kind of computer architecture that has common block of memory for both code
as well as data
and simultaneously cannot access both is called as ______
✓a) Von Neumann architecture
b) Harvard architecture
c) RISC architecture
d) Modified Harvard architecture

15) The stack of X-86 based processor is


a) Upward growing stack
✓b) Downward growing stack
c) Configurable by the the programmer as upward growing or downward growing
d) None of the above

16) The number of data lines of a processor basically indicates


✓a) The no of bits the processor can access
b) The total memory capacity(size) accessible by the processor
c) The processor has memory mapped I/O
d) None of above

17) Which of the following are the typical characteristics of RISC machine
a) Instruction taking multiple cycle
b) Highly pipelined
c) Instruction interpreted by micro programs
✓d) Multiple register sets

18) Memory access in RISC architecture is limited to instruction


a) CALL & RET
b) PUSH & POP
✓c) STA & LDA
d) MOV & JMP

19) Single-bit indicators that may be set or cleared to show the result of logical
or arithmetic operation
are
✓a) Flags
b) Registers
c) Monitors
d) Decisions

20) The register in the 8085 is used to keep track of the memory address of next
op-code to be run in
the program is
a) Stack pointer
✓b) Program Counter
c) Instruction pointer
d) Accumulator

21) A register in the microprocessor that keeps track of the answer or result of
any arithmetic or logic
operation is
a) Stack Pointer
b) Program Counter
c) Instruction Pointer
✓d) Accumulator

22) Which one of the following is not a vectored interrupt?


a) TRAP
✓b) INTR
c) RST 7.5
d) RST 3

23) The processor status word of 8085 microprocessor has five flags namely
✓a) S, Z, AC, P, CY
b) S, OV, AC, P, CY
c) S, Z, OV, P, CY
d) S, Z, AC, P, OV

24) CALL instruction is a ______ instruction.


a) 4 bytes
b) 2 bytes
c) 1 bytes
✓d) 3 bytes

25) RST0 - RST7 are the __________ in 8085.


a) hardware interrupts
b) logical interrupts
✓c) software interrupts
d) conditional interrupts

26) ________used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5)
by setting various
bits to form masks or generate output data via the Serial Output Data (SOD) line.
a) RIM
✓b) SIM
c) EI
d) DI

27) After the execution of CMP A instruction


a) ZF is set and CY is reset
b) ZF is set and CY is unchanged
c) ZF is reset and CY is set
✓d) ZF is reset and CY is unchanged

28 ) S0 and S1 pins are used for


a) serial communication
✓b) indicating the processor’s status
c) acknowledging the interrupt
d) none of the abov

29)What is the flag status of carry flag and auxiliary carry flag in the given 8085
program
MVI A,FFH
MVI B,01H
MOV H,A
ADD B
1) AC = 0, CY = 0
2) AC = 0, CY = 1
3) AC = 1, CY = 0
✓4) AC = 1, CY = 1

30)Find odd instruction in the following set


1) JNZ
2) JZ
3) CALL
✓4) PUSH

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