INDEX

1. Experiment 1:.............................................................................2
2. Experiment 2:.............................................................................4
3. Experiment 3:.............................................................................7
4. Experiment 4:.............................................................................9
5. Experiment 5:...........................................................................12
6. Experiment 6:...........................................................................15
7. Experiment 7:...........................................................................18
8. Experiment 8:...........................................................................22

1
 Experiment 1
Aim: To understand the operation of half adder and full adder circuits using logic gates and
to verify their truth tables.
Apparatus Required:
1. Half Adder Full Adder Kit
2. Power supply (DC)
3. Logic gates (AND, OR, XOR, NAND, NOR)
4. Resistors
5. LEDs
6. Connecting wires
Theory: A half adder is a digital circuit that performs addition of two binary digits. It has two
inputs, typically labeled as A and B, and two outputs, one for the sum (S) and another for
the carry (C). The truth table for a half adder is as follows:

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

A full adder, on the other hand, is a digital circuit that adds three binary digits - two inputs
(A and B) and a carry input (Cin). It produces two outputs, one for the sum (S) and another
for the carry (Cout). The truth table for a full adder is as follows:

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

2
Procedure:
1. Set up the breadboard and connect the power supply.
2. Connect the logic gates according to the circuit diagrams for the half adder and full adder.
3. Connect the inputs A and B for both the half adder and full adder circuits.
4. For the full adder, connect an additional input Cin.
5. Connect LEDs to the output pins for observing the results.
6. Apply power and verify the outputs with reference to the truth tables.
7. Note down the observations.
Precautions:
1. Ensure correct connections of power supply and logic gates to avoid short circuits.
2. Handle the components carefully to prevent damage.
3. Double-check the connections before applying power to the circuit.
4. Use proper labeling for inputs, outputs, and power connections.
5. Avoid applying excessive voltage or current to the circuit.
Result:
1. The half adder circuit correctly produces the sum and carry outputs based on the inputs A
and B.
2. The full adder circuit produces the sum and carry outputs considering the inputs A, B, and
Cin.
3. The observed outputs match the expected results as per the truth tables for both half
adder and full adder circuits.

Fig: Half Adder circuit

3
 Experiment 2
Aim:
To understand the conversion process between binary and Gray codes and to demonstrate
the implementation of these conversions using digital logic gates.
Apparatus Required:
1. Binary Gray Conversion Kit 2. XOR gates 3. LEDs 4. Resistors 5. Wires 6. Power supply (5V)
Theory:
Binary code is a numerical system that uses only two symbols, typically “0” and “1”, to
represent numbers. Gray code is a binary numeral system where two consecutive values
differ in only one bit position. The conversion between binary and Gray code involves
specific algorithms to ensure accuracy.
Procedure:
1. Connect the power supply to the breadboard and ensure it is delivering a stable 5V
output.
2. Place the XOR gates on the breadboard.
3. Connect the input switches representing binary numbers (A, B, C, D) to the XOR gates’
input pins.
4. Connect the LEDs to the output pins of the XOR gates.
5. Configure the connections according to the truth table provided.
6. For converting binary to Gray: - Set the binary input switches to the desired binary
number. - Observe the corresponding Gray code displayed on the LEDs.
7. For converting Gray to binary: - Set the Gray code input switches to the desired Gray
code. - Observe the corresponding binary number displayed on the LEDs.
8. Record the observations carefully, ensuring the correctness of the conversions.
Precautions:
1. Handle the kit with care to avoid damage. 2. Ensure proper connections and polarity
while connecting the components. 3. Double-check the wiring to prevent short circuits. 4.
Be cautious while handling the power supply to avoid electric shock. 5. Follow the truth
table accurately to obtain correct results.
Result:
Upon successful implementation of the experiment, the conversion process between binary
and Gray codes is demonstrated effectively. The LEDs display the corresponding Gray code
when converting binary to Gray and vice versa, validating the functionality of the circuit.

4
 Fig: Binary to Gray code
converter

Truth Table:

Binary (A, B, C, D) Gray (G3, G2, G1, G0)

0000 0000

0001 0001

0010 0011

0011 0010

0100 0110

0101 0111

0110 0101

0111 0100

1000 1100

1001 1101

1010 1111

1011 1110

5
1100 1010

1101 1011

1110 1001

1111 1000

6
 Experiment 3
Aim: To understand the working principle of a multiplexer and to demonstrate its
functionality in data transmission.
Apparatus Required:
1. Multiplexer Kit
2. Connecting wires
3. Power supply
4. Logic gates (AND, OR, NOT)
5. LEDs
6. Resistors
Theory: A multiplexer (MUX) is a digital device that selects one of several analog or digital
input signals and forwards the selected input into a single line. It is often used in digital
systems for data transmission, communication, and signal routing applications.
The most common type of multiplexer is the binary mux, which has 2^n input lines and n
selection lines, where n is the number of address bits. The number of input lines determines
the size of the data selector, allowing it to choose between 2^n input lines.
The multiplexer’s operation relies on the binary selection input, which is decoded to choose
one of the input lines. The selected input is then transferred to the output line. The
selection process follows a predefined truth table based on the number of input lines and
selection bits.
Procedure:
1. Connect the power supply to the kit.
2. Ensure proper voltage levels.
3. Connect the ground and Vcc pins of the kit to the power supply.
4. Connect the input lines and output lines to the appropriate pins of the multiplexer.
5. Connect the selection inputs (address lines) to the logic gates for control.
6. Apply logic signals to the selection inputs to choose different input lines.
7. Observe the output and verify the functionality of the multiplexer.
8. Repeat the process with different input combinations and observe the changes in the
output.
9. Measure voltages and currents at various points using a digital multimeter for further
analysis.

7
Fig: Circuit of multiplexer

Truth table:

Precautions:
1. Ensure correct connections as per the circuit diagram.
2. Avoid short circuits and incorrect polarity connections.
3. Handle the components with care to prevent damage.

Result: Upon completion of the experiment, the functionality of the multiplexer was
successfully demonstrated. The truth table for the multiplexer operation was verified,
showing the expected output for different input combination.

8
 Experiment 4
Aim: To understand the functionality and behavior of SR and D flip-flops, and to observe
their truth tables.
Apparatus Required:
1. Flip Flop Kit
2. Power supply unit
3. Connecting wires
4. LEDs (Light Emitting Diodes)
5. Resistors
6. Switches
Theory: Flip-flops are fundamental sequential logic circuits capable of storing binary
information. The SR (Set-Reset) flip-flop and D (Data) flip-flop are two common types.
1. SR Flip-Flop: It has two inputs - Set (S) and Reset (R), and two outputs - Q and Q’. When S=0
and R=1, the flip-flop is reset, and Q=0. When S=1 and R=0, it is set, and Q=1. When both S
and R are 0, the flip-flop maintains its previous state.

2. D Flip-Flop: It has a single data input (D) and operates on the rising or falling edge of the
clock signal. When the clock signal changes state, the input D is transferred to the output Q.

3. JK Flip-Flop: Combines features of SR flip-flop with a toggle function, allowing for stable
states, toggling, and no race conditions. J and K inputs control the state transitions, while a
high level on both toggles the output.

4. T Flip-Flop (Toggle Flip-Flop): Toggles its output state with each rising edge of the clock
signal when the T input is high. It simplifies toggling functionality compared to JK flip-flop by
having only one input controlling the state change.

Procedure:
1. Connect the power supply unit to the breadboard.
2. Connect as per circuit diagram.
3. Connect the necessary resistors, LEDs, and switches to simulate the input and output
states.
4. Apply logic levels to the Set (S), Reset (R), and clock inputs.
5. Observe the output states and record the observations.
6. Repeat the procedure for the D flip-flop.
7. Construct truth tables based on the observed states for both flip-flops.

9
 S R Q(t) Q(t+1)
0 0 - Q
0 1 Q 0
1 0 0 Q’
1 1 - -

2. D Flip-Flop Truth Table:

D CLK Q(t) Q(t+1)
0 ↑ - 0
0 ↓ - 0
1 ↑ - 1
1 ↓ - 1

3.JK Flip Flop Truth Table:

CLK J K Qn+1

↑ 0 0 Qn

↑ 0 1 0

↑ 1 0 1

↑ 1 1 Qn’

4. T Flip Flop Truth Table:

T Qn Qn+1

0 0 0

0 1 1

1 0 1

1 1 0

These tables illustrate the behavior of the flip-flops under different input conditions.

10
 D Flip Flop

JK Flip Flop T Flip Flop

Precautions:
1. Ensure correct connections according to the circuit diagram.
2. Avoid short circuits by double-checking connections.
3. Handle kit carefully to prevent damage from electrostatic discharge.
Result:
Flip Flops truth table have been verified.
Experiment 5
Aim: To understand the functionality and behavior of Shift Registers and to observe their
operations.
Apparatus Required:
1. Shift Register Kit
2. Power supply unit

11
 3. Connecting wires
4. Switches
Theory:

Serial in Serial Out register.

Serial in Parallel Out register.

Shift registers are digital circuits used for serial-to-parallel or parallel-to-serial data
conversion and storage. They can shift data bits in and out, making them essential
components in applications like data storage, signal processing, and serial communication.
Basic Shift Register Operation: Shift registers consist of flip-flops arranged in a chain, with
data shifting from one flip-flop to the next on clock pulses.
Types of Series Shift Registers:
a. Serial-In-Serial-Out (SISO): Data enters serially and exits serially.
b. Serial-In-Parallel-Out (SIPO): Data enters serially and exits in parallel.
Procedure:
1. Connect the power supply unit to the breadboard.
2. Connect the shift register Kit according to the datasheet and circuit diagram.

12
 3. Connect the switches to simulate the input and output states.
4. Apply clock pulses and input data to the shift register inputs.
5. Observe the shifting of data and record the observations.

A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data
bit.
The output from each flip-Flop is connected to the D input of the flip-flop at its right.
Shift registers hold the data in their memory which is moved or “shifted” to their required
positions on each clock pulse.

Clock Pulse No. QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

13
 3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Precautions:
1. Ensure correct connections according to the circuit diagram.
2. Avoid short circuits by double-checking connections.
3. Handle kit carefully to prevent damage from electrostatic discharge.
4. Use appropriate voltage levels and current-limiting resistors to prevent damage to the
LEDs.
5. Verify the functionality of the circuit before applying power.
Result:
Truth table of shift registers have been verified.

14
 Experiment 6
Aim: To study the operation and behavior of asynchronous and synchronous up-down
counters and observe their count sequences in both up and down counting modes.
Apparatus Required:
1. Counter IC Kit
2. Power supply unit
3. Connecting wires
4. LEDs (Light Emitting Diodes)
5. Resistors
6. Switches
Theory:
An ‘N’ bit binary counter consists of ‘N’ T flip-flops. If the counter counts from 0 to 2 N − 1,
then it is called as binary up counter. Similarly, if the counter counts down from 2 N − 1 to 0,
then it is called as binary down counter.
Asynchronous Counters:
Asynchronous counters, also known as ripple counters, use flip-flops that change state
based on the output of the previous flip-flop. Each flip-flop represents a binary bit in the
counter. The clock input for each flip-flop is derived from the output of the previous flip-
flop, resulting in a ripple effect when counting.

Synchronous Counters:
Synchronous counters use a common clock signal for all flip-flops, ensuring that all flip-flops
change state simultaneously. This eliminates the ripple effect seen in asynchronous
counters and allows for faster and more accurate counting.

Up Counters:
Up counters increment their count value with each clock pulse. For example, in a 4-bit up
counter, the count sequence would be 0000, 0001, 0010, 0011, and so on.

Down Counters:

15
Down counters decrement their count value with each clock pulse. For example, in a 4-bit
down counter, the count sequence would be 1111, 1110, 1101, 1100, and so on.

Procedure:
1. Connect the power supply unit to the breadboard.
2. Connect the counter kit according to the datasheet and circuit diagram.
3. Connect LEDs to the output pins of the counter to visualize the count sequence.
4. Connect the clock generator or pulse source to the clock input of the counter.
5. For synchronous counters, ensure that all flip-flops receive the clock signal
simultaneously.
6. Apply clock pulses and observe the count sequence for both up and down counting
modes.
7. Record the observed count sequence and note any differences between
asynchronous and synchronous counters.
Truth table of an asynchronous binary Up Counter :

Number of Edge Qo (LSB) Q1 Q2(MSB)

0 0 0 0

1 1 0 0

2 0 1 0

3 1 1 0

4 0 0 1

5 1 0 1

6 0 1 1

7 1 1 1

Precautions:
1. Ensure correct connections according to the circuit diagram.

16
2. Avoid short circuits by double-checking connections.
3. Handle kit carefully to prevent damage from electrostatic discharge.
4. Use appropriate voltage levels and current-limiting resistors to prevent damage to the
LEDs.
5. Verify the functionality of the circuit before applying power.
Result:
Counters have been verified.

Experiment 7:

Aim:
To study the characteristics of a NPN transistor in common emitter configuration and to evaluate:

1. Input resistance

17
2. Output resistance

3. Current gain

Apparatus Required:

1. Analog Board (ABO4)

2. DC Power Supply

3. 2mm Patch Cords

4. Digital Multimeter(x3)

Theory:

The NPN transistor is a widely used semiconductor device with three layers of doped semiconductor
material. In common emitter configuration, the emitter is connected to ground, the base is the input
terminal, and the collector is the output terminal. This configuration offers high current and voltage
gain, making it suitable for amplification purposes.

1. Input Resistance:

The input resistance Rin of the transistor in common emitter configuration can be
determined using small-signal analysis. It represents the ratio of change in input voltage to
change in input current while keeping the output voltage constant. Input resistance is
influenced by the biasing conditions and transistor parameters such as doping levels,
geometry, and temperature.

2. Output Resistance:

The output resistance, Rout characterizes the transistor's ability to maintain a stable output
voltage when subjected to variations in load resistance. It is defined as the ratio of change in
output voltage to change in output current while keeping the input voltage constant. Output
resistance depends on transistor construction, biasing, and load conditions.

3. Current Gain:

The current gain β (also known as the hFE) of the transistor is a measure of how much the
collector current IC changes in response to a change in base current IB while keeping the
collector-emitter voltage Vce, constant. It is defined as β=IC/IB .The current gain varies with
biasing conditions and operating conditions.

18
Readings and Graphs:

Vce = 1v
3 Vce = 3v
Vce = 5v

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Input Characteristics

S. No Input voltage VBE Input Current Ib at constant output voltage

1 0 VCE = 1v VCE = 3v VCE = 5v
2 0.1 0 0 0
3 0.2 0 0 0
4 0.3 0 0 0
5 0.4 0 0 0
6 0.5 0 0 0
7 0.6 0 0 0
8 0.7 0.6 0.6 0.6
9 0.8 2.7 2.6 2.5
10 0.9 5.5 5.3 5.2

19
 ㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤ
ㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤㅤ Output Characteristics

Output Output current at constant value of input current

voltage VCE IB = 0 IB = 10muA IB = 20muA IB = 30muA IB = 40muA
0 0 0 0 0 0
0.5 0 0.2 0.7 1.4 2
1 0 0.2 0.7 1.4 2
2 0 0.2 0.7 1.4 2
3 0 0.2 0.7 1.4 2
4 0 0.2 0.7 1.4 2
5 0 0.2 0.7 1.4 2
6 0 0.2 0.7 1.4 2
7 0 0.2 0.7 1.4 2
8 0 0.2 0.7 1.4 2

Procedure:

3.5

2.5
Ib = 10
Ib = 20
2
Ib = 30
1.5 Ib = 40

0.5

0
0 1 2 3 4 5 6 7 8 9 10

1. Setup: Construct the common emitter configuration circuit using the NPN transistor,
appropriate resistors, and a DC power supply.
2. Biasing: Apply appropriate bias voltages to the base, emitter, and collector terminals
to ensure the transistor operates in the active region.
3. Measurements:
 Apply a small AC signal to the input and measure the corresponding changes
in input and output voltages and currents.
 Vary the load resistance and observe the changes in output voltage and
current.

20
Result:

Based on the experimental data and calculations, the characteristics of the NPN transistor in
common emitter configuration can be analyzed, and the input resistance, output resistance,
and current gain can be evaluated. Corresponding graphs are plotted.

21
 Experiment 8:

Aim:
To study the characteristics of a Junction Field-Effect Transistor (JFET) in a common source
configuration and evaluate its output/drain characteristics and transfer characteristics.

Apparatus Required:

1. Analog Board (ABO8)

2. DC Power Supply

3. 2mm Patch Cords

4. Digital Multimeter

Theory:

A Junction Field-Effect Transistor (JFET) is a three-terminal semiconductor device that operates by

controlling the conductivity of a channel between two terminals (the source and drain) using an
electric field applied across a semiconductor junction (the gate). JFETs are majority carrier devices,
meaning that current flow occurs due to the movement of majority carriers (either electrons or
holes) within the semiconductor channel. The most common types of JFETs are N-channel and P-
channel, depending on the majority carriers used for conduction. In a common source configuration,
the source terminal is grounded, the input signal is applied to the gate, and the output is taken from
the drain terminal.

A) Output/Drain Characteristics:
The output or drain characteristics of a JFET describe the relationship between the drain current (ID)
and the drain-source voltage (VDS) with the gate-source voltage (VGS) held constant. These
characteristics provide insights into the operating regions of the JFET and are crucial for
understanding its behaviour in different circuit configurations. The main operating regions include:

 Ohmic Region: In this region, the JFET behaves as a linear resistor. The drain current (ID)
increases linearly with the drain-source voltage (VDS), typically controlled by the drain-
source resistance (RD).

 Pinch-off Region: As the drain-source voltage (VDS) increases, the channel between the
source and drain narrows until it reaches a point where the channel is effectively pinched off.
At this point, the drain current (ID) becomes nearly constant, and the JFET enters saturation.

22
 Saturation Region: In this region, the drain current (ID) remains relatively constant despite
further increases in the drain-source voltage (VDS). The JFET operates as a voltage-controlled
current source, with the drain current primarily determined by the gate-source voltage
(VGS).

 Breakdown Region: Beyond saturation, if the drain-source voltage (VDS) continues to

increase, the JFET may enter a breakdown region where the drain current (ID) increases
sharply, leading to device failure.

B) Transfer Characteristics:
The transfer characteristics of a JFET illustrate the relationship between the drain current (ID)
and the gate-source voltage (VGS) with the drain-source voltage (VDS) held constant. These
characteristics provide insights into the JFET's conductivity and threshold voltage. Key
parameters and regions include:

 Threshold Voltage (Vth): The gate-source voltage at which the JFET just starts conducting,
representing the point where the channel begins to form between the source and drain
terminals.

 Conductance (G): The slope of the transfer characteristics curve represents the
transconductance (Gm), a measure of how effectively the JFET responds to changes in the
gate-source voltage (VGS) by controlling the drain current (ID).

 Transconductance (Gm): Transconductance is a key parameter that characterizes the

relationship between the input signal applied to the gate of a JFET and the resulting change
in drain current. It measures the sensitivity of the drain current to variations in the gate-
source voltage, assuming the drain-source voltage remains constant. Mathematically,
transconductance (Gm) is defined as the ratio of the change in drain current (ΔID) to the
change in gate-source voltage (ΔVGS), expressed as:

Gm = ΔID / ΔVGS
Transconductance is typically measured in Siemens (S) or mhos.

 Amplification Factor (μ): The amplification factor, also known as mutual conductance, refers
to the ratio of the change in drain current (ΔID) to the change in drain-source voltage (ΔVDS),
assuming the gate-source voltage remains constant. Amplification factor (μ) indicates how
effectively the JFET amplifies the input signal. Mathematically, amplification factor (μ) is
expressed as:

23
 μ = ΔID / ΔVDS

Amplification factor is dimensionless and provides insight into the amplification capability of
the JFET.

 AC Drawn Resistance (RD): AC drawn resistance, also known as dynamic drain-source

resistance, is a measure of how the drain-source voltage (VDS) changes in response to a
change in the drain current (ID) under AC conditions, while the gate-source voltage (VGS) and
the drain-source voltage (VDS) are constant. It represents the incremental resistance offered
by the JFET to the AC component of the drain current. Mathematically, AC drawn resistance
(Rd) is expressed as:

RD = ΔVDS / ΔID

AC drawn resistance is typically measured in ohms and plays a crucial role in analysing the
small-signal behaviour of the JFET in AC circuits.

 DC Drawn Resistance (RDC):

DC drawn resistance, also known as static drain-source resistance, is a measure of the change
in drain-source voltage (ΔVDS) resulting from a change in the drain current (ΔID) under DC
conditions, while the gate-source voltage (VGS) remains constant. It represents the resistance
offered by the JFET to the DC component of the drain current. Mathematically, DC drawn
resistance (RDC) is expressed as:

RDC = ΔVDS / ΔID

DC drawn resistance is typically higher than AC drawn resistance and is important for-
analysing the large-signal behaviour of the JFET in DC circuits.

Readings and Graphs:

24
 ID (mA)
VDS VGS = 0V VGS = -1V VGS = -2V
0 0 0 0
1 14.6 10 2.8
2 23.1 17.5 3.6
3 28.2 19 4
4 32.8 19.4 4.4
5 36.1 21.7 4.6
6 36.95 26 4.9
7 36.86 29.4 5.1
8 36.27 33.7 22.1
9 36 33.3 26.2

S. No IB (μA) IC (mA)
1 0 0
2 10 3.4
3 20 7.1
4 30 10.9
5 40 14.8
6 50 18.9
7 60 22.8
8 70 26.8
9 80 31.2
10 90 35.1
11 100 38.9

At VGS = -3V, ID = 0mA

25
 40

35

30

25

20

15

10

0
0 1 2 3 4 5 6 7 8 9 10

X axis: Vds

Y axis: Id

Input characteristics

X axis: Ib

Y axis: Ic

Output characteristics

Procedure:

26
 1. Connect the JFET to the breadboard as described.

2. Connect the DC power supply unit to provide biasing voltage to the JFET.

3. Connect the signal generator to the gate terminal of the JFET.

4. Connect the drain resistor (RD) between the drain terminal and the positive supply voltage.

5. Connect the source terminal of the JFET to ground.

6. Apply a small AC signal to the gate terminal using the signal generator.

7. Set the signal generator to produce a small AC voltage signal with a known frequency and
amplitude.

8. Vary the gate voltage (VGS) in small increments and record the corresponding drain current
(ID) using a multimeter.

9. Measure the drain-source voltage (VDS) for each set of VGS and record the values.

10. Repeat steps 8-9 for different values of VGS to cover the desired range.

11. Calculate the transconductance (gm), amplification factor (μ), and AC drawn resistance (rd)
using the collected data.

12. Plot graphs of drain current (ID) vs. drain-source voltage (VDS) for different values of gate-
source voltage (VGS) to observe the output/drain characteristics.

13. Plot graphs of drain current (ID) vs. gate-source voltage (VGS) for different values of drain-
source voltage (VDS) to observe the transfer characteristics.

Precautions:

1. Ensure accurate measurements using the multimeter.

2. Maintain consistency in the experimental setup and conditions.

3. Take multiple readings to ensure data accuracy and reliability.

4. Handle the JFET and other components carefully to prevent damage.

27
 5. Follow proper safety procedures when working with electrical equipment.

Result:

 Graphs of drain current (ID) vs. drain-source voltage (VDS) for different gate-source voltages
(VGS) were plotted to observe output/drain characteristics.

 Graphs of drain current (ID) vs. gate-source voltage (VGS) for various drain-source voltages
(VDS) were plotted to observe transfer characteristics.

28