VLSI DESIGN (22ECC24 )

Dr.P.Anuradha
Associate Professor
ELECTRONICS & COMMUNICATION ENGINEERING
Chaitanya Bharathi Institute of Technology (A)

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 VLSI DESIGN UNIT IV Syllabus
UNIT–IV Designing of CMOS Circuits: Sub system design Principles, Dynamic logic, BiCMOS
inverter, pass transistors, Latch-up in CMOS Circuits, Domino logic, Transmission gate logic
circuits, Multiplexer and D flip flop using Transmission gates. Design of complex circuits using AOI
and OAI

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Implementation of AOI and OAI gates using CMOS Logic
Implementation of AOI and OAI gates using CMOS Logic
Example of OR-AND-INVERT (OAI) gate :F = (A + B + C) · D)
 THE PASS TRANSISTOR
• Unlike bipolar transistors, the isolated nature of the gate allows MOS
transistors to be used as switches in series with lines carrying logic
levels in a way that is similar to the use of relay contacts.
• This application of the MOS device is called the pass transistor and
switching logic arrays can be formed.
• PTL uses NMOS or PMOS transistor to transfer charge from input to
output under the control gate voltage
• These circuits widely used in design of ROM’s,PLA’s,MUX etc.
• NMOS permits flow of current from source to drain when the input is
1 i.e. the input at the source and appears on the drain.
• PMOS permits flow of current from source to drain when the input is
0 i.e. the input at the source and appears on the drain.
 NMOS PTL PMOS PTL

Input Control Output Input Control Output

0 0 X 0 0 0
1 0 X 1 0 1
0 1 0 0 1 X
1 1 1 1 1 X
2:1 MUX implementation using a pass-transistor logic
2:1 MUX implementation using a pass-transistor logic
4:1 MUX implementation using a pass-transistor logic
 Pass transistors

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 Transmission Gate(TG)

• A transmission gate is an electronic element and good non mechanical relay built with CMOS
technology.
• It is a parallel connection of nMOS and pMOS transistors that realizes a simple switch.
• The inputs to gate of one transistor of the nMOS and pMOS are complementary to each other.
The symbol of a transmission gate is shown below in fig

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 Design of 2 : 1 MUX using CMOS transmission gate

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 Design of XOR gate using CMOS transmission gate

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 D Latch using Transmission Gate logic
• D latch stores a logic level. This is often called 1 bit register or delay flip flop
• It has single data input D and two outputs: Q and
• The latch is a level-sensitive device and it is transparent when the clock is high if it is a
positive level-sensitive latch and when the clock is low it is called negative level-sensitive
latch.
• In latch the output (Q) is dependent only on the level of the clock (Clk). In this latch D is
control the output .
• This is also called level triggered flip flop, the output of the FF changes as long as the clock
signal at logic high.
• When the clock signal goes to zero, the output will simply preserve its state.

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 D Latch

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• The TG at the input is activated by the CK signal, whereas the TG in the inverter
loop is activated by the inverse of the CK signal.
• Thus, the input signal is accepted (latched) into the circuit when the clock is high,
and this information is preserved as the state of the inverter loop when the clock
is low.
• The operation of the CMOS D-latch circuit can be better visualized by replacing
the CMOS transmission gates with simple switches

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 Positive D latch using transmission Gate
When Clk = high (1) T1 is ON and T2 is OFF, so output (Q) directly follows
the input (D)
When Clk = low (0) T1 is OFF and T2 is ON, now
new data entering into the latch is stopped and we
get only previously-stored data at the output.
 Negative D latch using transmission Gate
It is also consist of two transmission gate and two inverters. It is working in
an exactly opposite manner of the positive level-sensitive D latch.
 Negative D latch using transmission Gate
When Clk = low (0) T1 is ON and T2 is OFF, so output (Q) directly follows the
input (D).
When Clk = high (1) T1 is OFF and T2 is ON, now new data entering into the
latch is stopped and we get only previously-stored data at the output.
 Edge Triggered D Flip flop using a transmission gate
D flip flop is an edge-triggered device which means the output (Q) follows the input (D)
only at the active edge (for positive rising edge) of the clock (for the positive edge-
triggered) and retain the same value until the next rising edge i.e. output does not change
between two rising edges, it should be changed only at the rising edge.

Positive edge-triggered D FF using Transmission gate

 Edge Triggered D Flip flop using a transmission gate
• It is a combination of negative level-sensitive latch and positive level-sensitive latch.
• It consists of two level-sensitive latches:
• A negative level-sensitive latch (Master)
• A positive level-sensitive latch (Slave)
• The Master latch captures the data when the clock is low.
• The Slave latch captures the data from the Master when the clock goes high.
• This ensures that the output changes only on the clock's active edge (either rising or falling),
making it an edge-sensitive device.
• When Clk= LOW (0) T1, T4 is ON and T2, T3 is OFF.
• New data (D) is continuously entering through T1 and getting
• stored till the edge of T2 (path is D-1-2-3-4 and at node 4 it stops) it cannot pass
through T2 and T3 transmission gate because they are off. This operation for the
master latch. For slave latch it keeps retaining the previously stored value of
output (Q) (path is 5-6-7-8-5).
• When Clk= HIGH (1) T2, T3 are ON and T1, T4 are OFF.
• Now master latch did not allow new data to enter into the device because T1 is
OFF and the previously stored data at point 4 is going through the path 4-1-2-5-
6-Q and this same data is reflected at the output and this does not change until
the next rising edge and this same data is also going to the transmission gate T4
(path is 4-1-2-5-6-7-8 and stops because transmission gate T4 is OFF).