Proceedings of the 2024 Sustainable Research and Innovation Conference

JKUAT Main Campus, Kenya

2 - 3 October, 2024

Quantitative Analysis of Switching Losses and

Efficiency Estimation in High-Frequency Power
Device Applications
J.M. Kinyua*, M. Aoki

The resultant of the ridging phenomenon and overshoot is the

Abstract— In pursuit of enhancing the performance of power increased converter power losses, the introduction of
converters, high-frequency power devices have become indispensable substantial EMI noise, and subsequent failure of SiC MOSFET
due to their superior switching capabilities and efficiency. This work if its limits are exceeded threatening its reliability. Additionally,
systematically presents a detailed analysis of parasitic elements in a significant power loss especially in lower power levels and
high-frequency power converter switches and subsequent power loss fast-charging 𝑑𝑣 ⁄𝑑𝑡 and 𝑑𝑖 ⁄𝑑𝑡 generates the EMI. The effects
distribution. The efficiency estimation of a Dual Active Bridge (DAB)
of parasitic elements also become severe as the switching
converter developed by utilizing the wide band gap semiconductor
power devices Silicon Carbide Metal-oxide Semiconductor field performance is intensified, which is crucial in achieving the
Effect Transistor (SiC MOSFET) and SiC diode which fully leverages device's real performance. Therefore, the high switching
the advantages of the SiC over silicon is presented. A comprehensive frequency in SiC MOSFETs significantly imposes an inevitable
analysis of switching characteristics and estimation of efficiency in the challenge in realizing a seamless switching operation albeit
high-frequency device is also presented. The switching losses and ability to work at higher power densities [4]. With increased
specifically the turn-on loss which is considered dominant are losses, their positive trend is limited. However, due to its ultra-
investigated and quantified. Other losses including voltage and current low recovery loss of body diodes, low trail current, low
turn-off, the conduction loss, the reverse recovery loss, and the gate conduction loss over a wide range, and the precedent favorable
drive losses are investigated. It's observed that the efficiency of the
converter is 2.91% higher by use of SiC devices than Si devices. The
conditions, the cumulative loss in a SiC is lower than in Si
efficiency estimation is validated through detailed studies with the help devices. Additionally, due to its higher breakdown field
of the LTSpice simulation software. strength, the SiC device has quite low on-state drain resistance,
which makes the conduction losses significantly low.
Keywords— SiC MOSFETs, Electromagnetic Interference Soft switching becomes an important technique that is
(EMI), Snubber circuit, switching losses, turn-on loss, turn-off loss. employed to alleviate these problems. All the presiding research
agrees that the high 𝑑𝑖 ⁄𝑑𝑡 and 𝑑𝑣 ⁄𝑑𝑡 occurring during the
I. INTRODUCTION switching transients coupled with parasitic elements of the
circuits are responsible for the oscillations. The authors of [5]
The evolution and continuous development of switching
try to design an RLC equivalent circuit that aids in dampening
devices with improved fast switching speed, low on-state
the oscillations during the turn-on and turn-off switching
resistance, low switching losses, Wide Band Gap (WBG), high
process. It is reported by [6] that the RC snubber when placed
blocking voltages, improved thermal conductivity, high
next to the module aids in reducing the switching ridging.
operational temperature capability, and high voltage
However, this will be at a cost and complexity of the circuit.
capabilities present optimism in the next generation of power
Additionally, the introduction of SiC diodes significantly
devices. The development of Silicon Carbide (SiC) MOSFET
reduces the main switching device stress as the reverse recovery
devices has kept a fast pace by ensuring that they seamlessly
current is absent as compared to Si diodes.
meet the requirements of extremely high performance [1].
It is good practice to ensure that the conduction loss in the
Additionally, the SiC MOSFET performs perfectly and
switches and the High-Frequency Transformer (HFT) is
efficiently when operating in high power density conversion
maintained significantly low. The power loss known as
and fast switching [2]. These devices possess superior
circulating loss resulting from the energy commutating ideally
characteristics over and above their counterpart (Si) Silicon
stored by the energy storage devices of the circuit should be
semiconductor devices, especially in the reduction of power
scaled down. Whereas in some instances, this circulating
loss, which makes them have improved efficiency even when
current is critical in achieving the ZVS, it should be maintained
operating at very high switching frequencies.
just enough for ZVS. The authors of [7] note that these current
High-frequency systems are characterized by being compact,
and voltage oscillations can be suppressed effectively by the
albeit smaller passive elements. The major limitations in high
introduction of the gate resistance though at the expense of the
switching are ridging, high oscillation, and overshoot since
loss and switching time.
current and voltage fluctuate precipitously during the turn-on
and turn-off operation [3].
J.M. Kinyua*, Department of Electrical & Mechanical Engineering, NiTech A Mutsumi, Department of Electrical & Mechanical Engineering, NiTech
(e-mail: j.kinyua.325@stn.nitech.ac.jp) (e-mail: aoki.mutsumi@nitech.ac.jp)

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 Proceedings of the 2024 Sustainable Research and Innovation Conference
JKUAT Main Campus, Kenya
2 - 3 October, 2024

process and analysis of the switching losses as well as

knowledge of their dominant contributors. This will aid in the
The losses in a power switching device include the off-state
consideration of how to limit these losses during high-
blocking losses, the turn-on-switching loss, the turn-off
frequency operations. The quest for the above issues and a
switching losses, and the conduction losses. The turn-on losses,
defined precise methodology to quantify
which is the most dominant loss consist of two sub-parts, that
is; the current rise and voltage fall. The switch configuration
consists of the switch, with an anti-parallel freewheeling diode. + Rstray
The reverse recovery behavior of the freewheeling diode and
the parasitic capacitance significantly affects the turn-on of the D Coss,D L Coss,L
switch. Figure 1, is a switch with its parasitic capacitances
indicated. Figure 2 is a typical circuit adopted to assist in
modeling the switching characteristics, and the analysis of the iload(t)
switching losses. The circuit equivalent model consists of the Ld
main parasitic elements, the constant voltage source 𝑉𝑑𝑐 , the Drain
output source current 𝐼𝑑𝑠 . The drive gate signal is assumed to Vdc ids(t)
Cgd
be commutating between -4V to 𝑉𝑑𝑟−𝑚𝑎𝑥 with an insignificantly Cds

Vds
small rise time and fall time, which is a square wave voltage. Rg Gate Cextn
Vdrive
𝑉𝑔𝑠 is the gate-source voltage, 𝑉𝑑𝑠 is the drain-source voltage. Cgs
The parasitic elements, which are the gate-source capacitance Source
𝐶𝑔𝑠 , drain-source capacitance 𝐶𝑑𝑠 , gate-drain capacitance, also
known as miller capacitance 𝐶𝑔𝑑 , 𝑉𝑑𝑟 is the square wave gate Ls
-
driver output voltage, 𝐼𝑑𝑠 is the drain current, 𝐼𝑐ℎ is the channel
current, 𝐼𝑑𝑖𝑜𝑑𝑒 is the diode current, 𝑉𝑑𝑖𝑜𝑑𝑒 is the cathode-anode Fig. 2 SiC MOSFET test Circuit.
voltage of the SiC Schottky diode. 𝑅𝑔 is gate drive resistance,
these losses is the main motivation behind this work.
𝑅𝑒𝑥𝑡 is the external gate resistance, 𝑅𝑠𝑡𝑟𝑎𝑦 is the parasitic stray
The rest of the paper is organized as follows. Section II gives
circuit resistance. The common nonlinear parasitic capacitances a detailed explanation of the switching sequences of SiC
are 𝐶𝑟𝑠𝑠, 𝐶𝑖𝑠𝑠 and 𝐶𝑜𝑠𝑠 . The value of the input capacitance is MOSFETs switches, and Section III gives the analysis and the
given as 𝐶𝑖𝑠𝑠 = 𝐶𝑔𝑠 + 𝐶𝑔𝑑 , and the MOSFET output mathematical formulation used to quantify the converter losses
capacitance is given as 𝐶𝑜𝑠𝑠 = 𝐶𝑔𝑑 + 𝐶𝑑𝑠 . 𝐶𝑟𝑠𝑠, is the reverse and efficiency. Section IV is a typical simulation of the SiC
transfer capacitance. MOSFET and the simulation results. Finally, section V gives a
brief conclusion.
Drain
II. SWITCHING SEQUENCE OF THE SIC MOSFET
Cgd
The switching characteristics of the SiC MOSFET involve
Cds
Vds
the turn-on and turn-off of the switch with charging and
Gate discharging of the various nonlinear parasitic capacitances.
Cgs Switching loss constitutes the highest power loss of the power
dissipated during the whole switching event [10].
Source

Fig. 1 SiC MOSFET Parasitic Capacitances.

Switching losses assessment is inevitable since it aids in Vdd
Vgs
understanding the losses and coming up with a methodology of VMiller
minimization. This is imperative as they have a significant Vth Igs
effect on the overall system efficiency. The switching times, the
drain-source resistance during conduction 𝑅𝑑𝑠(𝑜𝑛) and the Current Overshoot
parasitic capacitances shown in Figure 2 cause non-ideal I0 Ids
behaviors, ultimately resulting in increased losses. Vds
It is agreed by the authors of [8] that there is a scarcity of an
accurate and detailed elucidation of the SiC MOSFET
switching loss estimation process. Additionally, there is an urge Eon
Eon
for various designers to push the switching frequency higher.
t9 to t1 t2 t3 t4 T(ns)
This necessitates a clear understanding of the various analysis
and switching methodologies [9]. Furthermore, adopting a
higher frequency switching for the inverter comes with a cost Fig. 3 SiC MOSFET switching transients- during the turn-on process
because of high power losses, reducing the efficiency. This This is imperative to note when computing the converter
therefore calls for a clear understanding of the switching losses. Ideally, the reverse recovery effects are usually not

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 Proceedings of the 2024 Sustainable Research and Innovation Conference
JKUAT Main Campus, Kenya
2 - 3 October, 2024

considered, it is assumed to have a zero voltage drop and slope is determined by the gate current that flows through the
insignificant junction capacitance. The turn-on and turn-off are 𝐶𝑔𝑑 = 𝐶𝑟𝑠𝑠 . 𝑉𝑔𝑠 and 𝐼𝑑𝑠 insignificantly varies.
completely independent. Figure 3 is a typical turn-on event in a
SiC MOSFET. Stage 4( 𝑡3 < 𝑡 < 𝑡4 ): Voltage Fall Time: Gate Remaining
Charging Time
After the 𝑉𝑑𝑠 value reaches its minimum, the miller plater
A. Turn-on Switching Transients/Transition
ends. 𝑉𝑔𝑠 charges 𝐶𝑔𝑠 and continues to rise till it reaches the
It is noted clearly that during the turn-on process, the drive maximum of 𝑉𝑐𝑐 which is imposed by the driver voltage. 𝑉𝑑𝑠
circuit state changes from -4V to maximum 𝑉𝑑𝑟_𝑚𝑎𝑥 . and 𝐼𝑑𝑠 are in their steady state condition. At this stage, the
Consequently, the drain current linearly increases till the final value of 𝐼𝑔𝑠 falls to zero as shown in Figure 2. After this, the
value while the drain-source voltage drops to zero. This is switch will be in a conduction state till the next turn-off begins.
realized since the freewheeling diode is forward-biased at the
beginning, which forces it to sustain drain-source voltage B. Turn-off Switching Transients/Transition Process
constant till the SiC MOSFET conducts all the output current. Figure 3 is a waveform presentation of the turn-off events of
The working regions of the model are divided into small a SiC MOSFET switch. This happens when the gate drive
segments for easy elucidation [11], [12]. The wave patterns are voltage imposes a varying voltage 𝑉𝑑𝑟𝑖𝑣𝑒_𝑚𝑎𝑥 and reduces to a
observed as the drive voltage is applied at the gate and source minimum. The gate current 𝐼𝑔𝑠 , the drain current 𝐼𝑑𝑠 , the gate-
terminals of the switch at normal operating conditions. A brief source voltage 𝑉𝑔𝑠 , and the gate drive voltage 𝑉𝑑𝑟 are indicated.
elucidation of these stages is given in the sub-sections below.
The turn-off process can be divided into smaller parts for
Notingly, increasing the internal drain to source voltage higher
explanation.
than the (𝑉𝑔𝑠 − 𝑉𝑡ℎ ) makes the MOSFET enter into saturation.
Stage 1(𝑡0 < 𝑡 < 𝑡1 ): Turn-on Time Delay:
Initially, the applied drive voltage between the gate and
source is zero (-4V). Then, 𝑉𝑔𝑠 begins to rise. 𝐶𝑔𝑑 and 𝐶𝑔𝑠 will
be charged by the gate's current 𝐼𝑔 .The majority of the current Vdd
charges in the 𝐶𝑔𝑠 thus is higher than 𝐶𝑔𝑑 . As the gate signal is VMiller
increased, the switch remains in cut off region until it reaches Vth Vgs
the threshold voltage, 𝑉𝑔𝑠_𝑡ℎ . Gate voltage rises with a time
Igs
constant which is defined by switch-equivalent capacitance
(𝐶𝑖𝑠𝑠 = 𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) and gate resistance 𝑅𝑔 . The stage has no I0
Voltage Overshoot
Ids
switching losses since the switch is not activated. Only that the
Vds
load current circulates through the diode. This stage ends when
𝑉𝑔𝑠 reaches 𝑉𝑔𝑠_𝑡ℎ . When the threshold voltage 𝑉𝑔𝑠_𝑡ℎ is lower
than the gate-to-source 𝑉𝑔𝑠 , The MOSFET remains off, and the Switching loss
value of the drain current 𝐼𝑑 remains zero. 𝑉𝑑𝑠 and 𝐼𝑑𝑠 do not region
change [13], [14]. t4 t5 t6 t7 t8 t9 T(ns)
Stage 2(𝑡1 < 𝑡 < 𝑡2 ): Current Rise Period: Fig. 4 SiC MOSFET Switching transients during the turn-off process
Increasing the 𝑉𝑔𝑠 , higher than the threshold voltage
𝑉𝑔𝑠_𝑡ℎ will have the switch start to turn on. Drain current 𝐼𝑑𝑠 Stage 5(𝑡4 < 𝑡 < 𝑡5 ): On-State Operation:
starts to increase from zero to its maximum value 𝐼𝑑𝑠−𝑚𝑎𝑥 The switch enters into the conduction mode. At this stage, it
taking over the load current. This is known as the current rise handles the total inductive load current 𝐼𝑑𝑠 . The 𝑉𝑑𝑠(𝑜𝑛) at this
period. This current increases high above the load current 𝐼𝑜 - stage is not zero and contributes to the conduction losses. Figure
the load current commutates from the freewheeling diode to the 4 is an illustration of the SiC MOSFET waveforms during the
switch-which is still conducting. This is contributed by the off-transition. This includes the gate drive voltage 𝑉𝑑𝑟 , the gate-
freewheeling diode reverse current. 𝑉𝑑𝑠 remains almost source voltage 𝑉𝑔𝑠 , drain-source voltage 𝑉𝑑𝑠 and the gate's
constant in this region at blocking conditions [15], [16]. current 𝐼𝑔𝑠 . Since the switch was in an ON state, the value of
𝑉𝑑𝑠(𝑜𝑛) is low at the beginning and 𝐼𝑑𝑠 high. The switch input
Stage 3(𝑡2 < 𝑡 < 𝑡3 ): Voltage fall Time I, Miller Plateau:
capacitance 𝐶𝑖𝑠𝑠 is discharged through 𝐼𝑔𝑠 and the 𝑅𝑔 as 𝑉𝑔𝑠
In this stage, the freewheeling diode has been switched off
begin to decrease when the gate drive 𝑉𝑑𝑟 is decreased as
blocking voltage. The reverse recovery current decreases from
explained in the next stage.
𝐼𝑑𝑠−𝑚𝑎𝑥 to 𝐼𝑑𝑠 , thereafter remains constant. The Miller effect
takes place and the 𝑉𝑔𝑠 is clamped at 𝑉𝑔𝑠 = 𝑉𝑀𝑖𝑙𝑙𝑒𝑟 . When 𝐼𝑑𝑠 is Stage 6(𝑡5 < 𝑡 < 𝑡6 ): Turn-off Delay Time:
held constant by the external circuit the SiC MOSFET operates The gate voltage 𝑉𝑔𝑠 , decreases up to 𝑉𝑀𝑖𝑙𝑙𝑒𝑟 . The voltage
in saturation region known as Miller plateau. 𝑉𝑔𝑠 thus remains 𝑉𝑑𝑠(𝑜𝑛) remains significantly low and the switch current 𝐼𝑔𝑠
almost constant. 𝑉𝑑𝑠 drops fairly quickly from the maximum to insignificantly changes. The rate of 𝑉𝑔𝑠 decrease is given by a
the minimum value given by 𝐼𝑜 𝑅𝑑𝑠(𝑜𝑛) in this region. The 𝑉𝑑𝑠
time constant dependent on the switch input capacitance 𝐶𝑖𝑠𝑠

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 Proceedings of the 2024 Sustainable Research and Innovation Conference
JKUAT Main Campus, Kenya
2 - 3 October, 2024

and the gate resistor 𝑅𝑔 . The input capacitance 𝐶𝑖𝑠𝑠 is With 𝑃𝐶𝑜𝑛𝑑 as the total conduction loss and the 𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 is the
discharged through the gate drive circuit. total switching loss. These power SiC MOSFETs can be
modeled like small resistors thus the computation can be done
Stage 7(𝑡6 < 𝑡 < 𝑡7 ): Voltage Rise Time: Miller Plateau.
in a similar way to that of resistor power dissipation. This is
In this region, the switch is in saturation. The voltage 𝑉𝑔𝑠 because when the current flows through the 𝑅𝐷𝑆(𝑜𝑛) the power
reaches the 𝑉𝑀𝑖𝑙𝑙𝑒𝑟 and remains insignificantly changing within is dissipated as heat from the SiC MOSFET. Thus;
the region. At the same time, 𝐶𝑔𝑑 is discharged. 𝐼𝑔𝑠 and 𝐼𝑑𝑠 𝑃𝐶𝑜𝑛𝑑 = 𝑅𝐷𝑆(𝑜𝑛) .𝐼𝑟𝑚𝑠
2
(2)
remains constant in this stage. Drain source voltage 𝑉𝑑𝑠 rises to 2
Where the 𝐼𝑟𝑚𝑠
is expressed as in (3) when driven by a square
the bus voltage 𝑉𝑑𝑐 .
wave, with D as the duty cycle [19], [20].
Stage 8(𝑡7 < 𝑡 < 𝑡8 ): Voltage Rise Time II: (3)
𝐼𝑟𝑚𝑠 =𝐼𝑜 √𝐷
The load current 𝐼𝑑𝑠 starts to divert from the switch to the The cumulative gate resistance can be computed as follows:
freewheeling diode as the freewheeling diode is no longer
blocking voltage as it is forward-biased. 𝐼𝑑𝑠 quickly decreases 𝑅𝑔 = 𝑅𝑔(𝑖𝑛𝑡) + 𝑅𝑔(𝑒𝑥𝑡) (4)
to zero at the end of this region. An overshoot of 𝑉𝑑𝑠 occurs in Where the 𝑅𝑔 is the total gate resistance, 𝑅𝑔(𝑖𝑛𝑡) is the internal
this region due to the parasitic component induced by the
gate resistance and 𝑅𝑔(𝑒𝑥𝑡) is the total external gate resistance.
current. This stage ends when the 𝑉𝑔𝑠 drops to 𝑉𝑡ℎ . Once the
The conduction loss of the SiC Schottky power diode can also
drain current decreases, the SiC MOSFET suffers extra voltage
be calculated based on the dynamic resistance, 𝑅𝑜𝑛(𝑑𝑖𝑜𝑑𝑒) .
stress, as there is a voltage drop across the parasitic inductances.
Thus :
Stage 9(𝑡8 < 𝑡 < 𝑡9 ): Current Falling Time/Voltage Ridging 2
𝑃𝐶_𝑑𝑖𝑜𝑑𝑒 =𝑅𝑜𝑛(𝑑𝑖𝑜𝑑𝑒) 𝐼𝐷.𝑟𝑚𝑠 (5)
Time:
The conduction time 𝑡𝑜𝑛 constitutes the current rise time (𝑡𝑟𝑖 )
The drain-source voltage 𝑉𝑑𝑠 forms and oscillations (ridging) and voltage fall time (𝑡𝑓𝑣 ), and 𝑡𝑜𝑓𝑓 is the total voltage rise time
since there exist parasitic components (stray inductance and ( 𝑡𝑟𝑣 ) and current fall time ( 𝑡𝑓𝑖 ) [21]. Therefore, the total
SiC MOSFET output capacitance) and thereafter remain fairly
switching power loss of the switch is given as:
constant after the overshoot. The stray capacitance eventually
damps the high frequency and all the ridging energy is 1 (6)
dissipated whereas the value of 𝑉𝑔𝑠 continue to exponentially 𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 = 𝑉𝑑𝑠 𝐼𝑑𝑠 (𝑡𝑜𝑛 + 𝑡𝑜𝑓𝑓 )𝑓𝑠𝑤
2
decrease with a constant dependent on 𝐶𝑖𝑠𝑠 and 𝑅𝑔 till it reaches
zero. With the on-time loss and off-time loss being given by (7) and
(8).
Stage 10(𝑡9 < 𝑡 < 𝑡0 ): Off State Operation:
1 (7)
𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔(𝑜𝑛) = 𝑡𝑜𝑛 𝑉𝑑𝑠 𝐼𝑑𝑠 𝑓𝑠𝑤
2
Eventually, the inductive load current flows through the SiC
Schottky diode. In this region, there are no losses. 1 (8)
𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔(𝑜𝑓𝑓) = 𝑡𝑜𝑓𝑓 𝑉𝑑𝑠 𝐼𝑑𝑠 𝑓𝑠𝑤
III. ANALYSIS OF SWITCHING LOSS. 2
There is an insignificantly small to almost zero reverse The voltage 𝑉𝑑𝑠 and the current 𝐼𝑑𝑠 transition period is the
recovery charge due to the use of the Schottky diodes which are period in which the turn-on losses occur. The turn-on events
the majority of device carriers in SiC devices, this means that occur between the time 𝑡1 to 𝑡3 . Therefore:
there is no reverse recovery charge. The implication is that for 𝑡𝑜𝑛 = 𝑡1- 𝑡3. (9)
the computation in this manuscript, the recovery loss of the
diode is ignored [17] [18]. This transition of voltage and current occurs during turn-on
There are three main power losses in a SiC MOSFETs events in the periods defined by (𝑡1 − 𝑡2 ) and (𝑡2 −
converter. These include the power loss as a result of the 𝑡3 ) corresponds to 𝐼𝑑𝑠 and 𝑉𝑑𝑠 transitions respectively as
overlap of the non-zero current and voltage in the drain-source illustrated in Figure 2. Similarly, the transitional period for the
path during switching, the power loss as a result of the changing turn-off period is between intervals (𝑡6 − 𝑡7 ) and (𝑡7 −
and discharging of the gate-source and gate-drive parasitic 𝑡8 ) corresponding to 𝑉𝑑𝑠 and 𝐼𝑑𝑠 transitions.
capacitances (hence called switching power loss), and the 𝑡𝑜𝑓𝑓 = 𝑡6- 𝑡8 (10)
conduction power loss since when the switch gets into the on-
The switching loss for each of the SiC MOSFET can be
state, the 𝑉𝑑𝑠(𝑜𝑛) is usually not zero. These losses affect the
computed using the presiding mathematical formulas. In the
overall performance of the power conversation devices. case of a single-phase full DC-DC converter. Four SiC
The total switch loss can be computed as follows: MOSFET switches are used. The general efficiency of the
converter can be computed by the use of equation 11.
𝑃𝑡𝑜𝑡𝑎𝑙 =𝑃𝐶𝑜𝑛𝑑 +𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 (1)
𝜂=
𝑃𝑟𝑎𝑡𝑒𝑑 −𝑃𝑇
𝑥100% (11)
𝑃𝑟𝑎𝑡𝑒𝑑

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 Proceedings of the 2024 Sustainable Research and Innovation Conference
JKUAT Main Campus, Kenya
2 - 3 October, 2024

With 𝑃𝑇 as the total power loss in all the switches, considering This implies that the 𝑅𝑑𝑠(𝑜𝑛) given in the datasheet at ambient
the conduction, switching losses of the converter switches, . temperature is used for the simulation and computation. Since
IV. SIMULATION RESULTS the temperature at the junction is not affected by power loss
within a short period. The waveform of the source voltage 𝑉𝑑𝑐
To analyze the influence of 𝐶𝑔𝑑 on 𝑉𝑔𝑠 transient response, the is shown in Figure 5. Additionally, the 𝑉𝑑𝑟𝑖𝑣𝑒 range, unlike in
drive voltage, 𝑉𝑑𝑟𝑖𝑣𝑒𝑟 which is a square wave with an amplitude Si MOSFET devices where it ranges from 0V to maximum
equal to 𝑉𝑑𝑑 and corresponding switching frequency 𝑓𝑠𝑤 and voltage, the SiC MOSFETs range below 0V, In this case, from
duty cycle, D is supplied at the gate. In the analysis of the SiC -4V up to 15V. The chosen SiC device can handle up to 19V
MOSFET and SiC Schottky diode in this work, the Wolfspeed as indicated in the data sheets. The gate drive voltage dictates
SiC MOSFET C3M0065090J with the datasheet parameters the 𝑉𝑔𝑠 waveform, shown in the Figure 6.
shown in Table I was used.
TABLE I
DATASHEET PARAMETERS Sic MOSFET CM30065090J
at (25°C)
Parameter Name Value
𝑇𝑗 25°C
𝑉𝑑𝑠 900V
𝐼𝑑𝑠 35A
𝑅𝑑𝑠(𝑜𝑛) 65mΩ
𝑉𝑡ℎ 1.8V, 2.1V, 3.5V
𝑅𝑔𝑎𝑡𝑒 3.5 Ω
𝑉𝑔𝑠 𝑜𝑝 -4V/15V Fig. 5 The waveforms of the input voltage 𝑉𝑑𝑐
𝑔𝑔𝑚 16S
The simulation results below show the ideal situations and do
not take into account the effects of the PCB parasitics. The
Wolfspeed SiC MOSFET CM30065090J and the Wolfspeed
Schottky diode C3D20065D were used for the simulation as
mentioned above. Table II and Table III show the parameters
which were used for simulations in this work.
TABLE II
DATASHEET PARAMETERS SCHOTTKY DIODE
C3D20065D at (25°C)
Parameter Name Value Fig. 6 𝑉𝑑𝑟𝑖𝑣𝑐 ranging from -4V to 15V
𝑉𝑟𝑝𝑚 650V Waveforms of the 𝑉𝑑𝑠 and 𝐼𝑑𝑠 are similarly shown in Figures
𝑉𝑓 1.8V 7-9. In these figures, the vertical axis denotes 𝑉𝑑𝑠 (unit is V) and
𝐼𝑓 7.5A the 𝐼𝑑𝑠 (Units is A), while the horizontal presents the number of
𝐼𝑟 12A sample times. A combination of turn-on events is shown in
Figure 7. A magnified version of the turn-on extracted from
Figure 7 is shown in Figure 8. Similarly, Figure 9 shows the
Since 𝑅𝑑𝑠(𝑜𝑛) is a temperature-dependent parameter, it is
SiC MOSFET turn-off events.
assumed that the SiC MOSFET junction temperature is
equivalent to ambient temperatures of 25°C throughout the
work. .
TABLE III
EXPERIMENTAL PARAMETERS USED AT ROOM
TEMPERATURE (25°C)
Parameter Name Value
𝑇𝑗 25°C
𝑉𝑑𝑐 400V Fig. 7 The turn-on and turn-off events in SiC MOSFET
𝐼𝑑𝑠 20A
𝑅𝑑𝑠(𝑜𝑛) 65mΩ
𝑉𝑡ℎ 1. 8V, 2.1V, 3.5V
𝑅𝑔𝑎𝑡𝑒 3.5 Ω
𝑉𝑑𝑟𝑖𝑣𝑒 -4V/15V
L 20mH

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 Proceedings of the 2024 Sustainable Research and Innovation Conference
JKUAT Main Campus, Kenya
2 - 3 October, 2024

Figure 12, is 12.2W. This is close to the computed conduction

loss by the use of equation 2, which gave it to be 11.69W.
Making the assumption that this is a non-isolated DC-DC
converter, and neglecting the inductor loss, the computed
efficiency using equation 11 is 96.61% for a 3kW converter.
Which is 2.9% higher than using the Si MOSFETs with Si
diode.

Fig. 8 SiC MOSFETs Turn-on waveforms waveform

Fig. 9 SiC MOSFETs turn-off waveforms

Fig. 12 Conduction power loss during the turn-on
It is worth noting that the waveform in Figure 11 shows the
turn-on power loss curve extracted from Figure 10, with the
rectangular part in green marked as A, and magnified. It's noted V. CONCLUSION
that the extracted area under the curve represents the total power
loss during the turn-on process. Additionally, the 𝑉𝑔𝑠 curve Through the analysis of the basic switching transients of SiC
shows that the drive voltage is less than zero (-4) at the MOSFETs, there are typically different operation regions of a
beginning as expected, before the turn-on. After the turn-on, it switch. In this paper, the power losses of a power inverter based
increases till reaching the Miller plateau voltage. Where this on SiC MOSFETs are analyzed with consideration of the
process was elucidated in Section II in detail. switching frequency. The finding shows that power losses
increase linearly with an increase in switching frequency. The
simulations for the power loss were carried out with the
LTspice model. The turn-on switching loss in SiC MOSFETs is
usually higher than the turn-off loss. Additionally, the turn-on
dv/dt is higher than the turn-off dv/dt. The quantified efficiency
was obtained as 96.91%.

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