Chapter 2: The Microprocessor and its Architecture
Introduction
• This chapter presents the microprocessor as a
programmable device by first looking at its
internal programming model and then how its
memory space is addressed.
• The architecture of Intel microprocessors is
presented, as are the ways that the family
members address the memory system.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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Chapter Objectives
Upon completion of this chapter, you will be able to:
• Describe function and purpose of each
program-visible register in the 8086-Core2
microprocessors, including 64-bit extensions.
• Detail the flag register and the purpose of
each flag bit.
• Describe how memory is accessed using real
mode memory-addressing techniques.
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Chapter Objectives (cont.)
Upon completion of this chapter, you will be able to:
• Describe how memory is accessed using
protected mode memory-addressing
techniques.
• Describe how memory is accessed using the
64-bit flat memory model.
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2–1 INTERNAL MICROPROCESSOR
ARCHITECTURE
• Before a program is written or instruction
investigated, internal configuration of the
microprocessor must be known.
• In a multiple core microprocessor each core
contains the same programming model.
• Each core runs a separate task or thread
simultaneously.
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A thread consists of a program counter, a register set, and a
stack space.
A task shares with peer threads its code section, data section,
and operating system resources
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The Programming Model
• 8086 through Core2 considered program
visible.
– registers are used during programming and are
specified by the instructions
• Other registers considered to be program
invisible.
– not addressable directly during applications
programming
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• 8086 through the 80286 are fully upward-
compatible to the 80386 through Core2.
• Figure 2–1 illustrates the programming model
8086 through Core2 microprocessor.
– including the 64-bit extensions
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Figure 2–1 The programming model of the 8086 through the
Core2 microprocessor including the 64-bit extensions.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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Multipurpose Registers
• RAX - a 64-bit register (RAX), a 32-bit register
(accumulator) (EAX), a 16-bit register (AX),
or as either of two 8-bit registers (AH and AL).
• The accumulator is used for instructions such
as multiplication, division, and some of the
adjustment instructions.
• Intel plans to expand the address bus to 52
bits to address 4P (252~1015 =peta) bytes of
memory.
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Address Space (Main Memory: RAM)
• Address bus:16 bit →Address Space:64 KBytes
• Address bus:20 bit →Address Space:1 MBytes
Address bus:32 bit →Address Space:4 GBytes
Address bus:34 bit →Address Space:16GBytes
• Address bus:36 bit →Address Space:64GBytes
• Address bus:38 bit →Address
Space:256GBytes
• Address bus:52 bit →Address Space:1015
Bytes
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• RBX, addressable as RBX, EBX, BX, BH, BL.
– BX register (base index) sometimes holds offset
address of a location in the memory system in all
versions of the microprocessor
• RCX, as RCX, ECX, CX, CH, or CL.
– a (count) general-purpose register that also holds
the count for various instructions
• RDX, as RDX, EDX, DX, DH, or DL.
– a (data) general-purpose register
– holds a part of the result from a multiplication
or part of dividend before a division
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• RBP, as RBP, EBP, or BP.
– points to a memory (base pointer) location
for memory data transfers
• RDI addressable as RDI, EDI, or DI.
– often addresses (destination index) string
destination data for the string instructions
• RSI used as RSI, ESI, or SI.
– the (source index) register addresses source
string data for the string instructions
– like RDI, RSI also functions as a general-
purpose register
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Special-Purpose Registers
• Include RIP, RSP, and RFLAGS
– segment registers include CS, DS, ES, SS, FS,
and GS
• RIP addresses the next instruction in a section
of memory.
– defined as (instruction pointer) a code segment
• RSP addresses an area of memory called
the stack.
– the (stack pointer) stores data through this
pointer
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• RFLAGS Indicating Microprocessor
State(reporting condition Flags:Outcome of
operation) & Controlling Operation(Control
CPU behaviour)
• 8086 FLAGS(16-bit): CF, ZF, SF, OF, etc..
• Flags are upward-compatible from the
8086/8088 through Core2 .
• The rightmost five(CF,PF,AF,ZF,SF) and the
overflow flag are changed by most arithmetic
and logic operations.
– although data transfers do not affect them
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Flags never change for any data transfer or program control operation
Examples:
MOV AX, BX ; No flags changed
ADD AX, CX ; CF, ZF, SF, OF updated
JMP Next ; No flags changed
CMP AX, DX ; Flags updated (like SUB)
JE Equal ; Checks ZF (but doesn’t modify flags)
• Some of the flags are also used to control features found in the
microprocessor, i.e, directly control the Mp such as: IF, DF, etc.
• Example:
CLI ; Clear IF (disable interrupts)
MOV [AX], BX ; Critical operation (won’t be interrupted)
STI ; Set IF (re-enable interrupts)
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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• Flag bits, with a brief description of function.
• C (carry) holds the carry after addition or
borrow after subtraction.
– also indicates error conditions
• P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd
parity; logic 1 for even parity.
– if a number contains three binary one bits, it has
odd parity
– if a number contains no one bits, it has even
parity
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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List of Each Flag bit, with a brief
description of function.
• C (carry) holds the carry after addition or
borrow after subtraction.
– also indicates error conditions
• P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd
parity; logic 1 for even parity.
– if a number contains three binary one bits, it has
odd parity; If a number contains no one bits, it
has even parity
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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• A (auxiliary carry) holds the carry (half-carry)
after addition or the borrow after subtraction
between bit positions 3 and 4 of the result.
• Z (zero) shows that the result of an arithmetic
or logic operation is zero.
• S (sign) flag holds the arithmetic sign of the
result after an arithmetic or logic instruction
executes.
• T (trap) The trap flag enables trapping
through an on-chip debugging feature.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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• I (interrupt) controls operation of the INTR
(interrupt request) input pin.
• D (direction) selects increment or decrement
mode for the DI and/or SI registers.
• O (overflow) occurs when signed numbers
are added or subtracted.
– an overflow indicates the result has exceeded
the capacity of the machine
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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Segment Registers
• Generate memory addresses when combined
with other registers in the microprocessor.
• Four or six segment registers in various
versions of the microprocessor.
• Following is a list of each segment register,
along with its function in the system.
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• CS (code) segment holds code (programs
and procedures) used by the microprocessor.
• DS (data) contains most data used by a
program.
– Data are accessed by an offset address or
contents of other registers that hold the offset
address
• ES (extra) an additional data segment used
by some instructions to hold destination data.
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• SS (stack) defines the area of memory used
for the stack.
– stack entry point is determined by the stack
segment and stack pointer registers
– the BP register also addresses data within
the stack segment
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Segments and Offsets
• All real mode memory addresses must consist
of a segment address plus an offset address.
– segment address defines the beginning address
of any 64K-byte memory segment
– offset address selects any location within the
64K byte memory segment
• Figure 2–3 shows how the segment plus
offset addressing scheme selects a memory
location.
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Figure 2–3 The real mode memory-addressing scheme, using a
segment address plus an offset.
– this shows a memory
segment beginning at
10000H, ending at
location IFFFFH
• 64K bytes in length
– also shows how an
offset address, called a
displacement, of
F000H selects location
1F000H in the memory
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• Once the beginning address is known, the
ending address is found by adding FFFFH.
– because a real mode segment of memory is 64K
in length
• The offset address is always added to the
segment starting address to locate the data.
• Segment and offset address is sometimes
written as 1000:2000.
– a segment address of 1000H; an offset of 2000H
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Default Segment and Offset
Registers
• The microprocessor has rules that apply to
segments whenever memory is addressed.
– these define the segment and offset register
combination
• The code segment register defines the start
of the code segment.
• The instruction pointer locates the next
instruction within the code segment.
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• Another of the default combinations is the
stack.
– stack data are referenced through the stack
segment at the memory location addressed by
either the stack pointer (SP/ESP) or the pointer
(BP/EBP)
• Figure 2–4 shows a system that contains four
memory segments.
– a memory segment can touch or overlap if 64K
bytes of memory are not required for a segment
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Figure 2–4 A memory system showing the placement of four
memory segments.
– think of segments as
Windows that can be
moved over any area
of memory to access
data or code
– a program can have
more than four or six
segments,
• but only access four or
six segments at a time
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• Because memory is addressed within a
segment by an offset address, the memory
segment can be moved to any place in the
memory system without changing any of the
offset addresses.
• Only the contents of the segment register
must be changed to address the program
in the new area of memory.
• Windows programs are written assuming that
the first 2G of memory are available for code
and data.
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SUMMARY
• The programming model of the 8086
through 80286 contains 8- and 16-bit
registers.
• The programming model of the 80386 and
above contains 8-, 16-, and 32-bit extended
registers as well as two additional 16-bit
segment registers: FS and GS.
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SUMMARY (cont.)
• 8-bit registers are AH, AL, BH, BL, CH, CL,
DH, and DL.
• 16-bit registers are AX, BX, CX, DX, SP, BP,
DI, and SI.
• The segment registers are CS, DS, ES, SS,
FS, and GS.
• 32-bit extended registers are EAX, EBX,
ECX, EDX, ESP, EBP, EDI, and ESI.
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SUMMARY (cont.)
• The 64-bit registers in a Pentium 4 with 64-
bit extensions are RAX, RBX, RCX, RDX,
RSP, RBP, RDI, RSI, and R8 through R15.
• In addition, the microprocessor contains an
instruction pointer (IP/EIP/RIP) and flag
register (FLAGS, EFLAGS, or RFLAGS).
• All real mode memory addresses are a
combination of a segment address plus an
offset address.
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
SUMMARY (cont.)
• The starting location of a segment is
defined by the 16-bit number in the
segment register that is appended with a
hexadecimal zero at its rightmost end.
• The offset address is a 16-bit number
added to the 20-bit segment address to
form the real mode memory address.
• All instructions (code) are accessed by the
combination of CS (segment address) plus
IP or EIP (offset address).
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
SUMMARY (cont.)
• Data are normally referenced through a
combination of the DS (data segment) and
either an offset address or the contents of a
register that contains the offset address.
• The 8086-Core2 use BX, DI, and SI as
default offset registers for data if 16-bit
registers are selected.
• The 80386 and above can use the 32-bit
registers EAX, EBX, ECX, EDX, EDI, and
ESI as default offset registers for data.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
