Supertex inc.

HV9803B

LED Driver IC
with Average-Mode Constant Current Control

Features General Description

►► Fast average current control The HV9803B is an open loop average-mode current control
LED driver IC operating in a constant off-time mode. The IC
►► Correction for propagation delay and offset voltage
features ±2% current accuracy, tight line and load regulation
►► Fixed off-time switching mode of the LED current without any need for loop compensation
►► Linear dimming input or high-side current sensing. Its auto-zero circuit cancels the
►► PWM dimming input effect of both the input offset voltage and the propagation
delay in the current sense comparator.
►► Output short circuit protection with programmable
skip mode
The HV9803B can be powered from a 7.0 to 16V supply. The
►► Input under-voltage shutdown IC features fast PWM dimming response. The linear dimming
input LD can accept a reference voltage from 0 to 3.0V.
Applications
The IC is equipped with a current limit comparator for
►► Backlighting of LCD Panels
hiccup-mode output short circuit protection. It also features a
►► General Lighting programmable input under-voltage shutdown.

Typical Application Circuit

+VIN

7.0~16V CIN
CDD D1
L1

R1
VDD
DIM PWMD GATE Q1

HV9803B
REF LD CS

RCS
UVLO RT
CSKIP
RT
GND
R2

Doc.# DSFP-HV9803B
B032114
Supertex inc.
www.supertex.com
 HV9803B
Ordering Information Pin Configuration
Part Number Package Option Packing
CS 1 8 LD
HV9803BLG-G 8-Lead SOIC 2500/Reel VDD 2 7 UVLO
-G denotes a lead (Pb)-free / RoHS compliant package
GND 3 6 PWMD

GATE 4 5 RT
Absolute Maximum Ratings*
8-Lead SOIC
Parameter Value
VDD, GATE, CS -0.3V to +17V
Product Marking
LD, RT, PWMD, UVLO -0.3V to +6.0V
YWW
Y = Year Sealed
Operating temperature range -40°C to +125°C
WW = Week Sealed
Storage temperature range -65°C to +150°C 9803B L = Lot Number
LLLL = “Green” Packaging
Power dissipation @ 25°C 650mW
Package may or may not include the following marks: Si or
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional 8-Lead SOIC
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Typical Thermal Resistance
Package θja
8-Lead SOIC 101°C/W

Electrical Characteristics
(The * denotes specifications which apply over the full operating ambient temperature range of -40°C<TA<125°C. Otherwise specifications are at TA =
25°C. VDD = 12V, PWMD = 5.0V, unless otherwise noted)

Sym Description Min Typ Max Units Conditions

Input
VDD Input DC supply voltage range * - - 16 V DC input voltage
IDD Quiescent VDD supply current * - 1.5 2.5 mA VCS = 0V
VDD Under-Voltage Lockout
VDD under-voltage lockout
VDD(UV) * 6.45 6.70 6.95 V VDD rising
threshold
VDD under-voltage lockout
ΔVDD(UV) - - 500 - mV VDD falling
hysteresis
PWM Dimming
VEN(LO) PWMD input low voltage * - - 1.0 V ---
VEN(HI) PWMD input high voltage * 2.6 - - V ---
Internal pull-down resistance at
REN - 50 100 150 kΩ ---
PWMD

Doc.# DSFP-HV9803B Supertex inc.

B032114 www.supertex.com
2
 HV9803B
Electrical Characteristics (cont.)
(The * denotes specifications which apply over the full operating ambient temperature range of -40°C<TA<125°C. Otherwise specifications are at TA =
25°C. VDD = 12V, PWMD = 5.0V, unless otherwise noted)

Sym Description Min Typ Max Units Conditions

Current Sense Comparator
VLD External reference voltage - 0 - 3.0 V ---
* 284 - 296 VLD = 0.6V
VCS CS reference voltage mV
* 866 - 902 VLD = 1.8V
AV(LD) LD to CS voltage ratio - - 0.495 - - ---
TBLANK Current sense blanking interval * 150 - 280 ns ---
TON(MIN) Minimum on-time - - - 760 ns VCS = 0.5VLD +30mV
Reduction in output LED
DMAX Maximum steady-state duty cycle * 85 - - % current may occur beyond
this duty cycle
Short Circuit Protection
VLIM Internal current reference - 1.57 - 1.93 V ---
TDELAY Current limit delay CS-to-GATE - - - 150 ns VCS = VLIM +30mV
UVLO skip timer reset switch
RUVLO(R) - - - 500 Ω ---
resistance
VUVLO(R) UVLO skip timer reset voltage - 200 - 300 mV ---
TON(MIN) Minimum on-time (short circuit) - - - 430 ns VCS = VLIM +30mV
TOFF Timer
6.7 9.0 11.3 μs RT = 250kΩ
TOFF Off time -
0.8 1.0 1.2 μs RT = 25kΩ
IRT(LIM) RT over-current threshold - - 2.8 - mA ---
GATE Driver
ISOURCE Gate sourcing current - 0.165 - - A VGATE = 0V
ISINK Gate sinking current - 0.165 - - A VGATE = VDD
tRISE GATE output rise time - - 30 50 ns CGATE = 500pF
tFALL GATE output fall time - - 30 50 ns CGATE = 500pF
UVLO
UVLO Under-voltage threshold voltage * 1.17 - 1.29 V VUVLO rising
Under-voltage threshold voltage
ΔUVLO - - 150 - mV VUVLO falling
hysteresis
# Guaranteed by design
* Limits over temperature are guaranteed by design and characterization

Doc.# DSFP-HV9803B Supertex inc.

B032114 www.supertex.com
3
 HV9803B
Functional Block Diagram
i
+
-
IRT(LIM)
UVLO2
VDD + Reset
UVLO1 - -
+
VLD
UVLO
250mV
Auto-REF
LD xAV(LD)
POR
10mV SKIP

Average-Mode
L/E Control Logic
CS Blanking IN
GATE
OUT

PWMD
+ R Q
VLIM -
S Q
GND
SKIP Q S

TOFF
R Timer Current
Reset Mirror
RT
HV9803B i

Functional Description
Peak-current control of a buck converter is the most The HV9803B employs Supertex’ patented control scheme,
economical and simple way to regulate its output current. achieving fast and very accurate control of average current
However, it suffers accuracy and regulation problems that in the buck inductor through sensing the switch current only.
arise from the peak-to-average current error, contributed No compensation of the current control loop is required.
to by the current ripple in the output inductor and the The inductor current ripple amplitude does not affect this
propagation delay in the current sense comparator. The full control scheme significantly, and therefore, the LED current
inductor current signal is unavailable for direct sensing at the is independent of the variation in inductance, switching
ground potential in a buck converter when the control switch frequency or output voltage. Constant off-time control of the
is referenced to the same ground potential. While it is very buck converter is used for stability and to improve the LED
simple to detect the peak current in the switch, controlling current regulation over a wide range of input voltages. The
the average inductor current is usually implemented by IC features excellent PWM dimming response.
level-translating the current sense signal from the positive
input supply rail. While this is practical for relatively low input
voltage, this type of average-current control may become
excessively complex and expensive in the case of input
voltage in excess of 100V.

Doc.# DSFP-HV9803B Supertex inc.

B032114 www.supertex.com
4
 HV9803B
OFF Timer Short Circuit Protection
In the HV9803B, the timing resistor connected to RT The HV9803B is equipped with a protection comparator
determines the off-time of the gate driver, and it must be having a CS threshold VLIM. When this second threshold
wired to GND. The equation governing the off-time of the is triggered, the GATE output shuts off for the duration of
GATE output is given by: a restart delay, determined by the RC constant at UVLO.
The capacitor CSKIP is discharged below 200mV. A restart
TOFF = RT • 40pF delay due to charging CSKIP to the UVLO start threshold is
calculated as:
The RT input is protected from short circuit. Over-current k • VIN - 0.30V
condition at RT inhibits the IC. TSKIP = k • R1 • CSKIP • ln
k • VIN - 1.17V
Current Sense Comparator and Timer Circuits where k = R2 / (R1+R2).
The function of the HV9803B’s current sense comparator is
similar to that of a peak current controller. However, the GATE Under-Voltage Shutdown
pulse is not terminated immediately as the LD threshold is Under-voltage comparator input is provided to disable the
met. The GATE turn off in the nth cycle is delayed by a time IC, when the UVLO input is below a threshold. Hysteresis is
T2,n determined by a timer circuit as follows: provided to avoid oscillation.
1
T2,n = • (T
1,n
+ T1,n-1) Failure Modes and Effects Analysis (FMEA)
2
The HV9803B is designed to withstand short circuit between
where T1,n and T1,n-1 are the times to the LD threshold in any its adjacent pins without damage. The following table
two consequent switching cycles. This iterative control law is describes the effect of such incidental short circuit conditions.
needed for damping sub-harmonic oscillation.

Note, that the above control law is only valid up to a maximum Short Circuit
switching duty cycle Dmax= 0.85. Exceeding Dmax will cause Effect
Mode
reduction in the LED current.
The IC triggers the short circuit
CS to VDD protection and operates in the auto-
Propagation delay in the current sense comparator is one
restart mode continuously.
of the most significant contributors to the LED current error.
It must be noted that the control scheme described above Short circuit across the 12V should
does not improve this deficiency of the peak-current control VDD to GND cause the external bias supply over-
scheme by itself. Moreover, it samples the propagation delay current protection.
during T1 and replicates it during T2, essentially doubling the Should cause the external bias supply
error introduced by this delay. In order to eliminate this error, GND to GATE over-current protection. The power
the reference voltage is corrected by an auto-zero circuit. MOSFET Q1 is off.
In essence, the HV9803B samples its CS signal when the
current sense comparator triggers, detects the difference Case 1 – PWMD = Lo: The RT pin
between the sampled CS level and the reference input of sources its maximum current.
the current sense comparator. The resulting difference GATE = 0V, and Q1 is off.
is subtracted from the reference level to generate a new RT to PWMD
reference in the next switching cycle. Case 2 – PWMD=Hi: The RT pin is
pulled up, shutting off the timer.
GATE is off.
GATE Output
The GATE output of the HV9803B is used to drive an This will overdrive the under-voltage
external MOSFET. It is recommended that the gate charge PWMD to threshold. However, since VIN UV
QG of the external MOSFET be less than 25nC for switching UVLO condition is harmless to the IC, there is
frequencies ≤100kHz and less than 15nC for switching no effect.
frequencies >100kHz.
LD overdrives the UVLO. If LD is lower
UVLO to LD than the UVLO threshold, the IC shuts
The resulting LED current is calculated from the equation:
off. No effect otherwise.

0.495 • VLD - 7mV

ILED =
RCS

Doc.# DSFP-HV9803B Supertex inc.

B032114 www.supertex.com
5
 HV9803B
Pin Description (8-Lead SOIC)
Pin Name Description
This pin is the current sense pin used to detect the MOSFET source current by means of an external
1 CS
sense resistor.
This is the power supply input for the GATE output and input of the low-voltage regulator powering the
2 VDD
internal logic. It must be bypassed with a low ESR capacitor to GND (at least 0.1μF).
Ground return for all internal circuitry. This pin must be electrically connected to the ground of the
3 GND
power train.

4 GATE This pin is the output gate driver for an external N-channel power MOSFET.

5 RT A resistor connected between RT and GND programs the GATE off-time.

This is the PWM dimming input of the IC. When this pin is pulled to GND, the gate driver is turned off.
6 PWMD
When the pin is pulled high, the gate driver operates normally.
This pin is the under-voltage comparator input. It is also used to form a short-circuit protection skip
7 UVLO
delay.

8 LD This pin is the reference voltage input for programming the LED current.

Doc.# DSFP-HV9803B Supertex inc.

B032114 www.supertex.com
6
 HV9803B
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch

D θ1

Note 1
(Index Area
D/2 x E1/2)
E1 E Gauge
L2
Plane

L Seating
1 θ Plane
L1

Top View View B View B

Note 1
A h
h
A A2
Seating
Plane
A1 e b

Side View A
View A-A

Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.

Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1

MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 0.25 0.40 0 O
5O
Dimension 1.27 1.04 0.25
NOM - - - - 4.90 6.00 3.90 - - - -
(mm) BSC REF BSC
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 O
15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Doc.# DSFP-HV9803B Tel: 408-222-8888
B032114 7 www.supertex.com