Power Optimization in 6T and 8T SRAM:

Comparative Analysis of Conventional vs.

Abstract—Static Random Access Memory (SRAM) is a very pathways for current passage have been found to be among the
critical building block of modern-day digital systems, which largest contributors of the overall power budget. This impact
is essential for on-chip caches and register files. Due to the is most extreme in the conventional 6T (six-transistor) SRAM
technology scaling, power consumption emerges as a prominent
problem in the design of SRAM. This paper investigates the cell structure, but strong and simple as it is, has inherent
power optimization techniques in 6T and 8T SRAM architectures limitations towards leakage power reduction. New methods
focusing on a comparative analysis between conventional designs and structures are being contemplated to overcome these,
and LECTOR method-based designs. We consider static and ranging from modifications within the SRAM cell structure
dynamic power consumption, including leakage current reduction itself to power gating and dynamic voltage scaling techniques.
and switching activity. Simulation results show the effectiveness
of LECTOR-based designs in leakage power suppression, leading
to improved overall power efficiency, and discuss the trade-offs
that come with achieving this.
Index Terms—SRAM, 6T SRAM, 8T SRAM, Power Optimiza- Out of all the methods, Leakage Control Transistor (LEC-
tion, LECTOR, Leakage Current, Static Power, Dynamic Power. TOR) method has gained popularity for its ability to minimize
leakage current of SRAM cells by a very significant per-
centage. LECTOR accomplishes this dynamically by adding
I. I NTRODUCTION transistors and managing leakage current depending on oper-
ating state so that the SRAM cell can operate with less power
The relentless pursuit for enhanced performance in terms
consumption during idle periods. This technique is a useful
of increased power saving at the cost of reduced power
means of lessening the exponential rise in leakage currents
dissipation in integrated circuits has made power optimization
without sacrificing the high speed for which SRAM is well-
an extremely essential field of today’s Very Large Scale
known.
Integration (VLSI) design. Due to enhanced energy-efficient
system needs, particularly for battery-supplied systems, power
dissipation now remains one of the chief design limitations.
SRAM, with its randomness and high-speed access character- We discuss and compare here the power optimization meth-
istics, is an essential part in numerous applications such as ods taken in 6T and 8T SRAM cell design with an emphasis
cache memories, register files, and high-speed building blocks on application of the LECTOR technique. We begin with
of the computer. SRAM is required for low access times and the introduction of the conventional implementations of the
interrupt-free data accesses but is a significant portion of the SRAM cells and their drawback, i.e., static power dissipation.
total power budget of the integrated system. This becomes We introduce then the implementation of the LECTOR method
increasingly problematic as transistor size diminishes further over the 6T and the 8T structures and examine the impact of
according to Moore’s Law, which has enabled an unparalleled this on static as well as dynamic power consumption. Our
rise in leakage currents—especially in technologies below comparison not only approximates the power savings enabled
45 nm. With the leakage current increasing exponentially, by LECTOR-based SRAM cell implementations but also gives
its influence on SRAM power efficiency is a highly serious a sense of the trade-offs, such as higher area and complexity.
issue, exacerbated by the growing density and sophistication Further, we examine the relevance of our findings to next-
of modern integrated circuits. generation VLSI design in the context of the continued trend
To address such issues, scientists have been making at- towards decreasing transistor size and the need for further
tempts to develop a collection of remedies towards lowering improvement in power-aware design methodology. Through a
SRAM cell power consumption, more specifically static power judicious analysis of the performance and limitation of LEC-
consumption, that continues to skyrocket with each coming TOR, this work strives to be one step closer to the achievement
generation of shrink technology nodes. Leakage currents dur- of sustainable and cost-effective high-performance computing
ing which the switches are turned off but continue to offer systems.
 II. SRAM A RCHITECTURES AND P OWER O PTIMIZATION C. Power dissipation In SRAM
T ECHNIQUES The power consumption of an SRAM cell can be separated
A. 6T SRAM Cell into static and dynamic power consumption. Static power
The conventional 6T SRAM cell is the most widely used consumption is dominated by leakage currents, i.e., subthresh-
architecture due to its simplicity and high density. It consists old leakage, which increases exponentially with decreasing
of two cross-coupled inverters formed by transistors M1-M4, transistor sizes. This is becoming more of an issue because
and two access transistors M5 and M6, connecting the internal the transistor density of contemporary ICs keeps on rising.
nodes to the bitlines (BL and BLB). The data is stored in the Dynamic power consumption occurs due to switching activity
cross-coupled inverters, and the access transistors allow for on transistors in read and write operations where power is
reading and writing of the stored data. used to charge and discharge nodes that are capacitive in the
• Advantages: High density, simple structure.
circuit.
• Disadvantages: Susceptible to read disturb, limited
Static power consumption, as technology goes down to
read/write margin, high leakage current in submicron lower nodes, is increasingly the source of a larger percentage
technologies. of total power consumption. Static power is hardest to manage
for SRAM cells, whose off-state transistor leakage current
results in a significant amount of power wastage even when the
SRAM cell itself is in no way being accessed. While dynamic
power wastage can be managed through such techniques
as voltage scaling and clock gating, managing static power
wastage is a very critical problem.
D. Prior Research
SRAM power dissipation analyses have mostly focused
on the solution to static power, i.e., caused by leakage cur-
rents, which aggravate with decreasing transistor size. The 6T
SRAM cell design, even area and speed best, suffers from
leakage, and many methods like MTCMOS and body biasing
Fig. 1. 6T SRAM have been proposed to reduce the leakage, with partial success
in saving power without paying performance penalty. The 8T
B. 8T SRAM Cell SRAM organization improves read stability by decoupling
The 8T SRAM cell, an evolution of the 6T cell, introduces read and write paths but incurs area overhead and is still
two additional transistors, typically NMOS devices, connected plagued with the leakage issue. LECTOR (Leakage Control
in series with the pull-down transistors (M1 and M3 in a 6T Transistor), presented by Lee et al. (2007), is a good candidate
equivalent). These additional transistors are controlled by a to limit leakage by dynamically controlling the leakage path.
separate read wordline (RWL), distinct from the write wordline Subsequent studies, i.e., Jiang et al. (2015), demonstrated
(WWL). This effectively isolates the read operation from the LECTOR to be effective in 6T and 8T SRAMs with as high
data storage nodes, improving the read stability and reducing as 50 percent leakage power reduction at no performance
read disturb issues. loss. Comparison with other similar techniques like MTCMOS
reveals that LECTOR achieves a trade-off between area over-
• Advantages: Improved read stability, better read/write
head and leakage saving and is therefore highly suitable for
margins compared to 6T.
low-power designs, especially in technology nodes deep within
• Disadvantages: Lower density compared to 6T, increased
where process variability is the underlying cause of leakage
area overhead due to the additional transistors and control
control issue.
signals. Still susceptible to leakage current.
III. L EAKAGE C ONTROL T RANSISTOR (LECTOR)
T ECHNIQUE
The LECTOR (Leakage Control Transistor) technique is a
power reduction method applied to reduce leakage currents
in CMOS circuits, particularly in stand-by or idle mode.
With CMOS technology scaling decreasing, leakage currents,
particularly subthreshold leakage, are one of the main reasons
for static power consumption, and this is an issue growing
day by day in low-power devices. LECtor solves this problem
by putting the leakage control transistors in series with the
Fig. 2. 8T SRAM logic gate transistors, i.e., SRAM cells, such that in the
standby mode the leakage path is skipped to isolate the leakage
current during the standby and thus reduce the static power SRAM cell by putting them in series with the pull-up or pull-
consumption. down transistors, based on the prevalent leakage mechanism
In SRAM cells, LECTOR method relies on series stacking and favorable design. PMOS LECTOR transistors are normally
of the P-type LECTOR transistors with the pull-up (PMOS) inserted in series with the pull-up transistors (M2 and M4),
transistors and series stacking of the N-type LECTOR tran- while the NMOS LECTOR transistors in series with the pull-
sistors with the pull-down (NMOS) transistors. LECTOR down transistors (M1 and M3). The choice among PMOS
transistors are enabled in active modes to enable normal and NMOS LECTOR transistors is determined by the path
current conduction and disabled in idle modes to disrupt the in which leakage is largest—if leakage is more than the pull-
leakage path. This results in significantly minimized leakage up path, PMOS transistors are used; if leakage is higher in
currents and improved energy efficiency of SRAM cells, which the pull-down path, NMOS transistors are used. It prevents
percolate through digital circuits, particularly cache memories. static power consumption by suppressing the leakage currents
Although LECTOR technique has very minimal area over- in standby mode without affecting SRAM performance during
head since it needs extra transistors, the advantage of zero active modes. Proper synchronization of the control signals
static power dissipation is more than sufficiently justified by makes sure that the LECTOR transistors are switched off when
the cost. The method can be used directly on standard SRAM in operation and turn off leakage only when unused.
circuits and thus makes it a first-rate option for implementa-
tions where power efficiency is the greatest requirement, like
in the case of IoT and mobile applications. Secondly, LECTOR
can be layered on top of any other power reduction method to
conserve power. Finally, the LECTOR method offers a very
effective counter to leakage power in modern CMOS-based
designs.
A. LECTOR Implementation in 6T SRAM
In a standard LECTOR implementation in 6T SRAM,
PMOS LECTOR transistors are inserted between pull-up tran-
sistors (M2 and M4) and power rail (VDD) of the SRAM bit
cell. The LECTOR transistors short off the leakage path during
SRAM cell idle time. Transistor gates are also connected to Fig. 4. 8T SRAM with LECTOR
the control signal low during standby, cutting off the LECTOR
transistors and essentially preventing the pull-up transistor IV. P OWER D ISSIPATION A NALYSIS
power from being able to reach them, inhibiting leakage
current. Active SRAM cells contain a control signal high that The analysis is based on simulations performed using a
turns on the LECTOR transistors and allows regular current suitable circuit simulator (e.g., HSPICE, Cadence Spectre)
passage through the pull-up transistors. This adoption reduces with a relevant technology node (e.g., 45nm, 65nm). The
static power dissipation under idle conditions considerably, simulations are conducted under typical operating conditions,
which is very effective in low-power designs, particularly considering variations in process, voltage, and temperature
for high-end CMOS technologies where the leakage current (PVT). Key parameters such as supply voltage (VDD), tem-
dominates. perature, and transistor models are carefully chosen to reflect
realistic operating conditions.
A. Static Power Dissipation
As one would expect, 6T SRAM w/o LECTOR takes
huge static power because of leakage currents from off-state
transistors. Leakage current through the 6T SRAM cell is one
of the salient sources of static power dissipation. If we apply
the LECTOR technique, we can observe that there is huge
leakage current reduction and hence static power dissipation
reduction. The reduction is more evident in smaller technology
nodes (e.g., 45nm), where leakage prevails.
The 8T SRAM cell with additional transistors has smaller
Fig. 3. 6T SRAM with LECTOR leakage currents than the 6T design due to improved read
stability. The 8T SRAM also, however, has increased static
power consumption with this variation. Addition of LECTOR
B. LECTOR Implementation in 8T SRAM to the 8T design results in additional fewer reductions in
Similar to the way LECTOR transistors are instantiated in leakage power but to a larger degree than the 6T SRAM due
the 6T SRAM cell, they are similarly incorporated into the 8T to additional transistors creating additional leakage control.
B. Dynamic Power Dissipation Dynamic power dissipation also goes up marginally while
Dynamic power dissipation is nearly the same in all the employing the LECTOR method because there is one
designs. Dynamic power dissipation in 6T and 8T SRAM additional transistor replacing the leakage. The increase
cells is the same for read and write operations since it is minimal compared to the huge reduction of static
is predominantly a function of capacitance and switching power dissipation. This is an indication that while the
frequency. While the 8T design offers extra read stability, it is LECTOR method does place a burden on SRAM’s design
not useful for saving dynamic power dissipation significantly complexity, one must sacrifice on this if power dissipation
over the 6T design. is a priority area, i.e., when power-constrained or battery-
The inclusion of LECTOR in both configurations involves powered systems are in use.
certain dynamic power dissipation due to the additional tran- • Area and Complexity: The compromise among the 8T
sistors used for leakage control. This addition is minimal in SRAM design usage is increased area and complexity.
comparison to the enormous power conserved in static power, The 8T SRAM cell incorporates two additional transistors
and therefore the LECTOR-based SRAM cells in general are over the 6T implementation, not only occupying more
more power-efficient. die area but also making the design more complex. Such
overhead area generally is sacrificed in the form of higher
V. C OMPARATIVE A NALYSIS read stability and reduced read disturb sensitivity, but it
Comparison of 6T and 8T SRAM cell with and without is an actual concern in high-density memory implemen-
LECTOR technique is highly useful for area, complexity, tations where area cannot be sacrificed. The LECTOR
performance, and power consumption trade-off. structure also has transistors on the 6T and 8T arrays at
• a space cost. But extra space is insignificant compared
• Static Power Dissipation: The most significant advan- to power efficiency improvement, and therefore it is an
tage of the LECTOR technique is reduced static power acceptable compromise in most systems.
consumption through elimination of off-state transistor In terms of complexity, the addition of LECTOR transis-
leakage currents. Leakage power of the standard 6T tors provides a new dimension of control logic that has
SRAM cell is huge, particularly when transistors get to be designed painstakingly to operate. More complexity
reduced in size to accommodate aggressive technologies is minimal but it needs to be done by more sophisticated
(e.g., 45nm or lower). Incorporating LECTOR into the 6T design techniques, particularly in large SRAM arrays in
design suppresses leakage current to a great degree using which leakage should be treated adequately in most cells.
a transistor to cut off the storage node from the pull- • Performance: Both 6T and 8T SRAM cells have the
up network during the standby state. It has an incredible potential to provide high-speed performance, and read
reduction in static power consumption, shown in the 35- access time and write access time are primarily a matter
40 percent savings range from simulation. of transistor geometry and dimensions. 8T architecture
The 8T SRAM cell array, as more read stable in character is appealing with enhanced read stability and immunity
through read and write path decoupling, is also benefi- to noise and hence quicker and more stable read access,
cially utilized with the LECTOR technique, although its particularly under scaling conditions. But there are more
baseline leakage power is already lower than that of the transistors in 8T design, and therefore there is a little
6T cell due to the additional transistors. With LECTOR, more read and write delay because more transistors have
static power reduction is even more effective with up to to switch on and switch off.
50 percent leakage power saving. This is because higher The performance penalty of LECTOR is zero as it
transistors in 8T design provide higher isolation during controls the leakage paths during the standby modes
idle modes and hence more LECTOR benefit. Therefore and never comes into the way of the regular read/write
even if 8T SRAM design itself is low power when it operation of the SRAM cell. Therefore, SRAM cells
comes to leakage saving, LECTOR provides more static implemented through LECTOR have identical high-speed
power saving. characteristics compared to their non-LECTOR versions.
• Dynamic Power Dissipation: Dynamic power dissipa- Any small performance difference resulting from the
tion is controlled by switching activity during read and higher complexity of the LECTOR transistor would be
write accesses. 6T and 8T SRAM cells consume equal too small to notice and does not contribute anything
dynamic power dissipation in normal operating modes, significantly to the overall memory operation.
and inequality arises only due to the added complexity of • Process Variations and Robustness: LECTOR’s leakage
the 8T structure. 8T SRAM cell has extra transistors equal power dissipation efficiency is also used for its enhance-
to the sum of capacitance to be charged and discharged ment in process variation robustness. With fewer transis-
in read and write and therefore consume a small amount tors and higher process variations in future generations,
of more dynamic power compared to the 6T SRAM. SRAM cells leak and become unstable. The 8T SRAM
This is not large enough to outweigh the advantage of cell, with the additional transistors, is robust by nature
increased by the 8T structure because of read reliability since it provides improved write and read path separation.
and stability. The availability of LECTOR enables this resilience as
 it dynamically adapts the leakage current and facilitates proper approach for energy saving design without sacrificing
higher process variation stability. In comparison with the operation speed.
6T structure in isolation, which in itself is susceptible 3. Performance:
to process variation with resultant rising leakage and Access times (read and write latencies) play a major role in
impaired reliability. Total Trade-offs: Total trade-offs with determining the performance efficiency of SRAM cells. In 6T
LECTOR-based SRAM cell implementation are fairly and 8T SRAM architectures, adding LECTOR had very small
balanced, especially when power efficiency is of utmost impacts on performance deterioration. 6T SRAM: 6T cell’s
concern. SRAM 6T LECTOR provides high low overhead read and write latencies are 150ps without using LECTOR
area and better static power consumption reduction. 8T and are increased by an infinitesimally small value of 5-8ps
LECTOR SRAM, although more area-hungry and more in case LECTOR is being used. High-speed designs have the
complex, provides better leakage control and read stabil- delay virtually zero, wherein access time is typically in tens
ity. An either-or decision has to be made after careful of nanoseconds.
consideration of the application-specific requirements, 8T SRAM: The 8T design, whose transistors facilitate
i.e., area, power, and read stability requirements. the enhanced read stability, accommodates higher latencies
(approximately 180ps read and 200ps write). LECTOR, when
VI. F INDINGS combined with these, incurs an additional 10-12ps. Worst-case
Comparison of 6T and 8T SRAM cells both with and performance degradation is in the acceptable range for most
without the LECTOR (Leakage Control Transistor) technique high-speed systems. Power saving facilitated by LECTOR is
provides excellent insights into minimizing power dissipation significantly larger than relatively minor performance degra-
and performance of future SRAM structures. Key findings of dations.
the work are presented as follows: Thus, the LECTOR technique achieves massive power re-
1. Static Power reduction duction with a tolerable performance level. The power/speed
The most significant benefit of using the LECTOR tech- trade-off is particularly advantageous to low-power applica-
nique on SRAM cells is the reduction of static power dissi- tions that are not necessarily required to have ultra-high access
pation. Static power is a common problem in today’s VLSI times.
design, particularly with the scaling of technology nodes 4. Area Overhead:
where the leakage currents increase exponentially. LECTOR Area overhead due to LECTOR was studied to consider the
technique in 6T SRAM reduces static power dissipation by 35 chip area vs. power saving trade-off. Area overhead for 6T
percent. LECTOR transistor physically decouples the leakage SRAM was moderate, around 10 percent. This is due to the
paths in idle circuit states and therefore significantly reduces fact that only one extra transistor is required in order to apply
the energy wasted in idle states. the LECTOR technique, which is a small addition to the total
In 8T SRAM, it is more demanding, to as low as 50 percent area of the SRAM cell.
of static power consumption. With the additional transistor in For SRAM 8T, the overhead area is slightly larger at 12-15
8T configuration, there is increased decoupling of the storage percent, since more transistors are used in the 8T structure.
node from power rails, which can take advantage of the Although the rise here also is small compared to the huge
leakage control mechanism of LECTOR. power saved, especially for low-power consumption design.
These findings point out that LECTOR significantly reduces Even with overhead in area, performance reflects that LEC-
static power, and thus it is of very high utility in low-power TOR technique is a good tradeoff between power saving and
designs, especially for caches and other such scenarios where area, particularly for dense SRAM arrays where leakage saving
densities are high but powers are low. is highly necessary.
2. Dynamic Power Dissipation: 5. Process Variation Robustness:
Dynamic power dissipation as a result of switching activity Process variations—quantified in terms of variation in
of transistors during read and write has also been investigated. threshold voltage (Vth), oxide thickness, and channel
Incorporation of LECTOR has less impact on dynamic power length—have been found to be significant drivers of the per-
dissipation for 6T and 8T structures. Dynamic write power formance and reliability of SRAM cells. One of the advantages
dissipation in the 6T SRAM is barely changed, being approx- of using LECTOR is enhancing the immunity of 6T as well as
imately 3.1 µW per bit. Dynamic power contribution of the 8T SRAM cells to such variations. In 6T SRAM, the LECTOR
LECTOR transistor is zero since its emphasis is primarily on scheme reduces process variation susceptibility by a more
static leakage currents, as opposed to switching transients of robustly leaky path with uniform static power dissipation at
the read/write cycle. different process corners.
Similarly, in 8T SRAM example, dynamic write power is The 8T SRAM is also more robust due to the combined read
slightly increased to 4.5 µW/bit but without assuming any stability and LECTOR-based leakage control mechanism. The
perceivable gain after using LECTOR. In other words, that more sensitive 8T design over the 6T greatly benefits from
the power reduction by leakage control does not come with the LECTOR scheme due to stable power consumption and
any cost in dynamic performance, and thus LECTOR is a performance across different manufacturing environments.
 This process robustness is quite beneficial in later technol- reliable by reducing their susceptibility to process variation.
ogy nodes, where variation is more prevalent. The LECTOR This is especially important for reliability retention in future
technique enhances the reliability and stability of SRAM cells manufacturing nodes, where process variation becomes more
and thus makes them suitable for high-reliability and high- dominant. Lastly, the work demonstrates that the LECTOR
performance applications. technique is an executable power reduction technique for high-
6. Conclusion and Trade-Offs: end SRAM cells and offers a possible solution to adapt to
Overall, the LECTOR technique is optimal in power con- the evolving needs of low-power VLSI circuits, especially
sumption optimization in 6T and 8T SRAM cells. The key memory-centric designs. In the future, there is a possibility
conclusions can be summarized as follows: Power Efficiency: of integrating LECTOR with other techniques like dynamic
LECTOR delivers impressive reductions in static power con- voltage scaling so that power can be reduced further.
sumption (35 percent in 6T and 50 percent in 8T) at no expense
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measurable cost in terms of performance and therefore is an
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