74AHC1G08; 74AHCT1G08

2-input AND gate

Rev. 10.1 — 28 August 2024 Product data sheet

1. General description
The 74AHC1G08; 74AHCT1G08 is a single 2-input AND gate. Inputs are overvoltage tolerant. This
feature allows the use of these devices as translators in mixed voltage environments.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• CMOS low power dissipation
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
• Symmetrical output impedance
• Balanced propagation delays
• Input levels:
• For 74AHC1G08: CMOS level
• For 74AHCT1G08: TTL level
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +125 °C

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC1G08GW -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; SOT353-1
74AHCT1G08GW 5 leads; body width 1.25 mm
74AHC1G08GV -40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753
74AHCT1G08GV
74AHC1G08GZ -40 °C to +125 °C XSON5 plastic thermal enhanced extremely thin SOT8065-1
small outline package with side-wettable
flanks (SWF); no leads; 5 terminals;
body 1.1 × 0.85 × 0.5 mm
Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

4. Marking
Table 2. Marking codes
Type number Marking[1]
74AHC1G08GW AE
74AHCT1G08GW CE
74AHC1G08GV A08
74AHCT1G08GV C08
74AHC1G08GZ AE

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

A
1 B 1
Y 4 & 4 Y
2 A 2
B
mna113 mna114 mna221

Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram

6. Pinning information

6.1. Pinning

GZ package
GV package SOT8065-1 (XSON5)
GW package
SOT353-1 (TSSOP5) SOT753 (SC-74A)
B 1 5 VCC

B 1 5 VCC B 1 5 VCC
3
GND
A 2 A 2
A 2 4 Y
GND 3 4 Y GND 3 4 Y
aaa-035935

aaa-035731 aaa-035732 Transparent top view

6.2. Pin description

Table 3. Pin description
Symbol Pin Description
B 1 data input
A 2 data input
GND 3 ground (0 V)
Y 4 data output
VCC 5 supply voltage

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Product data sheet Rev. 10.1 — 28 August 2024 2 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level
Inputs Output
A B Y
L L L
L H L
H L L
H H H

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7.0 V
VI input voltage -0.5 +7.0 V
IIK input clamping current VI < -0.5 V -20 - mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA
IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 75 mA
IGND ground current -75 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 250 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT753 (SC-74A) package: Ptot derates linearly with 3.8 mW/K above 85 °C.
For SOT8065-1 (XSON5) package: Ptot derates linearly with 3.2 mW/K above 72 °C.

9. Recommended operating conditions

Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC1G08 74AHCT1G08 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VI input voltage 0 - 5.5 0 - 5.5 V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C
Δt/ΔV input transition rise and VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V
fall rate VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V

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Product data sheet Rev. 10.1 — 28 August 2024 3 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

10. Static characteristics

Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC1G08
VIH HIGH-level VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
input voltage VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
input voltage VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = -50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO = -50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
II input leakage VI = 5.5 V or GND; - - 0.1 - 1.0 - 2.0 μA
current VCC = 0 V to 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 1.0 - 10 - 40 μA
VCC = 5.5 V
CI input - 1.5 10 - 10 - 10 pF
capacitance
74AHCT1G08
VIH HIGH-level VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
input voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V
IO = -8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 μA - 0 0.1 - 0.1 - 0.1 V
IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V
II input leakage VI = 5.5 V or GND; - - 0.1 - 1.0 - 2.0 μA
current VCC = 0 V to 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 1.0 - 10 - 40 μA
VCC = 5.5 V

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Product data sheet Rev. 10.1 — 28 August 2024 4 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max Min Max Min Max
ΔICC additional per input pin; VI = 3.4 V; - - 1.35 - 1.5 - 1.5 mA
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
CI input - 1.5 10 - 10 - 10 pF
capacitance

11. Dynamic characteristics

Table 8. Dynamic characteristics
GND = 0 V; tr = tf = ≤ 3.0 ns. For test circuit see Fig. 5.
Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC1G08
tpd propagation A and B to Y; see Fig. 4 [1]
delay VCC = 3.0 V to 3.6 V [2]
CL = 15 pF - 4.6 8.8 1.0 10.5 1.0 12.0 ns
CL = 50 pF - 6.5 12.3 1.0 14.0 1.0 16.0 ns
VCC = 4.5 V to 5.5 V [3]
CL = 15 pF - 3.2 5.9 1.0 7.0 1.0 8.0 ns
CL = 50 pF - 4.6 7.9 1.0 9.0 1.0 10.5 ns
CPD power CL = 50 pF; f = 1 MHz; [4] - 17 - - - - - pF
dissipation VI = GND to VCC
capacitance
74AHCT1G08
tpd propagation A and B to Y; see Fig. 4 [1]
delay VCC = 4.5 V to 5.5 V [3]
CL = 15 pF - 3.6 6.2 1.0 7.1 1.0 8.0 ns
CL = 50 pF - 5.1 7.9 1.0 9.0 1.0 10.5 ns
CPD power CL = 50 pF; f = 1 MHz; [4] - 19 - - - - - pF
dissipation VI = GND to VCC
capacitance

[1] tpd is the same as tPLH and tPHL.

[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation PD (μW).
2 2
PD = CPD × VCC × fi + Σ(CL × VCC × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts

74AHC_AHCT1G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 10.1 — 28 August 2024 5 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

11.1. Waveform and test circuit

A, B input VM

tPHL tPLH

Y output VM

mna116

Measurement points are given in Table 9.

Fig. 4. Input (A and B) to output (Y) propagation delays

Table 9. Measurement point

Type Input Output
VI VM VM
74AHC1G08 GND to VCC 0.5VCC 0.5VCC
74AHCT1G08 GND to 3.0 V 1.5 V 0.5VCC

VCC

VI VO
PULSE
DUT
GENERATOR

RT CL

mna101

Test data is given in Table 8. Definitions for test circuit:

CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
Fig. 5. Test circuit for measuring switching times

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Product data sheet Rev. 10.1 — 28 August 2024 6 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

12. Package outline

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1

D B E A X

c
(5x)

y HE v M A

e1

5 4

pin 1 index
A A2

A1
1 2 3 A3
θ

w M B Lp
bp
(5x)
detail X
e e

0 3 mm
scale

Dimensions (mm are the original dimensions)

Unit A A1 A2 A3 bp c D(1) E(1) e e1 HE Lp v w y θ

max 1.1 0.1 1.0 0.30 0.25 2.2 1.35 2.4 0.46 8°
mm 0.15 0.65 1.3 0.3 0.1 0.1
min 0.8 0 0.8 0.15 0.08 1.8 1.15 1.8 0.26 0°
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. sot353-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
21-12-15
SOT353-1 MO-203 SC-88A
21-12-16

Fig. 6. Package outline SOT353-1 (TSSOP5)

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Product data sheet Rev. 10.1 — 28 August 2024 7 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

Plastic surface-mounted package; 5 leads SOT753

D B E A
X

y HE v M A

5 4

A1
c

1 2 3 Lp

detail X
e bp w M B

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A A1 bp c D E e HE Lp Q v w y

1.1 0.100 0.40 0.26 3.1 1.7 3.0 0.6 0.33

mm 0.95 0.2 0.2 0.1
0.9 0.013 0.25 0.10 2.7 1.3 2.5 0.2 0.23

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

SOT753 SC-74A 02-04-16

06-03-16

Fig. 7. Package outline SOT753 (SC-74A)

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Product data sheet Rev. 10.1 — 28 August 2024 8 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

XSON5: Plastic thermal enhanced extremely thin small outline package with
side-wettable flanks (SWF); no leads; 5 terminals; body 1.1 × 0.85 × 0.5 mm SOT8065-1
e
terminal 1
b v C A B
index area
(4×) w C
1 2

L
(4×)

3
e1

□Dh
k1 (4×)

5 4
k2
(2×)
y1 C

A
y C
5×
A3 (4×)

A1 seating plane
C
u C
2×
A D B
(2 ) (2)

terminal 1
index area
u C
(2) (2) 2×

0 1 mm
scale
Dimensions (mm are the original dimensions)

Unit A(1) A1 A3 b D (1) Dh E (1) e e1 k1 k2 L u v w y y1

max 0.50 0.040 0.28 0.35 0.30

mm nom 0.47 0.020 0.135 0.23 1.10 0.30 0.85 0.75 0.6 0.25 0.05 0.1 0.05 0.05 0.05
min 0.44 0.005 (typ) 0.20 0.27 0.2 0.45 0.22
Note:
1. Plastic or metal protrusions per side are not included.
2. Side wettable flanks (SWF), protrusion max. 0.02 mm. sot8065-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
24-07-09
SOT8065-1 MO-340
24-08-27

Fig. 8. Package outline SOT8065-1 (XSON5)

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Product data sheet Rev. 10.1 — 28 August 2024 9 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

13. Abbreviations
Table 10. Abbreviations
Acronym Description
ANSI American National Standards Institute
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
ESDA ElectroStatic Discharge Association
HBM Human Body Model
JEDEC Joint Electron Device Engineering Council
TTL Transistor-Transistor Logic

14. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT1G08 v.10.1 20240828 Product data sheet - 74AHC_AHCT1G08 v.10
Modifications: • Fig. 8: Added JEDEC reference MO-340 to SOT8065-1 package outline drawing.
74AHC_AHCT1G08 v.10 20240715 Product data sheet - 74AHC_AHCT1G08 v.9
Modifications: • Type number 74AHC1G08GZ (SOT8065-1/XSON5) added.
74AHC_AHCT1G08 v.9 20230830 Product data sheet - 74AHC_AHCT1G08 v.8
Modifications: • Section 2: ESD specification updated according to the latest JEDEC standard.
74AHC_AHCT1G08 v.8 20220111 Product data sheet - 74AHC_AHCT1G08 v.7
Modifications: • The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 1 and Section 2 updated.
• Fig. 6: SOT353-1 (TSSOP5) package outline drawing has changed.
• Section 8: Derating values for Ptot total power dissipation updated.
74AHC_AHCT1G08 v.7 20141118 Product data sheet - 74AHC_AHCT1G08 v.6
Modifications: • Section 4: table note added.
74AHC_AHCT1G08 v.6 20070629 Product data sheet - 74AHC_AHCT1G08 v.5
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Package SOT353 changed to SOT353-1 in Section 3 and Section 12.
• Quick reference data and Soldering sections removed.
74AHC_AHCT1G08 v.5 20020606 Product specification - 74AHC_AHCT1G08 v.4
74AHC_AHCT1G08 v.4 20020221 Product specification - 74AHC_AHCT1G08 v.3
74AHC_AHCT1G08 v.3 20010209 Product specification - 74AHC_AHCT1G08 v.2
74AHC_AHCT1G08 v.2 19990127 Product specification - 74AHC_AHCT1G08_N v.1
74AHC_AHCT1G08_N v.1 19981125 Preliminary specification - -

74AHC_AHCT1G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 10.1 — 28 August 2024 10 / 12

Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate
injury, death or severe property or environmental damage. Nexperia and its

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Nexperia 74AHC1G08; 74AHCT1G08
2-input AND gate

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking.......................................................................... 2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description............................................................. 2
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveform and test circuit.......................................... 6
12. Package outline.......................................................... 7
13. Abbreviations............................................................ 10
14. Revision history........................................................10
15. Legal information......................................................11

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Date of release: 28 August 2024

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