ECE 221

Digital Logic Design

Sequential Circuits
Latches and Flip-Flops
Mohammed Sharaf Sayed
Mohammed.sayed@ejust.edu.eg
 Lecture Outline

• Sequential Circuits
• Latches
• Flip-Flops
• Characteristic Tables and Equations
• Direct Inputs
• Analysis of Clocked Sequential Circuits
• State Equations, Table, and Diagram

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 Sequential Circuits

• It consists of a combinational circuit to which storage elements

are connected to form a feedback path.
• The binary information stored in these storage elements at any
given time defines the state of the sequential circuit at that
time.
• The sequential circuit receives binary information from external
inputs that, together with the present state of the storage
elements, determine the binary value of the outputs.

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 Sequential Circuits
• These external inputs also determine the condition for changing
the state in the storage elements.
 Thus, a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.
 In contrast, the outputs of combinational logic depend only on
the present values of the inputs.
• There are two main types of sequential circuits, and their
classification is a function of the timing of their signals:
– A synchronous sequential circuit is a system whose behavior
can be defined from the knowledge of its signals at discrete
instants of time.
– An asynchronous sequential circuit depends upon the input
signals at any instant of time and the order in which the
4 inputs change.
 Sequential Circuits
• A synchronous sequential circuit employs signals that affect the
storage elements at only discrete instants of time.
• Synchronization is achieved by a timing device called a clock
generator, which provides a clock signal having the form of a
periodic train of clock pulses, which is commonly denoted by the
identifiers clock and clk.
• Synchronous sequential circuits that use clock pulses to control
storage elements are called clocked sequential circuits.
• They are called synchronous circuits because the activity within
the circuit and the resulting updating of stored values is
synchronized to the occurrence of clock pulses.
• The storage elements (memory) used in clocked sequential
circuits are called flip-flops.
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 Sequential Circuits

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 Sequential Circuits
• The outputs are formed by a combinational logic function of the
inputs to the circuit or the values stored in the flip-flops (or both).
• The value that is stored in a flip-flop when the clock pulse occurs is
also determined by the inputs to the circuit or the values presently
stored in the flip-flop (or both).
• The new value is stored (i.e., the flip-flop is updated) when a pulse of
the clock signal occurs.
• The combinational logic must respond to a change in the state of the
flip-flop in time to be updated before the next pulse arrives.
• Propagation delays play an important role in determining the
minimum interval between clock pulses that will allow the circuit to
operate correctly.
• A change in state of the flip-flops is initiated only by a clock pulse
transition.
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 Latches

• Storage elements that operate with signal levels are referred to

as latches while those controlled by a clock transition are flip-
flops.
• Latches are said to be level-sensitive devices while flip-flops are
edge-sensitive devices.
• Latches are the basic circuits from which all flip-flops are
constructed.
• Latches are useful for storing binary information and for the
design of asynchronous sequential circuits.
• Latches are not practical for use as storage elements in
synchronous sequential circuits.
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 SR Latch

• The SR latch is a circuit with two cross-coupled NOR gates or two

cross-coupled NAND gates, and two inputs labeled S for set and
R for reset.
• The latch has two useful states:
– S = 1 and R = 0  Q = 1 and Q’ = 0, the latch is in the set
state.
– S = 0 and R = 1  Q = 0 and Q’ = 1, the latch is in the reset
state.
– S = 0 and R = 0  No change.
– S = 1 and R = 1  Q = 0 and Q’ = 0, forbidden condition
because if both inputs are then switched to 0 simultaneously,
the device will enter an unpredictable or undefined state or a
metastable state.
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 SR Latch
0
1

0
1

 The NAND require the complement of S and R, It requires a 0 signal

to change its state  it is sometimes referred to as an S’R’ latch.
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 SR Latch
• The basic SR latch can be modified by adding a control or enable
signal En.
 S = 1, R = 0, and En = 1  set state
 S = 0, R = 1, and En = 1  reset state
 En = 0  the circuit remains in its current state.
 S = R = 0, and En = 1  the state of the circuit does not change.
 S = R = 1, and En = 1  An indeterminate condition occurs.

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 D Latch
• One way to eliminate the undesirable condition of the
indeterminate state in the SR latch is to ensure that inputs S and
R are never equal to 1 at the same time.
• This is done in the D latch  This latch has only two inputs: D
(data) and En (enable).
• The D latch receives that designation from its ability to hold data
in its internal storage.

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 D Latch
• As long as the enable input is at 0, the cross-coupled SR latch has
both inputs at the 1 level and the circuit cannot change state
regardless of the value of D .
• The D input is sampled when En = 1.
– If D = 1, output Q goes to 1, placing the circuit in the set state.
– If D = 0, output Q goes to 0, placing the circuit in the reset state.
• The output follows changes in the data input as long as the enable
input is asserted.
• This situation provides a path from input D to the output, and for
this reason, the circuit is often called a transparent latch.
• When the enable input signal is de-asserted, the value of the data
input at the time the transition occurred is stored at the Q output.
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 Latches

Graphic symbols for latches

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 Flip-Flops

• A trigger is the momentary change in the control input of a latch

or flip-flop that causes change in its state.
• The D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic-1 level.
• As long as the pulse input remains at this level, any changes in
the data input will change the output and the state of the latch.
• The result is an unpredictable situation, since the state of the
latches may keep changing for as long as the clock pulse stays at
the active level.
 The key to the proper operation of a flip-flop is to trigger it only
during a signal transition.

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 Flip-Flops

• A clock pulse goes through two transitions: from 0 to 1 and the

return from 1 to 0.
• The positive transition is defined as the positive edge and the
negative transition as the negative edge.
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 Flip-Flops
• D flip-flop can be constructed with two D latches and an inverter.
• The first latch is called the master and the second the slave.
• The circuit samples the D input and changes its output Q only at
the negative edge of the synchronizing or controlling clock
(designated as Clk).

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 Flip-Flops

• When Clk = 1:
– The data from the external D input is transferred to the
master output at Y.
– The slave is disabled.
• Any change in the input changes the master output at Y, but
cannot affect the slave output.
• When Clk = 0:
– The slave latch is enabled, and the value of Y is transferred to
the output of the flip-flop at Q.
– The master latch is disabled because Clk = 0, and is isolated
from the D input
• A change in the output of the flip-flop can be triggered only by
and during the transition of the clock from 1 to 0.
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 Flip-Flops

• The dynamic indicator (>) denotes the fact that the flip-flop
responds to the edge transition of the clock.
• A bubble outside the block adjacent to the dynamic indicator
designates a negative-edge for triggering the circuit.
• The absence of a bubble designates a positive-edge response.
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 Flip-Flops

• There is a minimum time called the setup time during which the
D input must be maintained at a constant value prior to the
occurrence of the clock transition.
• Similarly, there is a minimum time called the hold time during
which the D input must not change after the application of the
positive transition of the clock.
• The propagation delay time of the flip-flop is defined as the
interval between the trigger edge and the stabilization of the
output to a new state.

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 T Flip-Flop
• The T (toggle) flip-flop is a complementing flip-flop
• The T flip-flop can be constructed with a D flip-flop and an XOR.
D = T ⊕ Q = TQ’ + T’Q
T=0D=Q T = 1  D = Q’

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 Characteristic Tables and Equations

• For the D flip-flop,

Q(t + 1) = D
• For the T flip-flop,
Q(t + 1) = T ⊕ Q = TQ’ + T’Q

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 Characteristic Tables and Equations

• A characteristic table defines the logical properties of a flip-

flop by describing its operation in tabular form.
• It defines the next state (i.e., the state that results from a
clock transition) as a function of the inputs and the present
state.
• Q(t) is the present state and Q(t + 1) is the next state.
• Q(t) denotes the state of the flip-flop immediately before the
clock edge, and Q(t + 1) denotes the state that results from
the clock transition.
• The logical properties of a flip-flop can be expressed
algebraically with a characteristic equation.

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 Direct Inputs

• Some flip-flops have asynchronous inputs that are used to

force the flip-flop to a particular state independently of the
clock.
• The input that sets the flip-flop to 1 is called preset or direct
set. The input that clears the flip-flop to 0 is called clear or
direct reset .
• Example:
 When power is turned on in a digital system, the state of
the flip-flops is unknown.
 The direct inputs are useful for bringing all flip-flops in the
system to a known starting state prior to the clocked
operation.
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 Direct Inputs
D flip-flop with active-low asynchronous reset

• When the reset input is 0, it clears output Q to 0 and Q’ becomes 1.

• The value in D is transferred to Q with every positive-edge clock
signal, provided that R = 1.

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 Analysis of Clocked Sequential Circuits

• A logic diagram is recognized as a clocked sequential circuit if

it includes flip-flops with clock inputs.
• The analysis of a sequential circuit consists of obtaining a
table or a diagram for the time sequence of inputs, outputs,
and internal states.
• The outputs and the next state are both a function of the
inputs and the present state.
• The behavior of a clocked sequential circuit can be described
by means of state equations.
• A state equation (also called a transition equation) specifies
the next state as a function of the present state and inputs.
• The right side of the equation is a Boolean expression that
specifies the present state and input conditions that make the
next state equal to 1.
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 Analysis of Clocked Sequential Circuits

 Example: Write the state

equations for the
following circuit:

DA = A(t + 1) = Ax + Bx

DB = B(t + 1) = A’x

y = (A + B)x’

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 Analysis of Clocked Sequential Circuits

• The time sequence of

inputs, outputs, and flip-
flop states can be
enumerated in a state
table (sometimes called a
transition table).
• The table consists of four
sections labeled present
state, input, next state,
and output.

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 Analysis of Clocked Sequential Circuits

• The present-state section shows the states of the flip-flops at

any given time t.
• The input section gives a value of the input for each possible
present state.
• The next-state section shows the states of the flip-flops one
clock cycle later, at time t + 1.
• The output section gives the value of y at time t for each
present state and input condition.

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 State Table

• It is sometimes convenient to express the state table in a slightly

different form having only three sections: present state, next state,
and output.
• The input conditions are enumerated under the next-state and
output sections.
• For each present state,
there are two possible
next states and
outputs, depending on
the value of the input.

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 State Diagram

• The information available in a state table can be represented

graphically in the form of a state diagram.
• A state is represented by a circle, and the (clock-triggered)
transitions between states are indicated by directed lines
connecting the circles.
• The binary number inside each circle identifies the state of
the flip-flops.
• The directed lines are labeled with two binary numbers:
– The input value during the present state is labeled first.
– The number after the slash gives the output during the
present state with the given input.

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 State Diagram

A(t + 1) = Ax + Bx
B(t + 1) = A’x
y = (A + B)x’

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 State Diagram

• The output along the directed line occurs during the present
state and with the indicated input, and has nothing to do with
the transition to the next state.
• A directed line connecting a circle with itself indicates that no
change of state occurs.
• The steps presented in this example are:
Circuit diagram  Equations  State table  State diagram
• The state diagram gives a pictorial view of state transitions
and is the form more suitable for human interpretation of the
circuit’s operation.

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 Lecture Summary

• We have discussed the following topics:

 Sequential Circuits
 Latches
 Flip-Flops
 Characteristic Tables and Equations
 Direct Inputs
 Analysis of Clocked Sequential Circuits
 State Equations, Table, and Diagram

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 Mohammed Sharaf Sayed
Mohammed.sayed@ejust.edu.eg