EC106

Chapter 6
Sequential Logic
Nithin Chatterji
Assistant Professor
ECED, SVNIT
Prepared using:
1. Morris Mano, “Digital Logic and Computer Design.” (Pearson India, 2017)
 Introduction
• Sequential logic: Systems with combinational circuits and
memory elements are described.
• Feedback path.
• Memory elements
– Stores binary information
– Binary information defines the state of the sequential circuit.
• External i/ps plus state of the memory elements determine
– the o/ps and the next state of the memory element.
• Sequential circuit is specified by a time sequence of i/ps,
o/ps and internal states.
 Synchronous vs Asynchronous Sequential
Circuits (based on timing)
Synchronous Asynchronous
• Behavior can be defined from the • Behavior depends upon
knowledge of its signals at discrete
instants of time. – the order in which its i/p
signals change
• Synchronization by master-clock
generator. – Can be affected at any
– Produces periodic train of clock instant of time.
pulses. • Memory devices used are
– Distributed throughout the system. time-delay devices.
– Memory systems are affected only
with arrival of the synchronization • Unreliable due to variation
pulse (AND gates) in delays of the i/ps.
 Clocked Sequential circuits
• Synchronous Sequential circuits that use clock pulses in the i/ps of
the memory elements: Clocked Sequential circuits.
• Most frequent.
• Do not have instability problems.
• Timing is broken into independent discrete steps.
• Sequential circuits we discuss are clocked sequential circuits.
• Memory elements used are called flip-flops.
– Binary cells capable of storing one bit of information.
– 2 o/ps: normal and complement values.
– Various types of flip-flops: based on the entry of binary information.
 Flip-Flops
• Maintain a binary state indefinitely ( as long as power is
delivered to the circuit)
• States are switched when directed by i/p signals.
• Different types of FF
– Number of i/ps
– Manner in which i/ps affect the binary state.
 Basic Flip-Flop circuit
• Constructed from 2 NAND or NOR
gates.
– more complicated types can be built
from these basic FFs.
• Cross-coupled connection from the
o/p of one gate to the i/p of the other
gate: Feedback
– Asynchronous sequential circuits
• 2 o/ps: Q and Q’, 2 i/ps: set and reset 1
• Binary state of FF is the value of the
normal o/p Q.
2
 NOR Flip-Flop circuit

• Normal operation: S=R=0.

• Set: S=1, R=0
• Reset: S=0, R=1;
• Undefined: S=R=1
 NAND Flip-Flop circuit

• Normal operation: S=R=1.

1
• Set: S=0, R=1
• Reset: S=1, R=0;
2
• Undefined: S=R=0
 Clocked SR Flip-Flop
• Graphic Symbol
– triangle is a symbol for a
dynamic indicator
– Indicates: FF responds to an i/p
clock transition from 0 to 1.
– State of the FF is determined by
Q.
 Clocked SR Flip-Flop
• Characteristic table
 Clocked SR Flip-Flop
• Characteristic equation
– specifies the value of the next state
as a function of the present state and
the inputs.
– an algebraic expression for the
binary information of the
characteristic table.
– two indeterminate states are marked
by X’s.
– both S and R cannot equal 1
simultaneously
 D Flip-Flop (transfer “data”)
• Modification of the clocked SR flip-flop
– SR flip-flop with an inverter in the R input.
– Also called gated D-latch.
– CP input is often given the variable designation G (for gate).
 D Flip-Flop (transfer “data”)
• Modification of the clocked SR flip-flop
– SR flip-flop with an inverter in the R input.
– Also called gated D-latch.
– CP input is often given the variable designation G (for gate).
• Graphic Symbol
 D Flip-Flop (transfer “data”)
• Modification of the clocked SR flip-flop
– SR flip-flop with an inverter in the R input.
– Also called gated D-latch.
– CP input is often given the variable designation G (for gate).
• Characteristic table
 D Flip-Flop (transfer “data”)
• Modification of the clocked SR flip-flop
– SR flip-flop with an inverter in the R input.
– Also called gated D-latch.
– CP input is often given the variable designation G (for gate).
• Characteristic Equation
 JK Flip-Flop
• Refinement of the SR flip-flop
– indeterminate state of the SR type is defined in JK.
 JK Flip-Flop
• Refinement of the SR flip-flop
– indeterminate state of the SR type is defined in JK.
• Characteristic Table
 JK Flip-Flop
• Refinement of the SR flip-flop
– indeterminate state of the SR type is defined in JK.
• Characteristic equation
 JK Flip-Flop
• Refinement of the SR flip-flop
– indeterminate state of the SR type is
defined in JK.
• If CP=1 and J=K=1
– Repeated and continuous transitions of
o/ps.
– To avoid this
• CP must be shorter than the propagation
delay through the FF.
 T Flip-Flop
• Single i/p version of JK FF.
– Both J and K are tied together.
– T stands for “toggle”, when T=1 and CP=1.
• Obtain the Characteristic Table and Characteristic
equation.
 Different conventions used
Latch vs Flip-Flop
• Latch is level-triggered.
• Flip-Flop is edge-triggered.
 Triggering of Flip-Flops
• Switch in the state of a FF by momentary change in the i/p
signal
– Momentary change: Trigger
• For Latches (Asynchronous FF) triggering is by change of
signal level.
– Level should return to its initial value (0 in NOR and 1 in NAND)
before second trigger.
• Flip-Flops (Clocked FF) are triggered by pulses.
– Pulse start from an initial value of 0, goes briefly to 1, and returns
to its initial value of 0.
– Time interval from the application of pulse until the o/p transition
is critical.
 Feedback path and instability

• Instability
– If o/ps of FFs are changing while the o/ps of the combinational circuits (i/ps
to FFs) are being sampled by the clock pulse.
• Can be prevented
– If o/ps of FFs do not start changing until pulse i/p returns to 0.
– Signal propagation delay of a FF from the i/p to o/p should be greater than
the pulse duration. (Difficult to control)
– Include a physical unit for the delay or
– Make FF sensitive to pulse transition.
 Definition of Clock pulse transition
• Positive pulse: 1 during the occurrence of pulse. 0
otherwise.
• 0 to 1: Positive edge
• 1 to 0 negative edge
 Multiple-transition problem
• Clocked flip-flops introduced is:
– Triggered during the positive edge of the pulse.
– State transition starts immediately after pulse becomes 1.
– New state of the FF may appear at the o/p while the pulse is
still 1.
– FF will start responding to these new values.
– A new o/p may occur.
– Hence, o/p of 1 FF cannot be applied to the i/p of another FF
when both are triggered by the same clock pulse.
• Can be eliminated if FF respond to edge transition only.
 Capacitive coupling
• RC circuit is inserted in the clock i/p of the FF.
– Generates a spike in response to momentary change in i/p.
– Positive spike: At positive Edge; Negative spike: At negative
Edge
• Edge triggering: By designing the FF to respond to one
spike and neglect the other.
 Master-Slave Flip-Flop
• Constructed from two separate FFs.
– One master and other acts as slave.
• When CP=0
– Slave is enabled.
– Q=Y
– Master is disabled.
• When CP=1 • When CP returns to 0
– Master is enabled. – Slave goes to the same
– Information at S and R i/ps is state as the master.
transmitted to Y.
– Slave is disabled.
Timing relationships in a master-slave flip-flop
• Initially FF is cleared
– Y=Q=0.
• S input can be changed at the same time that
the pulse goes through its negative edge
transition.
• Once the CP reaches 0, the master is disabled.
– possible to use the same clock pulse to switch
• output of the flip-flop
• input information.
• State changes at the negative edge transition
of the clock pulse.
 Clocked master-slave JK flip-flop
• Gates 1 to 4: Master FF.
• 5 to 8: Slave FF
 Cascading of many Master-Slave FFs
• When pulse is 1 all the masters (internal to the FF) are
enabled
– O/p of the FFs are not affected.
• After the clock returns to 0.
– Slaves are enabled.
– O/ps of some of the FFs are changed.
– None of the masters are affected by these changes.
 Edge-Triggered Flip-Flop
• Output transitions occur at a specific level of the clock
pulse
– When the pulse input level exceeds this threshold level, i/ps
are locked out.
– Could be positive or negative edge triggered.
 D-type positive-edge-triggered flip-flop
• Consists of three basic FFs.
– 1 and 2; 3 and 4; 5 and 6
• S=R=1: o/ps remain in the steady-
state values.
• Set: S=0 and R=1.
• Reset: S=1 and R=0.
CP=0
 CP=1
• S and R determined by the states of other 2 FFs.

CP=1
 Setup time
• Definite time for which D input
must be maintained at a constant
value prior to the application of the
pulse.
– Equals to the propagation delay
through gates 4 and 1
 Hold time
• Definite time for which D input
must be maintained at a constant
value after the application of the
CP=1
positive transition of the pulse.
– Equals to the propagation delay
through gate 3.
• To ensure that R becomes 0 in order to
maintain the o/p of gate 4 at 1 regardless
of the value of D.
 Direct Inputs
• Direct preset: Set asynchronously.
• Direct clear: Reset asynchronously.
– Helpful to bring all FFs to an initial cleared state.
• Must be connected to both master and slave to override
other i/ps and the clock.
 Sequential circuit analysis
• Behavior of the sequential circuit is determined from the
i/ps, o/ps and present state of the circuit.
• O/ps and next state: function of i/ps and the present state.
• Analysis: Obtain proper description of the time sequence
of i/ps, o/ps and states.
– State table or state diagram
– Or Boolean expressions (time sequence must be included
directly or indirectly)
 Example 1
• Logic diagram of a sequential circuit can
be drawn with knowledge of :
– Type of Flip-Flop (FF) used.
– Boolean functions for all the combinational
circuits.
• FF i/p equations: Boolean functions
– Time is not explicitly included, but implied
from C.
• SA = R A =
• S𝐵 = R B =
• Y =
 State table

Mealy Model circuits: O/p depends on the i/ps as well as the present state

Moore Model circuits: O/p depends on the present state only. One dimensional
state table is enough.
 Moore Model circuit
• DA = A ⊕ X ⊕ Y
• Z=A
• Draw the logic diagram
and state table.
 State Diagram
• Information available in state table graphically
represented.
• More suitable for human interpretation.
• State: represented by a circle.
• Transitions: Indicated by directed lines connecting
circles.
 Example
Mealy Model circuit
 Example
Moore Model circuit
State equation
Excitation Table SR FF
Excitation Table D FF
Excitation Table JK FF
Excitation Table T FF
 Sequential Circuit Design
• Starts with specification and ends with the logic diagram or set of
Boolean functions from which the logic diagram can be obtained.
• A combinational circuit could be fully specified by a truth table.
• A sequential circuit requires a state table or a state diagram.
• The design involves
– Choosing the FF
– Finding a combination circuit which along with the FFs fulfills the
specifications.
– n FFs can represent 2n states.
– Combination circuit derived from the state table by finding- FF i/p and
o/p equations.
– After assignment of states by binary combinations, a sequential problem
translates to combinational problem.
 Design Procedure
• Specification
• Formulations: State diagram or State table.
• State reduction if sequential circuit characterized by the i/p-o/p
relationships independent of the number of states.
• State Assignment: Assign binary codes to the states in the table.
• Determine the number of FFs needed and assign a letter symbol
• Choose the type of FF. (SR or D for transfer of data, T for applications
involving complementation (binary counters) and JK for general
applications.)
• From the state table, derive the circuit excitation and output tables.
• Using the map or any other simplification method, derive the circuit
output functions and FF i/p functions.
• Draw the logic diagram.
 Problem: Use JK FF to design the clocked
sequential circuit shown in the state diagram.
Excitation table
I/ps to the FF (combinational
circuits)
I/ps to the FF (combinational
circuits)
Block diagram
 Design of Counters
• Counters: Sequential circuits which undergo prescribed
sequence of states upon application of i/p pulse.
• I/p pulse: Called count pulse.
– clock or from an external source.
– Prescribed time or random.
• Sequence: binary (simplest and straightforward) or any other
• Used in all equipment with digital logic.
– Number of occurrences.
– Timing sequences to control operations.
 Binary Counters
• Simplest and straight forward.
• n-bit counter: n FFs and count from 0 to 2n-1.
• FF count repeats. Goes to 000 after 111.
• i/p and o/p values not shown.
• Clocked sequential circuits: State transitions during clock pulses.
Not shown explicitly.
• Only i/p: Count pulse.
• O/ps: Specified by the present states of FFs.
• Next state
– Depends only on the present state.
– Transitions during clock pulses.
– Completely specified by the count sequence.
 Excitation Table for 3-bit counter
• Next number represents
the next state.
• Count sequence:
Provides all information
to design the circuit.
• Follows the same procedure.
• Excitation obtained directly from the count sequence.
• Binary counters most effectively constructed by T FFs.
• Last row compared with the first count 000, its next state.
Simplification of FF i/ps.
Simplification of FF i/ps.
 Other counters
• BCD counter: Sequence from 0000 to 1001.
• Other counters may follow random sequences.
• Design procedure is same.
• Excitation table obtained by comparing present state
and next state.
• Next state of the last entry is the first count.
Design a counter that has repeated sequence of
six states.
• Use JK FF.
Simplification of FF i/ps
 Review
• Flip-Flops
• Triggering of Flip-Flops
• Analysis of clocked sequential circuits
• State reduction and Assignment
• Flip-Flop Excitation Tables
• Design Procedure
• Design of counters
• Design with state equations