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Coa L3

COA resource L3

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0% found this document useful (0 votes)
4 views37 pages

Coa L3

COA resource L3

Uploaded by

Aashi Verma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Organization and

Architecture
Lecture-3

Faculty: Dr. Asif Uddin Khan


Functional Units of Computer

2
Input/output Unit
Input Devices
l Keyboard

l Mouse

l Scanner

Output Devices
l Monitor

l Projector

l Printer
3
Memory Unit
l Store programs and data
l Two classes of storage(primary and secondary)
Ø Primary storage
v Fast
v Programs must be stored in memory while they are being executed
v Large number of semiconductor storage cells
v Processed in words
v Storage cell has Address
v Memory hierarchy – cache, main memory
Ø Secondary storage
v Larger and cheaper
non-volatile device that holds data until it is deleted or overwritten

4
Memory Unit

5
Central Processing Unit(CPU)
CPU has three components
•Arithmetic and Logic Unit(ALU)
•Control Unit(CU) •Registers used
•Registers with ALU for faster
operation

6
Arithmetic and Logic Unit(ALU)
Performs arithmetic and logical operations
l Arithmetic operations − bit addition,
subtraction, multiplication and division.
l logical operations − AND, OR, NOT, XOR,
NOR, NAND, etc.
l Bit-Shifting Operations − Shifting the positions
of the bits by a certain number of places either
towards the right or left.

7
Arithmetic and Logic Unit(ALU)
Performs arithmetic and logical operations
l Arithmetic operations − bit addition,
subtraction, multiplication and division.
l logical operations − AND, OR, NOT, XOR,
NOR, NAND, etc.
l Bit-Shifting Operations − Shifting the positions
of the bits by a certain number of places either
towards the right or left.

8
Control Unit
l All computer operations are controlled by the control
unit.
l The timing signals that govern the I/O transfers are
also generated by the control unit.
l Control unit is usually distributed throughout the
machine instead of standing alone.
l Operations of a computer:
Ø Accept information in the form of programs and data through an
input unit and store it in the memory
Ø Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
Ø Output the processed information through an output unit
Ø Control all activities inside the machine through a control unit

9
Processor Registers
l Registers are very fast computer memory which are used during
execution of programs efficiently
l Used to quickly access, store, and transfer data and instructions that
are being used immediately by the CPU.
l A processor register may hold an instruction, an address, or any data

10
Registers used in Processor
l Instruction register (IR):Stores instruction
to be executed
l Program counter (PC):Gives address of
next instruction
l General-purpose register (R0 – Rn-1):Used
by CPU for temporary storage
l Memory address register (MAR):Holds
memory address where CPU wants to read
or write data
l Accumulator register: Used during
arithmetic and logical operation of ALU. 11
Registers used in Processor
Memory Data Register (MDR):
l Holds data/instruction from memory to processor.

l Holds data from processor to memory or I/O devices.

12
Basic Operational Concepts
l Activity in a computer is governed by instructions.
l To perform a task, an appropriate program
consisting of a list of instructions is loaded in the
memory.
l Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
l Data to be used as operands are also stored in the
memory and taken to processor for processing

13
Operational concepts

OperatingSteps:
•Instruction fetch based on PC and store in IR
•Instruction decode
•Operand fetch
•Perform ALU operation
•Store result
•Increment PC to point next instruction during
execution

Example-1: Add LOCA, R0


üAdd the operand at memory location
LOCA to the operand in a register R0 in
the processor.
üPlace the sum into register R0.

Processor and memory interaction


14
Typical Operating Steps
l Programs reside in the memory through input
devices
l PC is set to point to the first instruction
l The contents of PC are transferred to MAR
l A Read signal is sent to the memory
l The first instruction is read out and loaded
into MDR
l The contents of MDR are transferred to IR

15
Typical Operating Steps (Cont’)

l Get operands for ALU


Ø From General-purpose register
Ø From Memory (address to MAR – Read – MDR to
ALU)
l Perform operation in ALU
l Store the result back
Ø To general-purpose register
Ø To memory (address to MAR, result to MDR – Write)
l During the execution, PC is
incremented to the next instruction 16
A Typical Instruction
l Add LOCA, R0
l Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
l Place the sum into register R0.
l The original contents of LOCA are preserved.
l The original contents of R0 is overwritten.

17
Operating Steps of Add LOCA, R0
l PC gives memory address of the instruction “Add LOCA, R0”
l Address is loaded into MAR
Fetch
l Memory location identified
l Control Unit(CU) sends read signal to the memory
l Instruction is read and loaded into MDR
l Instruction is moved from MDR to the processor register(IR)
l Instruction decoded
l The operand at LOCA is fetched
l The fetched operand is added to the contents of R0
l The resulting sum is stored in register R0
18
Separate Memory Access and
ALU Operation
l Load LOCA, R1
l Add R1, R0
l Whose contents will be overwritten?

19
Question: Write the operational steps
of following instruction
l Add R0, LOCA
ü Add the operand in a register R0 to the operand in
memory location LOCA.
ü Place the sum into register to the memory location LOCA.

20
BUS STRUCTURE
• A group of parallel wires that connect the
functional units of computer and serves as a
connecting path is known as BUS
• Connect different parts inside a computer together.
üIn addition to the lines that carry the data, the bus must
have lines for address and control purposes.
üThe simplest way to interconnect functional units is to
use a single bus, as shown below.

21
Bus Structure
• Each wire in a bus can transfer one bit of information.
• The number of parallel wires in a bus is equal to the word
length of a computer.
• The devices connected to a bus vary widely in their speed
of operation
ü Some devices are relatively slow, such as printer and keyboard.
ü Some devices are considerably fast, such as optical disks.
ü Memory and processor units operate are the fastest parts of a
computer.
• Efficient transfer mechanism thus is needed to cope with
this problem
ü A common approach is to include buffer registers with the
devices to hold the information during transfers.
ü Prevent a high-speed processor from being locked to a slow I/O
device during a sequence of data transfers.

22
Single Bus Vs Multi Bus system
• Single Bus: All units are connected to this Bus. One
transfer at a time. Two units are active at a time.
Cost is low.
• Multi Bus: Allows more parallelism. More cost.

23
Types of Buses
• Data Bus: Carries data
• Address Bus: Carries address
• Control Bus: Carries control signals

24
Bus Width
• Refers to the number of parallel lines(wires) used in
the bus.
• It determines the number of bits that can be
carried by the bus.

25
Data Bus
• Used to transfer data within Microprocessor and
Memory/Input or Output devices.
• It is bidirectional as Microprocessor requires to send
or receive data.
• The word length of a processor depends on data bus
width. 8 bit Microprocessor has 8 bit data bus and
16 bit Microprocessor has 16 bit data bus.
• Example:
üIntel 8085 is called 8 bit Microprocessor because it has an
8 bit data bus. Intel 8086 is called 16 bit Microprocessor.

26
Address Bus
• Used to transfer the addresses of Memory or I/O devices.
• It is unidirectional.
• The width of the address bus refers to the number of parallel
lines(wires) used in address bus.
• The number of bits that can be used to form an address of a
memory location depends on the address bus width.
• Example:
ü Intel 8085 microprocessor, has 16 bit address bus. This means it can
transfer maximum 16 bit address. So its memory addressing capacity
= 216 = 65,536 = 64K.
ü Intel 8086 microprocessor, has of 20 bit address. So its memory
addressing capacity = 220 = 1MB.

27
Control Bus
• It consists of a number of signals that are
used to synchronize the operation of the
individual microcomputer elements.
• The microprocessor sends some of these
control signals to the other elements to
indicate the type of operation being
performed.

28
Numerical Questions of
Bus Structure
Dr. Asif Uddin Khan
Memory Units

30
Bus Width

• Refers to the number of parallel lines(wires) used in the


bus.
• It determines the number of bits that can be carried by
the bus.

31
Address bus width
• The width of the address bus refers to the number
of parallel lines(wires) used in address bus.
• It determines the number of bits that can be used
to form an address of a memory location.
• If a memory contains n locations, then we require
log2n bits to represent any location of the memory.
• Example: A memory has 32 locations. Find the
width of the address bus.
• Ans: log232=5 bits

32
Questions
Q1) Find the address bus width for following
üThe memory size of a system is 16MB
üThe memory size of a system is 4GB
üThe memory size of a system is 8GB
üThe memory size of a system is 32KB

Q2) The address bus width of a system is 33 bits. Find


the maximum possible memory locations(memory
capacity).

33
Data bus width

• The width of the data bus refers to the number of


parallel lines(wires) used in data bus.
• Word length of a processor depends on the data
bus width.
• If word length of a processor is n bits then the
processor is treated as n bit processor
• Example: 32 bit processor means data bus width is
32 bits

34
Question-1

• There is a system having 32 bit processor with 64GB memory.


Find out the word length and width of the address and data bus.

35
Question-2

• There is a system having 64 bit processor with 128TB


memory. Find out the word length and width of the address
and data bus.

36
References
1. C o m p u t e r O rga n i za t i o n : C a r l H a m a c h e r ,
ZvonkoVranesic and SafwatZaky, Fifth Edition
McGraw-Hill, 2002.
2. Computer System Architecture: Moris M. Mano,
PHI New Delhi.

37

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