ADVANCED HIGH-

PERFORMANCE BUS
(AHB) PROTOCOL
An Overview of AHB Protocol in SoC Designs
Presented By :
Sriramula Nithin
Key Features of AHB :
❑ Multi master(16)- Multi slave(16) shared bus.
❑ Dummy slave (default slave).
❑ Burst transfers for higher data throughput.
❑ Supports Split transactions.
❑ Single clock-edge operation.
❑ Pipelined Operation.
❑ Locked Operations.
❑ Exclusive Read and Write operations(AHB5)
❑ Non-tristate implementation.
❑ Wide data bus configurations (32, 64, 128, 256 bits, etc.).
AHB Architecture Components :
❑ AHB Arbiter – Grants bus access to masters.
❑ AHB Master – Initiates transactions (read/write).
❑ AHB Decoder – Directs transactions to the appropriate slave.
❑ AHB Slave – Responds to transactions.
AHB Protocol Components :
Arbitration in AHB :
❑ Each master asserts HREQUESTx to indicate it wants to use the AHB bus.
❑ The arbiter applies priority rules (Round-Robin or fixed priority).
❑ The arbiter asserts HGRANT3 (assuming Master 3 is selected).
❑ HGRANT3 is given to Address and Control MUX as a selection line.
❑ Based on HADDR the decoder select one of the slave(assuming Slave2).
❑ Now Slave 2 responds back. Once the transaction is completed, Master3
de-asserts HBUSREQ3.
Signals of AHB Protocol :
❑ ADDRESS AND CONTROL SIGNALS:
o HADDR: Address bus (transmits the address of the transfer).
o HTRANS: Transfer type (Idle, Busy, Non-sequential, Sequential).
o HSIZE: Transfer size (Byte, Half word, Word, etc.).
o HBURST: Defines the burst type (Single, Incrementing, Wrapping).
❑ DATA SIGNALS :
o HWDATA: Write data bus (from master to slave).
o HRDATA: Read data bus (from slave to master).
❑ HANDSHAKE AND CONTROL SIGNALS :
o HWRITE: Write enable signal (indicates write transfer when HIGH).
o HREADY: Ready signal (indicates if the slave is ready for the next transfer).
o HRESP: Response signal (OKAY, ERROR, RETRY, SPLIT).
❑ CLOCK AND RESET SIGNALS :
o HCLK: System clock for synchronization.
o HRESETn: Active-low reset signal.
Without Wait States With Wait States

AHB Pipelined Operation

Burst transfers and Data beats :
❑A burst transfer consists of multiple data beats, each representing a single
data transfer per one clock cycle. Num of beats depends on the burst type:
1. INCR4 /WRAP4→ 4 beats
2. INCR8 /WRAP8 → 8 beats
3. INCR16 /WRAP16 → 16 beats

Example - INCR4 Burst :

❑ Transfers 4 data beats in 4 clock cycles.
❑ Each beat transfers 1 word, depending on Hsize.
❑ This improves efficiency by reducing address overhead and ensuring
continuous data flow.
Transfer Types in AHB :
❑ Single Transfer :
o A single data word transaction.
❑ Incrementing Burst (INCR) :
o Address increases sequentially without
a fixed boundary.
o Used for accessing sequential memory
locations.
❑ Wrapping Burst (WRAP) :
o Address wraps around after reaching a
boundary.
o Optimized for cache line fills to reduce
memory latency.
Incrementing Burst & HSIZE :
❑ HSIZE (Transfer Size)Defines the data size per transfer.
HSIZE = 000 → 8-bit (1 byte)
HSIZE = 001 → 16-bit (2 bytes)
HSIZE = 010 → 32-bit (4 bytes)
HSIZE = 011 → 64-bit (8 bytes)
HSIZE = 100 → 128-bit (16 bytes)
❑ Example: INCR4 with 32-bit Bus (HSIZE = 010)
Starting Address: 0x1000
Next Addresses: 0x1004, 0x1008, 0x100C
❑ Example: INCR8 with 16-bit Bus (HSIZE = 001)
Starting Address: 0x2000
Next Addresses: 0x2002, 0x2004, 0x2006, 0x2008,
0x200A, 0x200C, 0x200E
Four-beat incrementing burst, INCR4 :
Wrapping Burst & Address Calculation :
❑ Boundary Calculation : Boundary Size = Burst Length × Data Size (HSIZE)
❑ Example: WRAP4 (4-beat burst, 32-bit bus, HSIZE = 010)
o Boundary Size: 4 × 4 bytes = 16 bytes
o Starting Address: 0x1010
o Next Addresses: 0x1014 → 0x1018 → 0x1000 (wraps)
The address wraps within 0x1000 – 0x101C.
❑ Example: WRAP8 (8-beat burst, 16-bit bus, HSIZE = 001)
o Boundary Size: 8 × 2 bytes = 16 bytes
o Starting Address: 0x2028
o Next Addresses: 0x202A → 0x202C → 0x202E → 0x2000 (wraps) → 0x2002 →
0x2004 → 0x2006. The address wraps within 0x2000 – 0x203E.
❑ Note :
o Start Address should align with the boundary size.
o Wrapping ensures efficient cache utilization by keeping transfers within a defined block.
Four-beat wrapping burst, WRAP4 :
AHB Split Transaction Significance :
Split Transactions in AHB vs APB :
❑ In APB, if PREADY is low, the transfer is stalled, blocking the bus until
PREADY becomes high.
❑ In AHB, with split transactions, if a slave is busy, it informs the master to
wait and releases the bus for other transactions.
Example: Split Transaction in AHB :
❑ Master requests a transaction → Sends address and control signals.
❑ Slave is busy → Sends HRESP=SPLIT, instructing the master to wait.
❑ Bus is released → Other masters can use the bus.
❑ Slave completes processing → Notifies the arbiter.
❑ Master resumes transaction → Completes the data transfer.
❑ Benefit : Avoids bus blocking, improving efficiency in multi-master
systems.
Purpose of HPROT Signals :
Response Signals in AHB :
❑ The HRESP[1:0] (Response Signal) is used by the slave along with HREADY to
indicate the status of a transfer.
❑ It determines whether the transfer is successful, retried, split, or has failed.
❑ Response Types :
o OKAY (00) – Normal successful transfer, with HREADY high.
o ERROR (01) – Transfer failure due to an error, requiring termination.
o RETRY (10) – Slave requests the master to retry the transaction later.
o SPLIT (11) – Slave delays completion but releases the bus for other masters.
❑ Two Cycle Responses :
o The ERROR, SPLIT and RETRY responses require atleast two cycles, then
additional wait states may be inserted at the start of the transfer.
o The two-cycle response is required because of the pipelined nature of the bus. By
the time a slave starts to issue either an ERROR, SPLIT or RETRY response then
the address for the following transfer has already been broadcast onto the bus.
Two cycle Retry and Split Responses :
Difference Between RETRY & SPLIT :
❑ RETRY (HRESP = 10)
The arbiter continues normal priority allocation.
The same master can attempt the transfer again based on priority.
❑ SPLIT (HRESP = 11)
The arbiter allocates the bus to any other master, even if lower in
priority.
The transfer resumes only when the slave asserts HSPLITx for the
original master.
The slave records the HMASTER[3:0] to track which master is
waiting.
Active Byte lanes for Little endian :
data bus

Active Byte lanes for Big endian :

Locked Transfers in AHB Protocol :
❑ What is a Locked Transfer?
o A locked transfer ensures that a master maintains exclusive bus control for a
sequence of transfers.
o Used to prevent other masters from interrupting critical multi-transfer
operations.
o Indicated by the HLOCKx signal.

❑ Role of the Arbiter :

o Ensures that no other masters are granted the bus until the locked sequence is
completed.
o Keeps the master granted for one extra transfer to ensure completion without
SPLIT or RETRY responses.
o Asserts HMASTLOCK to inform the slave that locked transfers must be
processed before granting the bus to another master.
AHB-Lite Protocol :
❑ AHB-Lite is a simplified subset of the AMBA AHB protocol.
❑ It is designed for single-master systems, eliminating the need for arbitration.
❑ Provides high-speed pipelined transfers between a master and multiple slaves.
❑ Key Features :
o Single Master – No arbitration logic needed.
o Burst Transfers – Supports incrementing, wrapping, and single transfers.
o Pipelined Operation – Ensures high throughput with address, data phases.
o Low-Latency Access – No arbitration overhead, reducing bus delays.
o Standardized Interface – Ensures seamless integration with AMBA-based designs.
❑ AHB-Lite Bus Architecture :
o Master – Initiates all transactions (CPU, DMA, etc.).
o Slave – Responds to requests (Memory, Peripherals).
o Decoder – Routes transactions to the correct slave.
o Multiplexer – Selects data from the addressed slave and forwards it to the master.
Advantages of AHB-Lite :
❑ Lower Power Consumption – No arbitration overhead.
❑ Simpler Design – Fewer components, reducing area and cost.
❑ High Efficiency – Optimized for single-master, embedded applications.
❑ Seamless AMBA Integration – Works smoothly with other AMBA
protocols like APB.
Applications of AHB :

❑ Used in high-performance SoCs.

❑ Connects CPUs, on-chip memory, and high-speed peripherals.
❑ Found in embedded systems, automotive ECUs, and more.
❑ Backbone for mobile, IoT, and embedded systems.
❑ Used in DMA controllers for high-speed data movement.
❑ Ensures low-latency communication in real-time systems.
❑ Integrated into networking hardware like routers and switches.
❑ Optimized for power-efficient embedded applications.

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