1: Introduction to AMBA AHB
Overview of AMBA:
Developed by ARM in 1996 to support modular,
reusable SoC design.
Ensures efficient and standardized communication
among IP blocks.
Purpose of AHB:
Supports high-speed, high-bandwidth communications.
Designed with pipelining and burst capabilities for
performance.
2: Types of AMBA Buses
ASB (Advanced System Bus): Legacy bus with
pipelined features.
APB (Advanced Peripheral Bus): Simple interface
for low-bandwidth peripherals.
AHB (Advanced High-performance Bus): Mid-level
bus supporting high data throughput.
AXI (Advanced eXtensible Interface): High-
performance, flexible, suitable for complex SoCs.
ATB (Advanced Trace Bus): Debug and trace-focused
communication.
3: Key Features of AMBA AHB
Pipeline Architecture: Allows overlapping address
and data phases.
Multi-master and Multi-slave Support: Facilitates
concurrent operations.
Burst Transfers: Enables multiple data transfers per
address phase.
Handshake and Error Handling: Maintains reliability
with signals like HREADY and HRESP.
4: Literature Review Summary
R Key
Authors Focus Area Tools
ef Findings
Deeksha L., AHB VHDL,
Area-speed
[1] Shivakumar Master/Slave Xilinx,
optimization
B.R. Design ModelSim
Mamta B.
Memory Verilog, 15 mW,
[2] Savadatti et
Controller Xilinx 114.705 MHz
al.
Poorani P.,
Delay
[3] Vijayashree - 4-cycle delay
Analysis
B.M.E.
Javier Jalle, 57.142 ns,
[4] Arbitration -
Jaume Abella 17.5 MHz
Hitanshu Improved
Master FSM
[5] Saluja, N. Verilog time/area
Design
Grover efficiency
Bus System 24% energy
[6] Deepti V.D.
Encoding Verilog savings
5: AMBA AHB Architecture
System Components:
Masters: Initiate and control data transactions.
Slaves: Execute operations based on master's
requests.
Arbiter: Manages bus access among masters.
Decoder: Maps addresses to appropriate slave
devices.
Design Highlights:
Modular, scalable topology.
Supports advanced transactions: burst, split.
Pipelined design improves data throughput.
6: Operational Workflow
Phases:
Address Phase: Bus master sends address and control
information.
Data Phase: Data is either read from or written to
slave.
Efficiency Aspects:
Pipelined operation enhances speed.
Handshake (HREADY, HRESP) ensures proper
synchronization.
Reduces idle cycles for improved performance.
7: Master Interface
Signals Used:
HBUSREQ / HGRANT: Request and grant signals.
HADDR / HWRITE / HSIZE: Specify address,
write/read mode, and data size.
HWDATA / HRDATA: Carry write/read data.
Functional Steps:
Master requests bus, sends address and control info,
transfers or receives data.
8: Slave Interface
Signal Functions:
HSEL: Identifies selected slave.
HREADY: Indicates transaction readiness.
HRESP: Acknowledges success or error.
Operational Role:
Decodes command and addresses.
Exchanges data and updates status based on the
request.
9: Conclusion
Key Takeaways:
AMBA AHB protocol is critical for efficient, scalable
communication in embedded SoCs.
It supports high-performance data transactions with low
latency.
Widely applicable in automotive, consumer electronics,
and industrial systems.
Features like pipelining, arbitration, and burst support
enhance throughput and system efficiency.