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Phase detector for data-clock recovery circuit

Article in Electronics Letters · March 2002

DOI: 10.1049/el:20020109 · Source: IEEE Xplore

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 Given a, b, k,, k, and x s R , a k,-valued literal and k,-valued independent of the technology used and operates faster than
complementary literal operations are defined as switched-current mode designs.
kl ifasxsb
L(hUxb) = 0 [ otherwise
(4)
Acknowledgment: This work is sponsored by the BogaziCi University
Research Fund (01HA201).
0 ifasxsh
C L ( k c . a x b ) = k, { otherwise
$3 TEE 2002 4 November 2001
respectively. Considering the logic level definition in (2), wc propose Electronics Letters Online No: 20020127
the structure shown in Fig. 3 to implement the above operations DOI: IO.I049/el:20020I 2 7
simultancously from thc same circuit with quantities normalised to Ib.
T. Temel and A. Morgiil (Electrical Engineering Department,
Owing to space limitation only the block diagram is given. The internal
Bogazici Univemi~,Dtanbul, Turkey)
circuits are similar to the circuit of Fig. 2. Repeated quantities can be
rcproduced through proper mirror circuits. E-mail: temeltur@boun.edu.tr

References
1 JAN, A.K., BOLTON, R.J., and ABD-EL BARR, M.H.: ‘CMOS multiple-valued
logic design (Parts I and II)’, IEEE Trans. Circuits Sysr., 1993, 40, (8),
pp. 503-532
2 DAO, T.l:, RUSSELL, L.K., and MCCLUSKEY, E.J.: ‘Multi-valued integrated
injection logic’, IEEE Trans. Comput., 1977, C-26, (12), pp. 1233-1241
3 WAHO, T., CHEN, K.J., and YAMAhlOTO, M.: ‘Resonant tunneling diode and
HEMT logic circuits with multiple thresholds and multilevel output’,
IEEE J. Solid State Circiits, 1998, 33, (2), pp, 268-274
4 FRBITAS, D.A , and CURRENT, K.w.: ‘A CMOS current comparator circuit’,
Electron. Lett., 1983, 19, (17), pp. 695-696
5 ONh’EWEER, S.P.,and KERKHOFF, H.G.: ‘High-radix current mode circuits
Fig. 3 Current-mode iniplenientotion(if literal und complementary literal based on the truncated difference operator’. 17th ISMVL Conf. Proc.,
operations May 1987, pp. 188-195
6 ALLEN, C M.,and GIVONE, D.D.: ‘A minimization technique for multiple-
The circuit is designed with Mietec’s ES2 0.7 pm HSPicc (level 6) valued logic systems’, IEEE Trans. Comput., 1968, C-17, pp. 182-184
parameters in full-extraction for 2.7 V power supply voltage. HSPice
simulation results arc shown in Fig. 4. The topologies proposed are
compared with [l] using a switching transistor with body bias/no body-
bias conditions. The functions L(5, ’.2)and CL(3,’2) are implemented
using the same design parameters. The results are summarised in Table Phase detector for data-clock recovery
1 rrom which it can be seen that the proposed circuits operate fastcr circuit
with almost the same design costs.
A. Hati, M. Ghosh and B.C. Sarkar
801
A new type of phase detector which can be used in data-clock
recovely circuits is reponed. The main feature of the proposed
phase detector is that it is frce from data dependent jitter, which is
the main problem with the Hogge phase detector.

I
Introduction: Data clock recovery (DCR) circuits find wide applica-
tion in modem communication systems [l]. The performance of the
a
phase-locked loop (PLL)-based DCR circuit depends greatly on the
801
structure of the phase detector (PD) used in the loop. Different types
of PDs are suggestcd in the literature, among them the Hogge PD
I CL(3.393#
(HPD) is well known [2, 31. However, the main problem with the HPD
is that the output terminals do not assume fixed states even in the
condition of phase matching of the two inputs to it. Thus, when the
charge pump filter converts the HPD output state to analoguc control
0 li5 2jO 3j5 500 615 750 8j5 1000 voltage a train of special shaped pulses is present in the control
time, ns voltage, when applied to the voltage-controlled oscillator (VCO) used
b in the HPD-based PLL, and the output of the VCO is found to be
spectrally impure owing to these fluctuating control voltages, even in
Fig. 4 Simulalion results the locked state of operation of the PLL. To get rid of this problem, in
a ~ ( 5’2)
. this Letter a new type of PD with improved performance is proposed.
h CL(3, 3x5)
The structure of the new PD is very simple and is based on common
logic gates. The control voltage of the VCO with the new PD is
Table 1: Simulation results of proposed and switched-current completely frce from thc perturbing pulses, which is thc merit of the
mode designs for literal operations proposed structure.
Gate No, of Avcrage Average power
~~~
transmissions delay, ns dissipated, m W
23 4.3 0.50 circuit
Ref. [4] 21 7.1/6.2 0.42/0.46
CL(3, ‘2) This study 19 4.1 0.43
Ref. [4] 21 6.816.3 0.42j0.40 clock
signal
vco
charge pump
Conclusion: We have described a novel realisation of multi-valued filter output
logic literal and complementary literal operations. The new design is
based on a current-mode threshold circuit. The gate design is Fig. 1 Block diagram uf PLL-bused clock recovery circuit

ELECTRONICS LETTERS 14th February 2002 Vol. 38 No. 4 161

 I I
are low. Similarly it can he shown that when v, leads v2 then Uwill be
a positive pulse of width proportional to thc phase error between v1
and v2 and D will always be low and vice versa when v1 lags v2. Thus,
U and D outputs of the NPD can be low simultaneously or either onc

w,
alone can be high, but both can never be high simultaneously. In the
DCR circuit, a charge pump circuit is employed to convert the digital
I I signals Uand D into pump current (T,) and the loop filter (integrator)
then converts this current into an analogue voltage. Whenevcr v I and
v2 are aligned, no current will flow and as a result there is no net
CLK2
change in output of the loop integrator. However, when v i lcads (lags)
v2, +J, (-I,,) current will flow for a period proportional to the phase
[ - error between v1 and v2,thus the output of the loop integrator exhibits
a net increase (decrease). This control voltage will lead the VCO to
become locked to the input signal (vl). Since the control voltage
Fig. 2 Hardware structure of new phase detector remains unchanged in the phase-locked condition of vi and v2, the
spectral purity o f the VCO output will improvc, this being the mcrit of
v1 1 m I i n the proposed structure.
v2 flflflflflfiflflflflflflflflflflflflflflfiflflfl
Ql(F1) --i I Experimenful results: An experiment was performed using available
Q2(F2) 1 rl I IC building blocks to examine the responses of DCRs using the NPD
-
QZ(F2) u I or thc HPD. 4 pseudorandom noisc (PN) scquencc gencrator imple-
v3 q- n n n n mcnted using a linear fcedback shift register (LFSR) algorithm was
v4 T U u U u u u used to simulate the randomly varying zero-one sequence to be treated
v5 as the input data stream. The experimental DCRs regenerated the
U
D clock signals of the input PN sequcnce. The spectrum of the VCO
a
output from the DCR using the HPD is shown in Fig. 4u, which
vi 1 m I L n contains spurious components owing to thc prescnce o f jitter in the
v2 P- control signal, whcreas Fig. 4b shows the spectrum of VCO output
Qi(F1) 7 1 from the DCR using the NPD. The superiority of the DCR using the
QZ(F2) 1 m r NPD is quite evident from Figs. 40 and b.
a2(F2) 1 I mkr 1 249.9 kHz
v3 n n n n n ref 0 dBm atten l O d B -20.57 dBm
v4
U L : u u peak
n - 1 loa

-
"5
U n n n n n n
D
b
VI 1- m i
v2 P
Q1 (Fl) -1 n I
QW2) 1 I
-
QZ(F2)
nu nun n
I
n n n
v3
"4
u u U u u u start 100 kHz stop 375 kHz
v5
n n n n n n res BW 3 kHz VBW 3 kHz sweep 91.67 ms (401 pts)
U a
D J L n
~ ~ n n n n mkr 1 249.9 kHz
C
ref 0 dBm atten 10 dB -20.78 dBm
peak I I
Fig. 3 Timing diugrum of signuls at dijferent points of proposed phase log
10 dBi
detectors
a Input signals, v , and v2, are in the same phasc
b v , leads v2
c 1'1 lags 1'2
WlS2
53 FC
Structure und operation of new, PD: The block diagram of the PLL- AA
based DCR circuit is shown in Fig. I , while Fig. 2 shows the hardware
structure of the proposed new PD (NPD). It comprises two D-flip- ~

flops (F1 and F2), three EX-OR gates (El, E2 and E3), two AND start 100 kHz stop 375 kHz
gates (G 1 and G2) and one NOT gate. It compares thc phascs of the res BW 3 kHz VBW 3 kHz sweep 91 6 7 ms (401 pts)
two inputs v , and v2 where v1 is an unequal density zcro-one data b
stream and v2 is a locally regenerated VCO signal (a rectangular Fig. 4 Power .spectrum of wgeneruted reference signal obtained at loop
waveform of 50% duty cycle). The operation of thc NPD in open loop VCO output in CKC circuit
condition can he understood with the help of timing diagrams for
a HPD
different phase relations between v l and v2 given in Figs. 3a, h and c. b NPD
At the rising instants of thc v2 (Le. when it changcs from 0 to I ) the
statc of v I (0 or 1) will he transferrcd to the output Q1 (Q2) of F1 (F2) Conzmentc.: A new typc of phase dctector is proposed. The new
and will remain unchanged till the next rising instant of V I . The structure is easy to implement and requires only a Iew logic gates
output of E2 (v4) is high only when the output of F1 (Ql(F1)) and the in comparison to the HPD. In the NPD-based DCR circuit, the loop
output of F2 (Q2(F2)) are both the same (i.e either high or low) and it VCO control voltage is free from any variation in the locked state o f
will remain zero for a period cqual to the half period of v2. The output operation. Thus, this structure can be very useful in designing jitter-
v3 of E l is a positive pulse for each transition instant of v1 . but its free data and clock recovery circuits having spectrally pure outputs.
width depends on the phase error between vI and v 2 , The output v j of The results of the experiment performed at lowcr RF hands support
G1 is high only when w3 and v4 are both high. When vI leads (lags) vz, the claim of superiority of the NPD. Since thc constituent IC building
the width of v3 is greater (less) than half period of v2 and if vI and v2 blocks (FFs, VCO, etc.) are available at higher ends of the RF
are aligned, the width of v~ is equal to that of half period of v2. spectrum, the NPD-based systems can he designed at that frequency
Therefore, when v1 and v2 are aligned the outputs Uand D of the NPD region also.

162 ELECTRONICS LE77ERS 14th February 2002 Vol. 38 No. 4

 Co IEE 2002 17 September 2001 Table 1: Description of various memory organisation schemes
Electronics Letters Online No: 20020109
DOI: IO.1049/el:20020109 Address Coefficient 16-bit qoantised Our Olhers
set coefficient scheme schemes
A. Hati, M. Ghosh and B.C. Sarkar (Phy.yics Department, Burduun I (rcal, imaginary) I values
University Burdwan- 713 104, We,vt Bengal, India)
0001 .98, -.19 7d89, e706 Block
References 00 10 .92, -.38 7641, cm4
1 LEE, T.H., and BULZACCHBLLI. J.F.: ‘A 155-RIHz clock recovely delay and .83, -.55 6a64 bSe3
Block
phase locked loop’, lEEE J. Solid-Smte Circuits, 1992, 27, (12), 0100 .71, -.71 SaX2, aS7d
A
pp. 1736-1745 0101 .55. - 3 3 471c., 9592
-~
2 HOGtiE, C.R.: ‘A self correcting clock recovery circuit’, J Lightwave 0110 .38, -.92 30th. 89be Block
Technol., 1985, LT-3, (6), pp. 1312-1314 0111 .19, -.98 IXfY, 8276 11
3 SARKAR, B.C., and HATI, A,: ‘PLL-based frequency synthcsiscr witbout I000 0.0. -1.0 0000. xom
using the frequency divider’, IEE PTUC., Circuits Devices S’st., 148, ( 5 ) .
-.19, -.19 e706, 8276
pp. 255-260
- .38, -.92
- .55, -23 b8e3, 9592
Block
-.71, -.71 a574 a57d B
- 83. - 3 5 9592~,hXe?
..

Scheme for reducing size of coefficient 1110 I - 92, -.38 I X9bc, cfu4
Ill1 I -98-19 I mx
memory in FFT processor
M. Hasan and T. Arslan Let the complex coefficient values in tcrms of the real and imaginary
parts he reprcscnted as in (I):
Long fast Fourier transforms (FFTs) are required in applications such
as orthogonal frequency division multiplexing, radars and sonars. It i s zbg = R,, +i& (1)
highly desirable to reduce the sizc and power requirements of the FPT
so as to realise singlc chip long FFT-based systems targeting portable where b indicates the memory block numbcr and g is an index which
applications. Presented hcrc i s a novel technique to reduce the points to the coefficient values within individual blocks. The first
coctficient memory almost by a factor of four by exploiting the coefficient value in each block has an index g equal to zero. The first
relationships among the coefficicnt valucs thereby significantly block coefficient values are obtaincd from (1) by replacing h with I as
reducing the arca and power requirements of the hardware. shown in (2):
Introduction: The area and power consumption are of prime impor- zlg= +JIl, 0 5 g 5 N/8 (2)
tancc in portable telecommunication applications. Fast Fourier trans-
form (FFT) has to be computed in many of these applications. Long Let the coefficient memory addrcss generated and the actual block
FFTs are common in orthogonal frequency division multiplexing address be represented by an n-bit array A, and an (n - 1) bit array A,
(OFDM), radars and sonars, etc. Hence, it is very important to respectively. The coefficicnt memory block address is always 1 bit less
minimisc FFT hardware for its further area and power efficient than the conventional memory address as the block size is limited to
realisation. The numbcr of coerficients in a radix-2 FFT is equal to ((N/8)+ 1) instead of N/2. The corresponding addrcsses of the
N/2, where ‘N’ is the length of the FFT. The coefficient memory coefficient values in the first block are given by the following equation:
required to store thesc cocfficients will thus require N/2 locations ,4,,[n - 2 : 01 = A,[n - 2 : 01
where each location stores the real and the imaginary part of the
coefficient in a conventional implementation: here we term it Conv [i]. where n = logz (N/2), 0 sg 5 N / 8 and 0 5 m 5 N/8.
Ma and Wanhammar [Z] and Chang and Parhi [3] proposed that the sizc The second block coefficient values can be obtaincd in terms of the
of the coefficient memory can he cut to half (N/4) by exploiting the first block coefficient values by performing the following substitution
correlation among the coefficicnt values: here we term it Others. In this
Letter we present a novcl technique to reduce the size of the coefficient g + (N/X - 1 - g). The symbol -
in the right-hand side of (2): R1+ -Il, 11+--Rl and
here corresponds to a Complement
opcration. This can also be verified from Table 1, The resulting equation
memory by almost a factor of four ((N/X)+ I ) . We provide results
demonstrating that by adopting Our technique the savings in area and is as follows:
power will be substantial for long FFTs in different types of realisa-
tions compared to the Others memory-based techniqucs. Zz, = [-4 [.v18-I),- I +.A--R I ( w - I -,q) 1
0 5 g 5 ( ( N / 8 )-2)
Scheme description: The FFT coefficients are expressed as follows:
When the coefficient memory addrcss generator proceeds to generate
W, = exp(-jZIIk/N) the addrcss in the second block, the corresponding address in the first
where k varies from 0 to N/2 - I giving rise lo N/2 coefficients for an block (only Block 1 is stored) are obtained by taking the 2’s complement
N-point FFT where ‘W indicates the number of data points or the of the cocfficient memory address as follows:
length of the FFT. The values of the cocfficients for a 32-point FFT in A,, = -A,[n -2 : 01 +1 0 5 g 5 ( ( N / X )- 2 )
2’s complement form are given in Table 1. The partitioning of
coefficients into blocks (as shown in Table 1) is applicable to all W/8) + 1) 5 m 5 (@“4) - 1)
FFT lengths. Others proposed to divide the memory into two identical Similarly, the coefficient values in thc third block are obtained from thc
blocks, namely A and B. It is clcar that the coefficient values in block first block coefficient values using (2) as follows:
B can be generated from those in block A by interchanging the real
and imaginary parts of the coefficients and by also complementing the 4, = [I~,I+.j[--Rj,I 0 5 g 5 N/8
rcal part before its assignment to the imaginary part corresponding to
When the coefficient memory address generator proceeds to generate
block B. Hence, only block A needs to be stored. In Our technique,
the addresscs in the third block, the corresponding first block addresses
the memory is partitioned into four blocks (Block I to Block IV)
arc obtained as follows:
rather than two, as shown in Table 1. The memory size in Our scheme
is reduced to ( ( N / 8 )+ 1) locations (only Block I is needed) from the A,, = A,,[iz - 2 : 01 0 5 g 5 N / X , N / 4 5 m 5 3N/X
N / 4 locations proposed by Others schemes (only Block A is needcd).
Using Our scheme, therc is a nced to store only coefficient values in Similarly, the fourth block coefficient valucs arc obtained in terms of
Block I and the rcst of the coefficient values in other blocks and their the first block coefficient values again using (2) as follows:
corresponding first block addresses can be generated by following thc
gencral procedure given below. This procedure can he explained with
the help of a 32-point FFT example given in Table 1.

ELECTRONICS LETTERS 14th February 2002 Vol. 38 No. 4 163

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