Hindawi Publishing Corporation

Journal of Electrical and Computer Engineering

Volume 2016, Article ID 8202581, 9 pages
http://dx.doi.org/10.1155/2016/8202581

Research Article
A Low Noise, Low Power Phase-Locked Loop,
Using Optimization Methods

Noushin Ghaderi, Hamid Reza Erfani-jazi, and Mehdi Mohseni-Mirabadi

Faculty of Engineering, Shahrekord University, Shahrekord 8818634141, Iran

Correspondence should be addressed to Noushin Ghaderi; ghaderi.nooshin@eng.sku.ac.ir

Received 6 April 2016; Accepted 17 August 2016

Academic Editor: M. Jamal Deen

Copyright © 2016 Noushin Ghaderi et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
cited.

A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase
frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven
Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output
swing and high current matching. The designed PLL is utilized in a 0.18 𝜇m CMOS process with a 1.8 V power supply. It has a wide
locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the
overall jitter is decreased significantly.

1. Introduction in the charge pump circuit. Reference spurs and phase offset
are due to the current mismatch while the variations of
The role of a phase-locked loop or a delay-locked loop (DLL) the PLL loop bandwidth are caused by the variations of
is to generate a clock signal which is usually a multiple of a the output current amplitude. If the current matching and
reference clock and is synchronized with the reference clock control voltage range of a charge pump circuit increase
in phase. They are extensively utilized in many applications simultaneously, then the locking range frequency of the PLL
including clock data recovery systems and frequency synthe- will increase considerably.
sis circuits. In this paper a wide dynamic output voltage range,
One of the most important components of the PLL and high impedance, and low power charge pump based on
DLL, which is often considered as the bottleneck, is the a novel bulk driven Wilson current mirror is presented.
phase frequency detector (PFD). The limited speed of this Some optimization algorithms are employed to improve the
block is the main limiting factor in the data rate of the efficiency of the circuit.
PLL. In high frequencies, the PFDs cannot follow the phase
differences between reference and feedback clocks. Therefore,
a frequency divider circuit is often inserted before the PFD 2. Proposed PFD
block in the feedback path of the PLL. It means that the
input clock frequency of the PFD is reduced. However, by The PFDs detect a phase error signal which is passed through
adding the divider circuit, the overall jitter of the PLL will a loop filter to control the delay of a controllable delay
extremely increase. Thus, by designing a high frequency PFD, line. Therefore, in addition to determination of accuracy,
the divider circuit will be omitted and the noise behavior of a PD plays a key role in the speed and efficiency of PLL’s
the PLL will be improved [1]. performance.
Another important component of the PLL is charge pump A closed loop is the general structure used in the PFD
circuit. It converts the output signal of PFD into an accurate because it is simple, easy to implement, and immune to the
amount of current. In practice, there are some nonidealities dead-zone problem. Because of the feedback path, however,
2 Journal of Electrical and Computer Engineering

it has a limited speed which confines its usage in high speed In Figure 2(c), 𝐴 leads 𝐵. As can be seen, just after the
circuits. Furthermore, some rising edges can be missed in the rising transition on 𝐴, 𝐴 signal will be set to the high value
detection when the edges are overlapped with the reset signal while 𝐴 𝑑 , which is the delayed waveform of 𝐴 signal, still
[2]. Till now many circuits have been suggested to make the remains at the low value. Therefore, 𝑀1 and 𝑀2 turn on and
feedback path faster [3–6]; however the feedback path still the Up output will be set to the high value. In the same way,
remains in all of them which causes a reduction in the speed. just after the rising transition on 𝐵, 𝑀5 and 𝑀6 turn on,
Authors in [7] proposed an open loop PD to achieve a consequently setting the Down output to the high value. With
high speed performance, without the issue of the reset signal. rising transition on 𝐵𝑑 , both of the Up and Down outputs
However, the PFD circuit tends to dissipate crowbar current return to the low value. The circuits operate in the opposite
when both input signals are high. It means that the circuit has manner when 𝐴 lags 𝐵 as shown in Figure 2(d).
some extra average DC power consumption. According to [19], the time which is taken by the signal
The proposed circuit with a very simple structure solves to change from low (high) value to 70% (30%) of high (low)
the above problem. Furthermore, the proposed circuit solves value of logic states is called the gate rise time (or fall time).
the dead-zone and missing edge problems completely. In this circuit, rise time and fall time make 𝑇chp .
The task of a PD circuit is to compare the rising edge of The sum of output rise time and fall time is calculated
two inputs (𝐴 and 𝐵 in Figure 1) and generate a signal which to estimate the maximum operational frequency of the
is set to a high value with the rising edge of the first input and proposed PFD.
then is reset to a low value with the rising edge of the second
one. 𝑡rise(fall) = 1.2𝜏rise(fall) ,
Figures 1(a) and 1(b) show the proposed PD, for Up and
Down paths, which indicate two symmetrical and very simple 𝜏rise(fall) = 𝑅eqrise(fall) 𝐶𝐿
circuits for Up and Down signals. The waveforms of the PD
are shown in Figures 1(c) and 1(d). In Figure 1(c), 𝐴 leads 𝐵. If 𝑅eqrise = 𝑟𝑜1 + 𝑟𝑜2 ,
initially 𝐴 = 0 and 𝑉(𝐶1 ) = 𝑉dd , then a rising transition on 𝐴 (1)
𝑅eqfall = 𝑟𝑜3 + 𝑟𝑜4
leads to charge the output capacitor through 𝐶1 . Therefore,
the Up output node will be set to the high value. The Up 𝐶𝑑𝑔2 𝐶Not 𝐶𝑑𝑔3 𝐶delay
node stays in this state until rising transition on 𝐵. On the 𝐶𝐿 = 𝐶𝑑𝑏2 + 𝐶𝑑𝑏3 + +
𝐶𝑑𝑔2 + 𝐶Not 𝐶𝑑𝑔3 + 𝐶delay
other hand, at the Down circuit with 𝐴 at the high value,
the 𝑀6 transistor will be on, keeping the down output at 𝑇chp = 𝑇rise + 𝑇fall ,
the low value. After the rising transition on 𝐵, 𝑀5 will turn
on, causing the 𝐶2 capacitor to discharge to the ground. where 𝜏 is considered as time constant, 𝑅eq is the equivalent
Therefore, when 𝐴 returns to the low value and 𝑀6 turns off, resistant of the charging or discharging path at the output
Down output will remain at zero value. The circuits operate node (UP or DN), 𝐶𝐿 is the output equivalent capacitance,
in the opposite manner when 𝐴 lags 𝐵 (Figure 1(d)). 𝐶delay is the delay gate, and 𝐶Not is the Not gate equivalent
As can be observed, the above circuit is extremely simple capacitances.
and fast. Furthermore, due to the use of only three transistors By calculating the above equations, 𝑇chp is obtained as
in each path, the power consumption is considerably low. But 48.33 ps. Figure 3 shows that the dead zone is compensated
the proposed PD still suffers from the following problems. by delay gates through the Not gate and precharging time.
The first problem is as follows: Since the parasitic capac-
itance of 𝐶1 node is smaller than the parasitic capacitance of 𝑇chp = 𝑇delay − 𝑇Not . (2)
the output node, the output node will not be charged through
this node completely. Adding an additional capacitor to the 𝑇Not and 𝑇delay are delay times caused by Not gate and delay
𝐶1 node will add some problems such as extra chip area and gate, respectively. The values of 𝑇delay and 𝑇Not are obtained as
longer rise and fall time. 64.43 ps and 16.1 ps, respectively. It means that the dead zone
The second problem is its dead-zone problem. This is entirely removed.
problem may occur when the inputs have a very small phase It is evident that the delay time in Figure 3 cannot exceed
difference. Therefore, the output pulse may not find enough the value of 3/4 of the clock pulse width. Therefore, the
time to turn on the charge pump switches. To overcome the minimum value of pulse width is 85.9 ps. As a result, the
above two problems, the proposed PD is modified as shown maximum frequency of the proposed PFD is obtained as
in Figure 2, in which 𝐴 𝑑 and 𝐵𝑑 are delayed waveforms of 𝐴 5.82 GHz.
and 𝐵 signals. The ideal waveforms of two outputs are also The proposed PD is simulated in 0.18 𝜇m CMOS tech-
shown in this figure. nology by HSPICE software using level 49 parameters. The
Circuit performance is as follows: by delaying 𝐴 and 𝐵 results are drawn in Figure 4 using MATLAB software. The
signals on gates of 𝑀1, 𝑀4, and 𝑀3, the zero value of “up” figure shows the difference between average values of Up and
signal will occur a few seconds later. As a result, a high level Down signals versus the phase difference of two inputs at
of “up” signal will become wider than the real amount and six different frequencies, 1–100 MHz, 1 GHz, 3 GHz, 4 GHz,
the phase difference will be shown more extensive than the and 5 GHz. Since the nonlinearity of the characteristic at
actual value. This amount of broadness must be equal to the the high frequency happens at large phase differences, where
precharging time (𝑇chp ) of the internal parasitic capacitances. the polarity is more important than the magnitude, this
Journal of Electrical and Computer Engineering 3

Vdd Vdd

A B
M1 M4
C1 C2
A B
M2 M5

A A
Up Down
B B
B A
M3 M6 Up
Up

Down Down
(a) (b) (c) (d)

Figure 1: Proposed PD: (a) Up path. (b) Down path. (c) The waveforms of the PD when 𝐴 leads 𝐵; (d) when 𝐴 lags 𝐵.

Vdd Vdd
Ad Bd
M1 M5

A B A A
M2 M6
Up Down Ad Ad
B B
Bd Ad
M3 M7 Bd Bd

M4 M8 Up Up

Down Down

(a) (b) (c) (d)

Figure 2: Modified PD: (a) Up path. (b) Down path. (c) The ideal waveforms of the modified PD when 𝐴 leads 𝐵; (d) when 𝐴 lags 𝐵.

A
1.5
TNot TNot
Up − Down

1
Ad
Tdelay Tdelay 0.5

Bd 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Tdelay Tdelay Phase difference (∗ pi)

1–100 MHz 3 GHz

Up 1 GHz 4 GHz
Trise Tfall Trise Tfall 2 GHz 5 GHz

Figure 4: Difference between average values of Up and Down

signals versus the phase difference of two inputs.
Down
Tchp Tchp

Figure 3: The realistic waveforms of the modified PD.

of the PLL. The region around zero phase difference shows
the accuracy of the PFD even at 5 GHz frequency. The power
consumption of the proposed PD at 5 GHz frequency is about
nonlinearity can be ignored. The diagram should be linear 0.3 mW. Table 1 summarizes these results and presents a
in small phase differences to minimize the locking time jitter performance comparison among this work and others.
4 Journal of Electrical and Computer Engineering

Table 1: Performance comparison of the proposed phase detector.

Performance parameter [3] [8] [9] [10] This work

CMOS tech 0.13 𝜇m 0.35 𝜇m 0.18 𝜇m 0.13 𝜇m 0.18 𝜇m
Supply 1.2 v 3.3 v 1.8 v 1.2 v 1.8 v
Max freq. (GHz) 2.94 0.1 1 2.1 5 GHz
Dead-zone NA NA Free NA Free
Power cons. (mW) 0.496 @ 128 MHz NA NA NA 0.3
Structure Closed Open Closed Open Open

Iout
Iin /K Iin Iin /K

M3p M6p
M9p
M1n M2n M4n M5n
UPb M3s
M4s UP M4p
M7p
M8p M1p M2p M5p

M3n M6n Iin Iin Icharge

Iin /K Iin /K Iin /K

Out
Figure 5: Proposed high swing Wilson current mirror.
Iin Iin /K Iin /K Iin Idischarge Iin /K

M8n M1n M2n M5n

M7n M4n
M2s DNb
3. Proposed Charge Pump Circuit DN M1s

One of the most important components of the PLL is the M9n M3n M6n
charge pump circuit. An adaptive body bias charge pump cir-
cuit is proposed in [11]. In this circuit a number of resistances
are used to compensate current variation. However, multiple
parameters, such as temperature and fabrication, change the Figure 6: Proposed charge pump circuit.
value of these resistances and are not reliable. The charge
pump presented in [12] has used a compensation method to
reach a high output swing. However the circuit structure is
complicated. Moreover, in this circuit the power supply and The proposed charge pump circuit is indicated in Fig-
hence the power consumption are placed high to achieve a ure 6. In this circuit 𝑀1s and 𝑀3s which are controlled by
high output swing. In order to increase the output voltage DN and UPb, respectively, act as charge pump switches. 𝑀2s
swing of the charge pump, in [13] a bulk driven method in and 𝑀4s are working for faster and better switching. When
a cascade structure has been used. However, using a cascade these MOSFETs turned on, the gate’s capacitor of 𝑀4𝑛 or
structure sets limitation to output swing. 𝑀4𝑝 will be discharged and turn off faster.
A novel bulk driven, low voltage charge pump for high In the proposed circuit 𝑀7𝑛(𝑝)–𝑀9𝑛(𝑝) are used to con-
performance PLLs is proposed in this paper. This charge nect the bulk terminals of 𝑀4𝑛(𝑝) and 𝑀6𝑛(𝑝) to a higher
pump is designed based on Wilson current mirror by a novel voltage in comparison with the circuit of Figure 5. It means
bulk driven method. Output resistance and output swing are that the source-bulk voltage (𝑉SB ) is decreased. Therefore,
increased simultaneously. according to (3), the threshold voltage (𝑉𝑇 ) is reduced too.
The charge pump circuits must be designed to have a high Equations (4) and (5) indicate that, by decreasing 𝑉𝑇 , 𝑔𝑚 and
output swing. However, there are some limitations in output 𝑔𝑚𝑏 are increased and 𝑟𝑜 is decreased.
swing, especially when transistors are placed in cascade
form, to obtain the high output impedance. To overcome
the above problem, bulk driven technique is employed in 𝑉𝑇 = 𝑉𝑇0 + 𝛾 (√𝜑𝐹 + 𝑉SB − √𝜑𝐹 ) , (3)
the proposed circuit. The proposed charge pump circuit is
designed based on Figure 5. This circuit is a modified version 𝑊
of a super-Wilson current mirror [20]. As can be seen, the 𝑔𝑚 = 𝜇𝐶𝑜𝑥 (𝑉 − 𝑉𝑇 ) ,
diode connection transistor of an ordinary circuit is replaced 𝐿 GS
(4)
with a cascade one. Therefore, the loop gain is increased by a 𝛾
𝑔𝑚𝑏 = 𝑔𝑚 ,
factor of 𝑔𝑚1𝑛 𝑟𝑜1𝑛 𝑟𝑜3𝑛 . 2√𝜑𝐹 + 𝑉SB
Journal of Electrical and Computer Engineering 5

2 and the position of particle which has the lowest cost function
𝑟𝑜 = 2
. (5)
𝜇𝐶𝑜𝑥 (𝑊/𝐿) (𝑉GS − 𝑉𝑇 ) is saved in 𝐺best . The next vector of each particle depends on
its position and its distance to its 𝑃best and its distance to 𝐺best .
In (6), by increasing 𝑔𝑚𝑀4𝑛 and 𝑔𝑚𝑏𝑀4𝑛 and decreasing 𝑟𝑜𝑀4𝑛 The relations of particles movements are as follows:
and 𝑟𝑜𝑀6𝑛 , the output voltage swing is extremely increased.
𝑖+1 𝑖 𝑖
𝑉𝑛𝑚 = 𝑤 × 𝑉𝑛𝑚 + 𝐶1 × rand () × (𝑃best𝑛𝑚 − 𝑋𝑛𝑚 )
𝑉out min = 𝑉DS𝑀4𝑛 (sat) + 𝑉DS𝑀6𝑛 (sat)
𝑖
+ 𝐶2 × rand () × (𝐺best − 𝑋𝑛𝑚 ),
𝑉DS𝑀4𝑛 = [𝐼discharge − (𝑔𝑚𝑀4𝑛 + 𝑔𝑚𝑏𝑀4𝑛 ) 𝑉𝑔𝑠4 ] 𝑟𝑜𝑀4𝑛 , (6) (8)
𝑖+1 𝑖 𝑖+1
𝑋𝑛𝑚 = 𝑋𝑛𝑚 + 𝐶𝑉𝑛𝑚 ,
𝑉DS𝑀6𝑛 = 𝐼discharge 𝑟𝑜𝑀6𝑛 .
󵄨󵄨 𝑖+1 󵄨󵄨
󵄨󵄨𝑉𝑛𝑚 󵄨󵄨 ≤ 𝑉max ,
󵄨 󵄨
Output resistance is equal to
where 𝑉max indicates a parameter that prevents going out
𝑅out ≈ [(𝑔𝑚1𝑛 + 𝑔𝑚𝑏1𝑛 ) 𝑟𝑜1𝑛 𝑟𝑜3𝑛 (𝑔𝑚4𝑛 + 𝑔𝑚𝑏4𝑛 ) 𝑟𝑜4 ] of suitable search space which causes the solution to be in
󵄩 (7) acceptable region; 𝐶1 and 𝐶2 are constants which represent
⋅ 󵄩󵄩󵄩󵄩[(𝑔𝑚1𝑝 + 𝑔𝑚𝑏1𝑝 ) 𝑟𝑜1𝑝 𝑟𝑜3𝑝 (𝑔𝑚4𝑝 + 𝑔𝑚𝑏4𝑝 ) 𝑟𝑜4𝑝 ] . the speed of learning or pulling to 𝑃best and 𝐺best , and the
weighing function 𝑤 is given by
One of the most important issues in bulk driven circuits
is nonideal behavior of the MOSFETs due to their channel 𝑤max − 𝑤min
𝑤 = 𝑤max − × iter, (9)
formations. The operation of the bulk driven MOSFET is itermax
similar to a Junction Field Effect Transistor (JFET). Because
where 𝑤min and 𝑤max indicate the minimum and maximum
of nonlinear mathematical equations of the MOSFETs at
weighing functions and iter denotes the number of iterations.
low voltages, analysis of the circuit becomes complicated.
In order to optimize the parameters of the controller by
For solving this problem, designers have compensated these
PSO, the following cost function is used:
nonidealities by choosing the aspect ratios of MOSFETs by
𝑡1 𝑡1
trial and error (T&E) method [21]. Using of this method has 󵄨 󵄨
been the only solution so far. In this paper in addition to PSO = ∫ |𝑒 (𝑡)| 𝑑𝑡 = ∫ 󵄨󵄨󵄨󵄨𝑖discharge − 𝑖charge 󵄨󵄨󵄨󵄨 𝑑𝑡, (10)
0 0
T&E, MATLAB software is used to apply two methods of
optimization algorithms to find the optimum aspect ratios. where 𝑡1 is the final time of simulation, 𝑒 is the error signal,
The main purpose is equalizing the charge and discharge and 𝑡𝑠 is the settling time of the system.
current in a wide output voltage range to achieve the highest
output current matching. 4.2. Genetic Algorithm. Genetic Algorithm is a search-based
optimization method [23]. This algorithm has been proposed
4. Tuning by Particle Swarm by John Holland (1962). In the algorithm, he has benefited
from two principles of selection and reproduction in the
Optimization and Genetic Algorithm nature. Genetic Algorithm can be considered as an ori-
In this paper, in addition to T&E, MATLAB software is used ented random optimization method which gradually moves
to apply two methods of optimization algorithms to find the towards optimal point.
optimum aspect ratios. The main purpose is to equalize the Unlike other common optimization models in which only
charge and discharge current in a wide output voltage range one point is used in each stage of optimization process, in
to achieve the highest output current matching. Genetic Algorithm, a group of points are used.
To optimize the aspect ratios of M4n–M9n and M4p– If our optimization target function is as
M9p and choose the best values, Particle Swarm Optimiza- 𝐹 = 𝑓 (𝑥1 , 𝑥2 , . . . , 𝑥𝑛 ) , (11)
tion (PSO) and Genetic Algorithm (GA) are used.
then, the objective is to find the value of 𝑥𝑖 in such a
4.1. Particle Swarm Optimization. Particle Swarm Optimiza- way that 𝐹 function has the minimum value. In Genetic
tion (PSO) was introduced in 1995 by Kennedy and Eberhart Algorithm, at the first stage, a set of chromosomes are
[22]. In PSO algorithm, a random population of points is randomly created (random strings from 𝑥1 to 𝑥𝑛 ). These
generated. Each point represents a member of the population. 𝑥𝑖 refer to genes. Putting each of these chromosomes in
In PSO algorithm, there is no sudden jump or confusion; target function, the value of 𝐹 function is obtained. The first
each point is a solution. Considering 𝑋 and 𝑉 as particle generation concludes through appropriate scoring to these
position and velocity, respectively, the position of 𝑛th par- values. The first generation is called parents generation.
ticle in a space with 𝑚 dime is represented with 𝑋𝑛 = The process of creating offspring (children) in the next
[𝑋𝑛1 , 𝑋𝑛2 , . . . , 𝑋𝑛𝑚 ]. generations follows the following three general principles:
The position of each particle is changed at the next stage (a) Crossover
and it reaches a new position. The best position of 𝑛th particle
which corresponds to the lowest cost function for that particle (b) Elite
is saved in 𝑃best𝑛 . In addition, 𝑃best of all particles are compared (c) Mutation.
6 Journal of Electrical and Computer Engineering

Table 2: Aspect ratio values of MOSFETs at different methods. PSO

240
𝑀4𝑛 𝑀5𝑛 𝑀6𝑛 𝑀4𝑝 𝑀5𝑝 𝑀6𝑝
PSO 107 328 169 91 718 268 220
GA 287 344 261 137 662 363
200
T&E 43 327 111 53 795 222
180
GA optimization

Best cost
200
160

180 140

160 120
Best cost

100
140

80
120 0 50 100 150 200
Iteration

100 Figure 8: Convergence objective function for Particle Swarm

Optimization.

80
0 50 100 150 200
20
Iteration
Output current (𝜇A)

Figure 7: Convergence objective function for Genetic Algorithm. 15

10

After the second generation and after creating offspring with 5

ratios determined by selection algorithms, new generation
children are selected. Putting these children into target 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
function and scoring them, then, the algorithm is reiterated Vout (V)
until the algorithm meets the ending criteria (such as the
number of generation and time), causing the algorithm to be Idischarge (T&E) Icharge (PSO)
stopped. Icharge (T&E) Idischarge (GA)
Idischarge (PSO) Icharge (GA)

4.3. Results Optimization. In this study, the values of transis- Figure 9: Matching characteristic of the proposed charge pump.
tors aspect ratio are optimized using the following consider-
ations.
It should be noted that aspect ratios of 𝑀4𝑛(𝑝) equal
the proposed charge pump which are obtained from T&E,
𝑀7𝑛(𝑝), 𝑀5𝑛(𝑝) equal 𝑀8𝑛(𝑝), and 𝑀6𝑛(𝑝) equal 𝑀9𝑛(𝑝).
PSO, and GA methods as the output voltage is swept from 0
The aspect ratios of the MOSFETs should be positive.
to 1.8 V. As can be seen, the output dynamic voltage ranges of
In the present study, the number of the algorithm
output current matching are 0.25–1.6 V, 0.1–1.65 V, and 0.08–
iterations is the stopping criterion. Both PSO and GA are
1.65 V for T&E, PSO, and GA, respectively. According to these
simulated using the following two sets of parameters:
results, the GA method makes a better performance to this
(a) parameters iteration = 100 and population = 30, charge pump. Therefore, the aspect ratios which are presented
(b) parameters iteration = 200 and population = 50. by the GA are chosen for applying to the proposed charge
pump. Current mismatch is less than 1% of nominal output
The results pertained to the target function optimization of current (𝐼charge or 𝐼discharge ) over the output range of these
(10) have been shown in Figures 7 and 8. The respective methods.
figures, in fact, indicate cost function improvement for the In the usual bulk driven current mirror, the gate terminals
increase in the number of iterations. are tied to 𝑉dd [24]. However, in these circuits, the output
The results of T&E and optimal value factor’s aspect ratios current cannot track the input current in a specified range
are presented in Table 2. [13]. Figure 10 shows the variations of output current versus
To verify the efficiency of the proposed circuit, it is input current in the proposed circuit. As can be seen,
simulated under the power supply of 1.8 V in 180 nm CMOS the output current can track the input current in a wide
technology using Hspice. Input current is set to 20 𝜇A. input current range. The overall power consumption of the
Figure 9 shows the charge and discharge output currents of proposed charge pump circuit is around 160 𝜇W. Table 3
Journal of Electrical and Computer Engineering 7

Input and output current (𝜇A)

150

100

50

0
0 20 40 60 80 100 120 140 160
Input current (𝜇A)

Input current Output current in [21]

Output current

Figure 10: Input and output current transfer characteristics.

RMS jitter = 0.671 ps 1.8 3.46 ps

120
Number of occurrences

P-t-P jitter = 3.46 ps 1.6

100 1.4

Voltage (volt)
1.2
80
1
60 0.8
40 0.6
0.4
20 0.2
0 0
76.5 77 77.5 78 78.5 79 @0 @20 @40 @60 @80
Time (psec) Time (psec)
(a) (b)

Figure 11: (a) Output jitter histogram at 3 GHz. (b) Output jitter eye diagram at 3 GHz.

Table 3: Performance comparison of the proposed charge pump. a 1.85 GHz frequency offset. The phase noise of the PLL at the
locking frequency in different frequency offsets is presented
[11] [12] [13] This work in Figure 13. The output phase noise is −117.6 dBc/Hz at
CMOS tech (nm) 130 180 180 180 a 1 MHz frequency offset. The total power consumption is
Power supply (V) 1.2 3 1.8 1.8 about 11.5 mW. The figure of merit of the proposed PLL
Voltage swing (V) 0.2–1 0.2–2.7 0.3–1.58 0.08–1.66 according to (12) [25] is −198.47 dBc/Hz.
Swing/𝑉dd 66% 83.3% 71% 88%
𝑓0 FTR
Current mismatch 0.9% 2.1% 1% 1% FOM = 𝐿 {Δ𝑓} − 20 log { × }
Δ𝑓 10
Power consumption (𝜇W) 30 NA 395 160 (12)
𝑃diss
+ 10 log { },
1 mW
summarizes the performance of the proposed charge pump where 𝐿{Δ𝑓} is phase noise, Δ𝑓 is certain frequency offset, 𝑓0
and compares them with recent publications. As can be is center frequency, 𝑃diss is the power dissipation, and FTR is
observed, the proposed circuit has an excellent voltage swing tuning range of oscillation frequency.
per 𝑉dd , while its power consumption is reasonable. Table 4 summarizes these results and presents a perfor-
mance comparison of this work with some recent papers. The
5. Simulation Results of Proposed PLL proposed PLL achieves lowest FOM𝑇 by using a fast PFD
circuit and omitting the divider circuit.
The PLL is designed using the proposed PFD and charge
pump circuits. Furthermore, it employs a two-stage voltage 6. Conclusion
controlled ring oscillator [18]. This PLL has a wide locking
range from 500 MHz to 5 GHz. A very simple, low power, high speed, and open loop phase
Jitter histogram and eye diagram at 3 GHz operating fre- detector is proposed which operates in a wide frequency
quency are depicted in Figure 11, which shows around 0.671 ps range from 1 MHz to 5 GHz. Due to the extra simplicity
and 3.46 ps RMS and peak-to-peak jitters, respectively. of the circuit, the power consumption is very low and is
Figure 12 shows the output spectrum simulated at 3 GHz. about 0.3 mW at the highest operational frequency. The dead-
The simulation result shows a reference spur of −72 dBm with zone and missing edge problems are solved completely in
8 Journal of Electrical and Computer Engineering

Table 4: A performance comparison of proposed circuit with some recent papers.

Performance parameter [14] [15] [16] [17] [18] [7] This work
CMOS tech (nm) 65 65 65 65 90 180 180
Supply voltage (v) 1 1.2 1.2 1 1.2 1.8 1.8
VCO Ring Ring LC Ring Ring Ring Ring
Ref. frequency (GHz) 0.645 0.64 104 1.6 0.01 5 3
Locking range (GHz) 0.485–1.011 0.25–1.06 103.05–104.58 NA 3.5–7.1 2.5–7.3 0.5–5
Ref. spur (dBm) NA −54.8 −63.8 −47 −64.8 −66.8 −72
Phase noise @ 1 MHz offset (dBc/Hz) −110.8 −88.6 −80.41 −88 −105 −108.2 −117.6
RMS jitter (ps) NA 9.6 2.44 4.82 3.8 0.88 0.671
P-t-P jitter (ps) NA 52.2 18 38 NA 3.21 3.46
Power (mW) 10 1.2 63 0.99 29.64 13.4 11.5
FOM @ 1 MHz offset (dBc/Hz) −157 NA −162.57 NA NA −190.55 −198.47

1.85 GHz single ended charge pump architecture has a higher substrate
0 db
and supply noise coupling, a differential charge pump circuit
−20 db can be considered as a future work. Moreover, the operating
−72 dBm frequency range can be increased by tracking the self-
Spectrum (dBm)

−40 db
oscillation frequencies of the voltage-controlled oscillator
−60 db (𝑉CO ) and the frequency divider. The rms and peak-to-peak
−80 db jitters of this PLL at 3 GHz are 0.671 and 3.46 ps, respectively.
−100 db
−120 db Competing Interests
1 2 3 4 5 The authors declare that they have no competing interests.
Frequency (GHz)

Figure 12: Output spectrum of the VCO. References

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