IEICE TRANS. ELECTRON., VOL.E104–C, NO.

10 OCTOBER 2021
625

PAPER Special Section on Analog Circuits and Their Application Technologies

A Noise-Canceling Charge Pump for Area Efficient PLL Design

Go URAKAWA†a) , Hiroyuki KOBAYASHI† , Jun DEGUCHI† , Nonmembers,

and Ryuichi FUJIMOTO† , Senior Member

SUMMARY In general, since the in-band noise of phase-locked loops

(PLLs) is mainly caused by charge pumps (CPs), large-size transistors that
occupy a large area are used to improve in-band noise of CPs. With the
high demand for low phase noise in recent high-performance communica-
tion systems, the issue of the trade-off between occupied area and noise in
conventional CPs has become significant. A noise-canceling CP circuit is
presented in this paper to mitigate the trade-off between occupied area and
noise. The proposed CP can achieve lower noise performance than conven-
Fig. 1 PLL block diagram.
tional CPs by performing additional noise cancelation. According to the
simulation results, the proposed CP can reduce the current noise to 57%
with the same occupied area, or can reduce the occupied area to 22% com- Table 1 Closed loop transfer functions for PLL blocks (2020
c
pared with that of the conventional CPs at the same noise performance. We IEEE [31]).
fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL
using a 16-nm FinFET process, and 1.2-dB improvement in single sideband
integrated phase noise is achieved.
key words: PLL, frequency synthesizer, phase-locked loop, charge pump,
noise-cancel, phase noise, jitter, in-band noise, occupied area

1. Introduction

Phase-locked loops (PLLs) are often used as frequency syn-

thesizers in most wireless and wireline communication sys-
tems. The phase noise of PLLs limits the signal-to-noise ra-
tio of transmitters and receivers. Recent high-performance
communication systems with multi-level modulation, such
as quadrature amplitude modulation and pulse amplitude
modulation, strongly require lower phase noise to improve
communication quality [1]–[9].
In recent years, digital PLLs have been widely used
because of their benefits, such as portability, small area, and
noise tolerance. However, analog PLLs are still an attractive
option for clock generation when lower noise is required or
when designing in older processes [32]. The in-band phase
noise of digital PLLs is usually determined by the resolu-
tion of the time-to-digital converters (TDCs) and digitally
controlled oscillators (DCOs). High-resolution TDCs and Fig. 2 Example of phase noise with contribution of each block.
DCOs can result in large circuits that consume a lot of power
and area. Therefore, digital PLLs have higher cost and
worse performance compared with analog PLLs when tar- functions and frequency response of the phase noise in each
geting lower phase noise [33]. block. The transfer functions are obtained from the linear
Typical analog PLLs consist of a feedback loop with PLL model [10]–[12], and these transfer functions have dif-
several blocks as shown in Fig. 1. Table 1 shows the transfer ferent types of frequency response, including low-pass filter
(LPF), band-pass filter (BPF), and high-pass filter (HPF).
Manuscript received November 9, 2020. Figure 2 shows an example of the frequency response of
Manuscript revised February 18, 2021. the phase noise in each block. The dominant components
Manuscript publicized April 20, 2021.
† of phase noise differ depending on the frequency region
The authors are with Kioxia Corporation, Kawasaki-shi, 212–
8520 Japan. because the frequency response of the noise transfer func-
a) E-mail: go.urakawa@kioxia.com tions differ between blocks. For example, inside the loop
DOI: 10.1587/transele.2020CTP0004 bandwidth, the phase noise of voltage-controlled oscillators

Copyright 
c 2021 The Institute of Electronics, Information and Communication Engineers
 IEICE TRANS. ELECTRON., VOL.E104–C, NO.10 OCTOBER 2021
626

(VCOs) is not dominant since VCOs have an HPF trans-

fer characteristic, the in-band phase noise of VCOs is sup-
pressed. In contrast, the phase noise of PFD-CPs is domi-
nant inside the bandwidth, as shown in Fig. 2 [13], [14], ow-
ing to their LPF transfer characteristic.
There are methods for reducing in-band phase noise
from each block in a PLL. Reference clock noise generally
appears within several kilohertz-offset frequency, and can be
reduced by using low-noise crystal oscillators with high-Q Fig. 3 Conventional architecture of CP.
and enhancing the driving capability of the output buffers.
The noise of dividers can be suppressed by achieving high
slew rate using high-speed devices in advanced technolo-
gies like the FinFET process. The noise of the loop filters
is predominantly thermal noise from resistors, which can be
mitigated by adjusting the loop parameters to reduce the re-
sistances that comprise the loop filters [16]. The noise of
CPs can be reduced by increasing transistor sizes because
noise in devices such as MOSFETs can be suppressed by
using larger size devices. However, larger devices require
a larger occupied area, resulting in a higher fabrication cost
of low-noise CPs. This becomes a very serious issue when
using advanced technologies such as the FinFET process.
We propose a noise-canceling CP that suppresses the
in-band noise and reduces occupied area. This paper is or-
ganized as follows. The trade-off issues of conventional CPs
are described in Sect. 2. Section 3 introduces the design Fig. 4 Images of PFD-CP transfer curve and waveform (a) without offset
of the proposed CP that solves the trade-off. Section 4 current and (b) with offset current.
presents experimental results. Finally, Sect. 5 provides our
conclusions.
design advanced transceivers for wireline and wireless com-
2. Low-Noise Design Issues for Conventional CPs munication systems. When FinFETs are used, the noise per-
formance of CPs tends to be degraded compared with planer
2.1 General Issues of Conventional Low-Noise CPs MOSFETs [17]. FinFET gates are limited to short lengths
owing to the process integration of the high-permittivity gate
In the linear PLL model, the in-band phase noise associated dielectric and metal gate [17]. One typical method for im-
with the CPs can be expressed as itating a long-gate-length transistor is to use stacked short-
gate-length transistors [18]. However, the number of transis-
N2
LCP ∝ , (1) tors in the stack is limited due to the voltage drops from the
(ICP /2π)2 large source resistance of the transistors [17]. As a result,
where N is the number of divisions of the PLL, and ICP is there are limits to increasing the gate length in each transis-
the CP output current value [15]. This shows that the in- tor in CPs for low-noise performance, and low-noise design
band phase noise associated with CPs can be adjusted us- techniques for CPs are becoming more and more important
ing the loop parameters. Specifically, although the in-band in advanced FinFET processes.
noise can be reduced by using smaller N and larger ICP , this
creates undesirable requirements for other blocks. For ex- 2.2 Trade-Off between Area and Noise in Conventional
ample, increasing ICP causes larger capacitors to be required CPs with Phase Offset Generator
in the loop filters, which increases the occupied area. Sim-
ilarly, reducing N results in the need for a higher-frequency Figure 3 shows a conventional architecture for CPs using
reference clock since the output frequency of the PLL is de- a linearization method. In the linearized CP, it is common
termined by the reference frequency multiplied by N, and to use an offset CP current as a phase-offset generator [19]–
this results in increased power consumption. Thus, adjust- [22]. Figure 4 shows the injected charge versus input phase
ing loop parameters such as N or ICP to improve the in-band error characteristic, and waveforms of the reference (R) and
phase noise results in larger occupied area or power con- feedback (N) clocks in the PFD and the output current ICP
sumption. Hence, the only practical method for reducing of the CP. When there is almost no phase offset between the
the in-band phase noise is to adopt large-size transistors for two clocks, the PFD and CP operate in a region around the
CPs. zero-phase error called the dead zone, as shown in Fig. 4.
Recently, the FinFET process has been widely used to This dead-zone is primarily derived from the delayed
URAKAWA et al.: A NOISE-CANCELING CHARGE PUMP FOR AREA EFFICIENT PLL DESIGN
627

Fig. 5 Circuit diagram of conventional CP (2020

c IEEE [31]). Fig. 6 Current waveforms: (a) Current pulse of main CP; (b) Offset cur-
rent; (c) CP output current.

response of the “UP” or “DN” switches and current sources the conventional CP circuit. Incidentally, M6 is not a domi-
to fine phase errors. As shown in the waveforms in Fig. 4 (a), nant noise element because it has almost no operation while
ICP is not output properly because CP cannot adequately fol- the loop is locked with the phase offset.
low the fine phase error between the reference and feedback In order to reduce the CP noise, the size of each tran-
clocks. Consequently, PLL performances such as phase sistor is determined as follows based on the above relations.
noise and spurs are degraded because the behavior of the The sizes of M2, M3, M4, and M5 need to be large since
PLL differs from the ideal operation due to the dead zone. they are dominant noise sources. The size of M4 becomes
The phase-offset generator Ioffset is used to deal with very large depending on the mirror ratio from M3, which
above mentioned dead-zone issue. As shown in Fig. 4 (b), is usually more than 5 times, because the current value of
by using the phase-offset generator, the loop is locked with M3 cannot be designed so large to prevent extra power con-
a constant phase offset between the reference and feedback sumption. Since the size of M5 is large even though it has
clocks depending on the offset current value. Therefore, the a small current value, the size of M6 also needs to be large.
PFD and CP can operate in a linear region, which means that This is because the size of M6 is more than 10 times that
the PFD and CP can follow fine phase errors, and the PLL of M5 depending on the current mirror ratio, because the
with phase-offset generator can avoid performance degrada- current value of M6 is usually designed to be more than 10
tion due to the dead zone. Moreover, the phase offset gen- times the offset current of M5. Moreover, the current value
erator eliminates the need to consider the current mismatch of M1 is usually designed to be close to M2 and M5, and
between the up and down currents which often causes trou- therefore, the size of M1 automatically increases to match
ble when the PFD and CP operate in the region around the the size due to the mirror relation. In this way, although M1
zero-phase error [23]–[30]. and M6 are not dominant noise elements in the conventional
Figure 5 shows the circuit diagram of a conventional CP, their size needs to be large.
CP with phase-offset generator. The CP has two current To achieve low-noise performance in conventional CPs
sources M4 and M6 that are controlled by “UP” and “DN” with a phase offset generator as shown in Fig. 5, large tran-
signals from the PFD, IREF is a constant current source, and sistors are needed for M1, M2, M3, M4, M5, and M6. Since
M1, M2, and M3 are current mirrors. In this circuit, a cur- many large transistors are used, a large occupied area is
rent source M5 is added to the CP output as a phase offset needed for low noise performance, creating a trade-off be-
generator. Figure 6 (a), (b), and (c) show the current wave- tween noise performance and occupied area in conventional
forms of the current pulse IUP , the constant current Ioffset , CPs with a phase-offset generator.
and the CP output current ICPOUT , respectively. The pulse
width of IUP is automatically controlled by the PFD so that 3. Circuit Design of Proposed Noise-Canceling CP
the area “A” equals “B” in Fig. 6. This is because the to-
tal charge injected into the loop filter in one period is zero 3.1 Principle of Offset Current Generation and Noise Can-
when the PLL is locked [15]. The phase offset in the con- cellation in Proposed CP
ventional CP is realized by the offset current generator M5
in this way. The noise generated in M1 and IREF in Fig. 5 We propose a novel CP circuit as shown in Fig. 7 that miti-
are copied to both M4 and M5 and included in IUP and Ioffset , gates the trade-off between noise performance and occupied
respectively. These noise elements in IUP and Ioffset can be area. By using the proposed CP, the noise of M2 and M3
canceled, since the output charge accumulated by IUP is dis- in addition to IREF and M1 can be cancelled as described
charged by Ioffset every cycle while the PLL is locked [15]. later. A phase-offset generator using a capacitor CS is used
In contrast to IREF and M1, the noise of M2, M3, M4, and to flow the offset current instead of the offset current source
M5 cannot be canceled, and are dominant noise elements in that is used in conventional CPs. It is necessary to repeatedly
 IEICE TRANS. ELECTRON., VOL.E104–C, NO.10 OCTOBER 2021
628

Fig. 7 Circuit diagram of proposed CP (2020

c IEEE [31]).

Fig. 9 Current waveforms: (a) Current pulse of main CP; (b) Offset cur-
rent; (c) CP output current.

Fig. 8 Parts related to generating a phase offset.

Fig. 10 Proposed CP with parts related to discharging method high-

charge and discharge for every period of the phase compar- lighted.
ison because current cannot flow continuously to a capaci-
tor. We use the current source M7, voltage-follower A1, and
some switches for the charge and discharge operations. The M2, and M3 in IUP are pulled out by ICHG , and this is the
upper- and lower-electrode voltage of CS , and the CP-output principle of the noise cancellation in the proposed CP.
voltage are defined as VU , VL , and VCP , respectively. Discharging the capacitor CS is required in order to
Similar to the conventional CP, the following-stage LF achieve sufficient phase offset. If CS is not discharged suf-
is charged by the CP current Iup . After that, CS is charged ficiently, the offset current is small and the phase offset is
by ICHG in the proposed CP to realize the phase offset opera- also small. The development of the discharge method is the
tion. Figure 8 shows the circuit diagram of the proposed CP most significant part of the proposed CP because noise per-
during a charging operation. In order to generate the phase formance greatly depends on the discharging method.
offset, switches S1 and S2 are turned on, and ICHG flows to Figure 10 shows the proposed CP circuit during the dis-
CS as shown in Fig. 8. At this time, IUP does not flow and charge operation. Figure 12 (b), (c), and (d) show the wave-
ICHG comes from the following-stage LF as ICPOUT . Note forms of ICPOUT , QS , and VCs , respectively, where QS is the
that ICHG is strongly correlated with IUP because the LF is charge stored in CS , and VCs represents the voltage differ-
previously charged by IUP . Figure 9 (a), (b), and (c) show the ence between VU and VL . It is crucial to prevent charge from
current waveforms of the current pulse IUP in Fig. 7, the off- leaking from CS during this time because any leak is un-
set current ICHG , and CP-output current ICPOUT in Fig. 8, re- correlated with the current mirrors and degrades the noise-
spectively. The offset current ICHG flows and the charge cor- canceling effect. Therefore, the capacitor CS is controlled to
responding to area “B” is stored in CS as shown in Fig. 9 (b). be disconnected from CPOUT except while being charged,
Once the PLL is locked, the areas “A” and “B” in Fig. 9 and the voltage follower A1 and switch S3 are used to keep
are exactly the same, because the output charge accumulated VU the same as VCP while S1 is turned off. After that, S4 is
by IUP is exactly discharged by ICHG every cycle while the turned on to discharge CS , and the current flows to the lower
PLL is locked. In other words, the time over which IUP flows electrode of CS from M7. As a result, VL is pulled up by
is controlled so that the areas “A” and “B” are the same by this current and QS is discharged as shown in Fig. 12 (c) and
the locked PLL. Therefore, the noise elements of IREF, M1, (d).
URAKAWA et al.: A NOISE-CANCELING CHARGE PUMP FOR AREA EFFICIENT PLL DESIGN
629

cancelling CP including the example of the transistor sizes.

First, M1, M2, and M6 can be designed small because they
are not dominant noise sources. Next, the size of M3 can
be reduced because of the additional noise-canceling effect
of the proposed CP. Finally, it is necessary to determine the
sizes of M4 and M7 carefully to be large enough depend-
ing on the target noise specifications. Thus, although many
large MOSFETs are needed in a conventional CP, the pro-
posed CP needs only two large MOSFETs and offers an area
efficient design.
In actual implementation, incomplete cancellation oc-
curs for the correlated noise contained in IUP and IDCHG .
Therefore, when this incomplete cancellation is taken into
account, extremely small transistors need to be avoided.
Fig. 11 Transistor sizes in the proposed CP.
3.3 Detailed Circuit Operation of the Proposed CP

Figure 12 shows detailed waveforms for the proposed CP.

First, S1 and S2 are turned on and charge is drawn into CS
generating the offset current ICHG . VU rises to VCP and QS
becomes charged, as shown in Fig. 12 (c) and (d). At the
same time, S5 is also turned on and the current generated in
M7 flows to ground. Next, S1 and S3 are turned off and on,
respectively, and CS is disconnected from the node CPOUT
and connected to the voltage follower A1 to keep VU the
same as VCP before the phase comparison. After this, the
current pulse IUP is output from M4 to compensate the offset
charge. After IUP stops, S5 is turned off and switches S2 and
S4 are turned on to discharge CS by M7. VL is pulled up by
the current of M7 and QS is discharged as shown in Fig. 12.
The design consideration when controlling these
switches is to prevent unnecessary leaks from CS . There-
fore, it is necessary to control the on and off timings of the
switches so that the voltage across CS does not change. For
example, in order to maintain VU when Cs is disconnected
from CPOUT via S1, S3 needs to be turned on in conjunc-
tion with S1 being turned off. In the same way, S4 needs
to be turned on in conjunction with S2 and S5 being turned
off the moment Cs is disconnected from ground via S2 to
maintain VL to ground.
These operations are repeated every period of the phase
comparison; that is, the operation frequency of S1–S5 is the
same as the frequency of the phase comparison. Therefore,
Fig. 12 Timing diagram of the operation of the proposed circuit.
S1–S5 need to be designed properly considering whether
they can operate at the target reference frequency, since they
Note that the charge and discharge currents of CS orig- may become one of the factors that limits the CP operating
inate from current sources M4 and M7, respectively, and speed. Although the operation speed using the proposed CP
both current sources copy the current of M3. The common is lower than that using the conventional CP, the proposed
noise elements included in the charge and discharge currents CP can operate up to 500 MHz in our simulation, which is
(i.e. the noise of IREF, M1, M2, and M3) can be canceled sufficient for 100 MHz used in this work.
in the proposed CP. Thus, additional noise-canceling effects
are obtained, and the noise performance of the proposed CP 3.4 Simulated Results of Proposed CP
is further improved compared with conventional CPs.
Figure 13 shows simulation results of the CP current noise
3.2 Device Size Considerations of the Proposed CP for conventional and proposed CPs. The simulation results
indicate that the in-band noise can be improved because
Figure 11 shows a circuit diagram of the proposed noise- of the additional noise-canceling effect of the proposed CP.
 IEICE TRANS. ELECTRON., VOL.E104–C, NO.10 OCTOBER 2021
630

Fig. 14 Simulation results for relation between CP area and CP noise

Fig. 13 Simulated CP current noise (2020
c IEEE [31]). (2020
c IEEE [31]).

Table 2 Comparison of noise contributions (2020

c IEEE [31]).
transistors in the conventional CP because of the relatively
small noise contributions of the switches and voltage fol-
lower as shown in Table 2.
Figure 14 shows simulation results for the relation be-
tween occupied area and integrated current noise for the pro-
posed and conventional CPs. These data were plotted by
sweeping the transistor sizes of the current sources in CP
and simulating the CP current noise. It can be clearly seen
that lower-noise performance can be realized with smaller
occupied areas by using the proposed CP. The proposed CP
can reduce the value of the current noise to 57% for the same
occupied area. When the same noise performance is re-
quired, the occupied area of the proposed CP can be reduced
to 22% compared with the conventional CP. Moreover, al-
though the lower limit of current noise of the conventional
CP is about 9.18 nArms, a noise current value of 8.05 nArms
These simulations were executed using periodic noise anal- can be achieved using the proposed CP with small occupied
ysis under conditions equivalent to the loop being locked, area.
which means that the input phase error of the PFD between
the reference clock and feedback clock are set so that the 4. Experimental Results
output charge equals zero. The sizes of IREF, M1, M2, M3,
M4, and M6 are the same in each CP with only the offset We fabricated a prototype of the proposed CP embedded in
generator differing for easy comparison. a 28-GHz LC-PLL using a 16-nm FinFET process. Both
Table 2 shows the noise-contribution ratio for the simu- conventional and proposed CPs were implemented and se-
lation results for the conventional and proposed CPs shown lectable by changing the mode to evaluate the effectiveness
in Fig. 13. In the conventional CP, the contribution of M5 of the proposed CP. The frequency of the reference clock is
is the highest and the contributions of M4, M3, and M2 100 MHz. It was generated by doubling the 50-MHz fun-
are higher, as we expected. In the proposed CP, the con- damental frequency of the crystal oscillator considering the
tribution of M7 is the highest, and the contribution of M4 suitability for mass production in terms of its cost and avail-
is the second, that is, M7 and M4 are the dominant noise ability. The power-supply voltage of the PLL is 0.9 V. The
sources in the proposed CP as expected. In these simulation die micrograph is shown in Fig. 15. The fully integrated
circuits, IREF was designed with the approximately mini- PLL occupied an area of 280 μm × 340 μm, and the area
mum size of PMOSFET because the noise of IREF can be occupied by the CP is only 140 μm × 45 μm. In order to
canceled. However, IREF cannot be cancelled completely achieve the same noise performance using the conventional
in actual simulations and represents a slightly high contri- CP, a CP area of at least 4.5 times is required according to
bution in both CPs. estimates in Fig. 14. This difference in area occupied by the
It is necessary to consider the noise contributions of CPs has a large impact on the area occupied by the whole
the additional switches and the voltage follower in the pro- PLL.
posed CP. However, these components can be designed us- The measured output phase noise of the PLL is shown
ing smaller transistors compared with the current-source in Fig. 16. The red line shows the phase noise using the pro-
URAKAWA et al.: A NOISE-CANCELING CHARGE PUMP FOR AREA EFFICIENT PLL DESIGN
631

Fig. 15 Die micrograph (2020

c IEEE [31]).

Fig. 17 Simulated phase noise profile with breakdown of each block.

Fig. 16 Measured PLL phase noise (2020

c IEEE [31]).
Fig. 18 Improvements in phase noise.

posed CP showing that in-band phase noise is suppressed

compared with that using the conventional CP. Single side-
band integrated phase noise from 1-kHz to 40-MHz off-
set frequency is improved by 1.2 dB. The dashed line in
Fig. 16 shows the simulated phase noise of the PLL using
the proposed CP. The measured phase noise of the proposed
PLL is close to the simulation result. Figure 17 shows the
simulation results, including the breakdown of noise in the
PLLs with proposed and conventional CPs. Except for the
CPs, the other blocks are common to both PLLs. It is clear
that the improvement in the in-band phase noise is due to
the improvement in the CP noise owing to the additional
noise-canceling effect of the proposed CP. These measure-
ments were made by evaluating the PLL output signal af-
Fig. 19 Comparison of measured spurs.
ter division by four using a Keysight E5052A signal source
analyzer.
Figure 18 shows the calculation results for the differ- during phase comparison in the conventional CP as shown
ence between the two phase noise curves in Fig. 16 in each in Fig. 6 (c), but IUP is not reduced during phase comparison
offset frequency. It can be seen that the phase noise is in the proposed CP as shown in Fig. 9 (c). Therefore, the
improved in all regions inside the loop bandwidth (1.0 MHz) loop bandwidth was a little wider in the PLL with the pro-
with a maximum improvement value of 4.9 dB at 2.2-kHz posed CP and phase noise is slightly degraded compared to
offset. The phase noise of the PLL using the proposed CP the PLL with the conventional CP in the region from 1-MHz
is degraded in the region from 1-MHz to 3-MHz offset, it is to 3-MHz offset.
due to the slight difference in the loop bandwidth. The effec- We measured the spurs in order to check the effects of
tive gain of the PFD with the conventional CP was smaller the additional operations of switches in the proposed CP.
than the proposed one because the IUP is reduced by Ioffset Figure 19 shows measured reference spurs of the PLL using
 IEICE TRANS. ELECTRON., VOL.E104–C, NO.10 OCTOBER 2021
632

Table 3 Performance summary

cent high-performance communication systems which re-
quire low-noise PLLs with small occupied area. In partic-
ular, it is effective when high-cost advanced technologies
such as FinFET process are used.

Acknowledgments

The authors would like to thank T. Suzuki for techni-

cal discussions, J. Wadatsumi, M. Morimoto, M. Ashida,
F. Tachibana, Y. Satoh, Y. Tsubouchi, T. Toi, H.C. Ngo,
K. Kamikawa and T. Aoyama for their supporting of this
project.

References

[1] W. Wu, C.-W. Yao, K. Godbole, R. Ni, P.-Y. Chiang, Y. Han, Y.

Zuo, A. Verma, I.S.-C. Lu, S.W. Son, and T.B. Cho, “A 28-nm
75-fsrms Analog Fractional-N Sampling PLL with a Highly Linear
DTC Incorporating Background DTC Gain Calibration and Refer-
ence Clock Duty Cycle Correction,” IEEE J. Solid-State Circuits,
the conventional and proposed CPs. Since there was almost vol.54, no.5, pp.1254–1265, May 2019.
[2] F. Song, Y. Zhao, B. Wu, L. Tang, L. Lin, and B. Razavi, “A Frac-
no difference between the two lines in Fig. 19, the spurs us- tional-N Synthesizer with 110fsrms Jitter and a Reference Quadru-
ing the proposed CP were virtually not degraded owing to pler for Wideband 802.11ax,” IEEE ISSCC, pp.264–265, May 2019.
the additional switching operations. It is assumed that the [3] S. Kawai, R. Ito, K. Nakata, Y. Shimizu, M. Nagata, T. Takeuchi,
additional operations of the switches have less effect on the H. Kobayashi, K. Ikeuchi, T. Kato, Y. Hagiwara, Y. Fujimura,
spurs because the number of switches directly connected to K. Yoshioka, S. Saigusa, H. Yoshida, M. Arai, T. Yamagishi, H.
CPOUT is only one (S1) as shown in Fig. 7 and the current Kajihara, K. Horiuchi, H. Yamada, T. Suzuki, Y. Ando, K.
Nakanishi, K. Ban, M. Sekiya, Y. Egashira, T. Aoki, K. Onizuka,
flowing through the switch is small enough. The spurs were and T. Mitomo, “An 802.11ax 4 x 4 High-Efficiency WLAN AP
caused by sharing the power supplies of the VCO, crystal Transceiver SoC Supporting 1024-QAM with Frequency-Depen-
oscillator, and other PLL blocks in the prototype. The spur dent IQ Calibration and Integrated Interference Analyzer,” IEEE J.
at 50-MHz offset was due to the fundamental frequency of Solid-State Circuits, vol.53, no.12, pp.3688–3699, Dec. 2018.
the crystal oscillator, and other spurs such as 200-MHz, 300- [4] G. Vlachogiannakis, C. Basetas, G. Tsirimoku, C. Vassou, K.
Vastarouchas, A. Georgiadou, I. Sotiriou, T. Korfiati, and S.
MHz, and 400-MHz offsets were primarily due to harmonic
Sgourenas, “A Self-Calibrated Fractional-N PLL for WiFi 6/
frequencies. These measurements were made by evaluating 802.11ax in 28nm FDSOI CMOS,” IEEE ESSCIRC, Sept. 2019.
the PLL output signal after division by four using a Keysight [5] V. Aggarwal and S. Aniruddhan, “A 27-29GHz Integer-N PLL with
N9020A signal analyzer. Quadrature phases for 5G applications,” IEEE MTT-S, Aug. 2019.
Finally, the implementation and measurement results [6] W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, and
are summarized in Table 3. At 28-GHz output and 0.9-V M. Hossain, “A 28-GHz Quadrature Fractional-N Frequency Syn-
thesizer for 5G Transceivers with less than 100-fs jitter based on
supply, the measured RMS integrated jitter of the PLL using cascaded PLL architecture,” IEEE Trans. Microw. Theory Techn.,
the conventional and proposed CPs was 848 fs at 10.0 mW vol.65, no.2, pp.396–413, Feb. 2017.
and 735 fs at 11.2 mW, respectively. The power consump- [7] S. Kim, B. Han, M. Cho, S. Oh, J. Lee, and T.-B. Cho, “A 14nm
tion of the CP increased by 1.20 mW from 0.48 mW to FinFET Sub-Picosecond Jitter Fractional-N Ring PLL for 5G Wire-
1.68 mW, and the 98% of the increase was due to the less Communication,” IEEE RFIC, June 2018.
[8] W. Wu, C.-W. Yao, K. Godbole, R. Ni, P.-Y. Chiang, Y. Han, Y.
voltage-follower A1 in Fig. 7. Consequently, the FoM of
Zuo, A. Verma, I.S.-C. Lu, S.W. Son, and T.B. Cho, “A 28-nm
−232.2 dB was achieved with the proposed CP compared to 75-fsrms Analog Fractional-N Sampling PLL with a Highly Linear
−231.4 dB with the conventional CP. DTC Incorporating Background DTC Gain Calibration and Refer-
ence Clock Duty Cycle Correction,” IEEE J. Solid-State Circuits,
5. Conclusion vol.54, no.5, pp.1254–1265, May 2019.
[9] Z. Berber, S. Kameche, and E. Benkhelifa, “Design of integer-N
PLL frequency synthesizer for E-band frequency for high phase
We proposed a noise-canceling CP circuit in this paper that noise performance in 5G communication systems,” IET Networks,
employs a capacitor CS instead of a current source to re- vol.9, no.1, pp.23–28, Jan. 2020.
alize offset phase operation in a low-noise CP. By care- [10] Z. Brezovic and V. Kudjak, “PLL phase-noise modeling by PC,”
ful designing the charge and discharge methods of the CS IEEE International Conference Radoelektronika, April 2009.
taking correlations into account, additional noise cancela- [11] C. Hangmann, C. Hedayat, and U. Hilleringmann, “Modeling and
characterization of CP-PLL phase noise in presence of dead zone,”
tion was achieved, and the trade-off between occupied area
IEEE International New Circuits and Systems Conference, pp.349–
and noise performance was mitigated. The simulated and 352, June 2014.
measured results indicated the effectiveness of the proposed [12] B. Razavi, RF Microelectronics 2nd edition, pp.611–646, published
CP. The proposed noise-canceling CP can be applied to re- by Prentice Hall, Sept. 2011.
URAKAWA et al.: A NOISE-CANCELING CHARGE PUMP FOR AREA EFFICIENT PLL DESIGN
633

[13] J. Vovnoboy, R. Levinger, and D. Elad, “Charge pump architecture [32] M.S.-W. Chen, “Digital Fractional-N Phase-Locked-Loop Design,”
with reduced medium and high frequency noise,” IEEE COMCAS, IEEE ISSCC, Tutorial6, Feb. 2020.
Nov. 2015. [33] M.S.-W. Chen, D. Su, and S. Mehta, “A calibration-free 800MHz
[14] F. Herzel, S.A. Osmany, and J.C. Scheytt, “Analytical Phase-Noise fractional-N digital PLL with embedded TDC,” IEEE JSSC, vol.45,
Modeling and Charge Pump Optimization for Fractional-N no.12, pp.2819–2827, Dec. 2010.
PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.57, no.8,
pp.1914–1924, Aug. 2010.
[15] S. Levantino, G. Marzin, C. Samori, and A.L. Lacaita, “A Wideband
Fractional-N PLL with Suppressed Charge-Pump Noise and Auto-
matic Loop Filter Calibration,” IEEE J. Solid-State Circuits, vol.48,
no.10, pp.2419–2429, Oct. 2013.
[16] D. Banerjee, “PLL performance, simulation, and design,” National
Semiconductor Corporation, 1998. http://cc.ee.nchu.edu.tw/˜aiclab/ Go Urakawa received B.E. and M.E.
public htm/PLL/Books/1998Banerjee.pdf degrees from Kyushu University, Fukuoka,
[17] C.-T. Ko, T.-K. Kuan, R.-P. Shen, and C.-H. Chang, “A 7-nm Japan, in 2002 and 2004 respectively. In
FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference 2004, he joined the circuit design section
Spur Featuring a Track-and-Hold Charge Pump and Automatic of high-frequency analog integrated circuit in
Loop Gain Control,” IEEE J. Solid-State Circuits, vol.55, no.4, Semiconductor Company, Toshiba Corporation,
pp.1043–1050, April 2020. Yokohama Japan, where he was engaged in the
[18] F.-L. Hsueh, Y.-C. Peng, C.-H. Chen, T.-J. Yeh, H.-H. Hsieh, C.-H. development of integrated PLLs. In 2017, he
Chang, S.-L. Liu, M.-C. Chuang, and M. Chen, “Analog/RF won- joined Kioxia Corporation, Kawasaki, Japan.
derland: Circuit and technology co-optimization in advanced finFET He has been engaged in research and devel-
technology,” IEEE Symposium on VLSI Technology, 2016. opment of an advanced circuit design on high
[19] H.-M. Chien, T.-H. Lin, B. Ibrahim, L. Zhang, M. Rofougaran, A. speed I/O.
Rofougaran, and W.J. Kaiser, “A 4GHz fractional-N synthesizer for
IEEE802.11a,” IEEE VLSI, pp.46–49, June 2004.
[20] H. Mo, G. Hu, and M.P. Kennedy, “Comparison of Analytical Pre-
dictions of the Noise Floor due to Static Charge Pump Mismatch in Hiroyuki Kobayashi received the B.E. de-
Fractional-N Frequency Synthesizers,” IEEE ISCAS, May 2016. gree in electronic engineering from the Osaka
[21] C.-L. Ti, Y.-H. Liu, and T.-H. Lin, “A 2.4-GHz Fractional-N PLL Institute of Technology, Osaka, Japan, in 1998
with a PFD/CP Linearization and an Improved CP Circuit,” IEEE and the M.E. degree in electronic engineering
International Symposium on Circuits and Systems, May 2008. from Osaka University, Suita, Japan, in 2000. In
[22] P.-E. Su and S. Pamarti, “Fractional-N Phase-Locked-Loop-Based 2000, he joined Toshiba Corporation, Kawasaki,
Frequency Synthesis: A Tutorial,” IEEE Trans. Circuits Syst. II, Japan, where he was involved in the research
Exp. Briefs, vol.56, no.12, pp.881–885, Dec. 2009. and development of analog and RF circuits for
[23] D. Gaied and E. Hegazi, “Charge-Pump Folded Noise Cancelation wireless communications. In 2017, he joined
in Fractional-N Phase-Locked Loops,” IEEE Trans. Circuits Syst. II, Kioxia Corporation, Kawasaki, Japan. He has
Exp. Briefs, vol.61, no.6, pp.378–382, April 2014. been engaged in research and development of an
[24] B. Razavi, “An Alternative Analysis of Noise Folding in advanced circuit design on high speed I/O.
Fractional-N Synthesizers,” IEEE ISCAS, May 2018.
[25] M.P. Kenedy, G. Hu, and V.S. Sadeghi, “Observations Concerning
Noise Floor and Spurs Caused by Static Charge Pump Mismatch
in Fractional-N Frequency Synthesizers,” ISSC 2014/CIICT 2014, Jun Deguchi received the B.E. and M.E. de-
June 2014. grees in machine intelligence and systems engi-
[26] V.S. Sadeghi, H.M. Naimi, and M.P. Kennedy, “The Role of Charge neering and the Ph.D. degree in bioengineering
Pump Mismatch in the Generation of Integer Boundary Spurs in and robotics from Tohoku University, Sendai,
Fractional-N Frequency Synthesizers: Why Worse Can Be Better,” Japan, in 2001, 2003, and 2006, respectively. In
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.60, no.2, pp.862–866, 2004, he was a Visiting Scholar at the University
Dec. 2013. of California, Santa Cruz, CA, USA. In 2006, he
[27] Z. Tang, X. Wan, M. Wang, and J. Liu, “A 50-to-930MHz Quadra- joined Toshiba Corporation, and was involved
ture-Output Fractional-N Frequency Synthesizer with 770-to- in design of analog/RF circuits for wireless
1860MHz Single-Inductor LC-VCO and Without Noise Folding Ef- communications, CMOS image sensors, high-
fect for Multistandard DTV Tuners,” IEEE ISSCC, pp.358–359, speed I/O, and accelerators for deep learning.
Feb. 2013. From 2014 to 2015, he was a Visiting Scientist at the MIT Media Lab,
[28] E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, Cambridge, MA, USA, and was involved in research on brain/neuro sci-
“A 700-kHz Bandwidth ΣΔ Fractional Synthesizer with Spurs ence. In 2017, he moved to Kioxia Corporation (formerly Toshiba Memory
Compensation and Linearization Techniques for WCDMA Appli- Corporation), and has been a Research Lead of an advanced circuit design
cations,” IEEE J. Solid-State Circuits, vol.39, no.9, pp.1446–1454, team working on high-speed I/O, deep learning/neuromorphic accelerators
Sept. 2004. and quantum annealing. Dr. Deguchi has served as a member of the tech-
[29] N. Hou and Z. Li, “Design of high performance CMOS charge pump nical program committee (TPC) of IEEE International Solid-State Circuits
for phase-locked loops synthesizer,” IEEE APCC, Oct. 2009. Conference (ISSCC) since 2016, and IEEE Asian Solid-State Circuits Con-
[30] H. Shao, K. Lin, B. Wang, C. Chen, F. Gao, F. Huang, and X. Wang, ference (A-SSCC) since 2017. He has also served as a TPC vice-chair of
“A High-Performance Charge Pump with Improved Static and IEEE A-SSCC 2019, and a review committee member of IEEE Interna-
Dynamic Matching Characteristic,” IEEE ASICON, Nov. 2015. tional Conference on Artificial Intelligence Circuits and Systems (AICAS)
[31] G. Urakawa, H. Kobayashi, J. Deguchi, and R. Fujimoto, “A Noise- 2020.
Canceling Charge Pump for Area Efficient PLL Design,” IEEE
RFIT, Sept. 2020.
 IEICE TRANS. ELECTRON., VOL.E104–C, NO.10 OCTOBER 2021
634

Ryuichi Fujimoto received his B.E., M.E.,

and Dr. Eng. degrees from Waseda University,
Tokyo, Japan, in 1988, 1990, and 2003, respec-
tively. He joined the Mobile Communication
Laboratory, Corporate Research and Develop-
ment Center, Toshiba Corporation, Kawasaki,
Japan, in 1991. Since then, he has been en-
gaged in the research and development of inte-
grated circuits and device models. In 2005, he
was transferred to Wireless & Multimedia LSI
Development Department, Toshiba Corp. Semi-
conductor Company. From 2009 to 2011, he was on loan to Semiconduc-
tor Technology Academic Research Center (STARC). After that, he was
with Center of Semiconductor Research & Development, Semiconductor
& Storage Products Company, Toshiba Corporation. Currently, he is with
Institute of Memory Technology Research and Development in Kioxia Cor-
poration. Dr. Fujimoto was an Associate Editor of IEICE Transactions on
Electronics from 2001 to 2004, IEICE Electronics Express (ELEX) from
2003 to 2008, and IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences from 2005 to 2009. He was a
secretary of the Japan Chapter of IEEE Circuits and Systems Society from
2008 to 2009. Currently, he is a chair of the Japan Chapter of IEEE Solid-
State Circuits Society. He is a member of the IEEE, IEEJ and JAAS.