Datasheet

PROGRAMMABLE TIMING CONTROL HUB FOR 9LRS3197

INTEL BASED SYSTEMS

Recommended Application: Features/Benefits:

CK505 version 1-1 clock, with fully integrated voltage regulators • Supports spread spectrum modulation, 0 to -0.5%
and series resistors down spread for CPU and SRC clocks
• Uses external 14.318MHz crystal, external crystal
Output Features: load caps are required for frequency tuning
• 2 - CPU differential low power push-pull pairs
• 1 - SRC differential low power push-pull pair Key Specifications:
• 1 - SATA differential low power push-pull pair • CPU outputs cycle-cycle jitter < 85ps
• 1 - DOT differential low power push-pull pair • SRC outputs cycle-cycle jitter < 125ps
• 1 - REF, able to drive 3 loads, 14.318MHz • +/- 100ppm frequency accuracy on all clocks
• 1 - 27MHz_SS/non_SS single-ended output pair

Pin Configuration

CLKPWRGD/PD#_3.3
REF_3L/FSLC_3.3**
VDDREF_3.3
SDATA_3.3
SCLK_3.3

GNDREF
X1
X2

32 31 30 29 28 27 26 25
VDDDOT96MHz_3.3 1 24 VDDCPU_3.3
GNDDOT96MHz 2 23 CPUT0_LPR
DOT96T_LPR 3 22 CPUC0_LPR
DOT96C_LPR 4 21 GNDCPU
VDD_27MHz 5 9LRS3197 20 CPUT1_LPR
27MHz_nonSS 6 19 CPUC1_LPR
27MHz_SS 7 18 VDDCPU_IO
GND27MHz 8 17 VDDSRC_3.3
9 10 11 12 13 14 15 16
GNDSATA
SATAT_LPR
SATAC_LPR
GNDSRC
SRCT1_LPR
SRCC1_LPR
VDDSRC_IO
*CPU_STOP#

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor
32-pin MLF
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Pin Description
Pin# Pin Name Type Pin Description
1 VDDDOT96MHz_3.3 PWR Power pin for the DOT96MHz output 3.3V.
2 GNDDOT96MHz PWR Ground pin for the DOT96MHz output
True clock DOT96 output with integrated 33ohm series resistor. No
3 DOT96T_LPR OUT
50ohm resistor to GND needed.
Complement clock DOT96 output with integrated 33ohm series
4 DOT96C_LPR OUT
resistor. No 50ohm resistor to GND needed.
5 VDD_27MHz PWR Power pin for the 27MHz output 3.3V.
6 27MHz_nonSS OUT 27MHz non-spread output, 3.3V
7 27MHz_SS OUT 27MHz spread output, 3.3V
8 GND27MHz PWR Ground pin for the 27MHz output
9 GNDSATA PWR Ground pin for the SATA output 3.3V.
True clock of differential 0.8V push-pull SATA output with integrated
10 SATAT_LPR OUT
33ohm series resistor. No 50ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SATA output with
11 SATAC_LPR OUT integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
12 GNDSRC PWR Ground pin for the SRC outputs
True clock of differential 0.8V push-pull SRC output with integrated
13 SRCT1_LPR OUT
33ohm series resistor. No 50ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SRC output with
14 SRCC1_LPR OUT integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
15 VDDSRC_IO PWR 1.05V to 3.3V from external power supply
16 *CPU_STOP# IN Stops all CPU clocks, except those set to be free running clocks
17 VDDSRC_3.3 PWR Supply for SRC clocks, 3.3V nominal
18 VDDCPU_IO PWR 1.05V to 3.3V from external power supply
Complementary clock of differential pair 0.8V push-pull CPU outputs
19 CPUC1_LPR OUT with integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
True clock of differential pair 0.8V push-pull CPU outputs with
20 CPUT1_LPR OUT integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
21 GNDCPU PWR Ground pin for the CPU outputs
Complementary clock of differential pair 0.8V push-pull CPU outputs
22 CPUC0_LPR OUT with integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
True clock of differential pair 0.8V push-pull CPU outputs with
23 CPUT0_LPR OUT integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
24 VDDCPU_3.3 PWR Supply for CPU clocks, 3.3V nominal
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or
25 CLKPWRGD/PD#_3.3 IN
PWRDWN# mode
26 GNDREF PWR Ground pin for the REF outputs.
27 X2 OUT Crystal output, Nominally 14.318MHz
28 X1 IN Crystal input, Nominally 14.318MHz.
29 VDDREF_3.3 PWR Power pin for the XTAL and REF clocks, nominal 3.3V
14.318 MHz reference clock, which can drive 3 loads / 3.3V tolerant
30 REF_3L/FSLC_3.3** I/O input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
31 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
32 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.

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General Description
The 9LRS3197 is a CK505 clock synthesizer. The 9LRS3197 provides a single-chip solution for Intel based systems. The
9LRS3197 is driven with a 14.318MHz crystal.

Functional Block Diagram

Xtal

REFCLK

Prog.SS
27MHz_SS
PLL3

SRC
Prog.SS SRC(1)

PLL1 CP UCLK
CPUCLK(1:0)

SATA_nonS

0
Fixed SATA
1
PLL2
B0b1
COUT_DIV

27M Hz_no nSS

SRC0

DOT96M Hz

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Table 1: CPU Frequency Select Table

FSLC CPU SRC REF DOT
B0b7 MHz MHz MHz MHz
0 (Default) 133.33
100.00 14.318 96.00
1 100.00
1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.

Table 2: pin 6, 7 Configuration

Pin 6 Pin 7 Spread
B1b3 B1b2 B1b1 Comment
MHz MHz %
0 0 0 27MHz_nonSS 27MHz_SS -1.75%
0 0 1 27MHz_nonSS 27MHz_SS +-0.5%
0 1 0 27MHz_nonSS 27MHz_SS -0.5% Default
0 1 1 27MHz_nonSS 27MHz_SS -1%
1 0 0 27MHz_nonSS 27MHz_SS -1.5%
1 0 1 27MHz_nonSS 27MHz_SS -2%
1 1 0 27MHz_nonSS 27MHz_SS -0.75%
1 1 1 27MHz_nonSS 27MHz_SS -1.25%

IO_Vout Select Table

b2 b1 b0 IO_Vout
0 0 0 N/A
0 0 0 N/A
0 1 0 0.5V
0 1 1 0.6V
1 0 0 0.7V
1 0 1 0.8V
1 1 0 0.9V
1 1 1 1.0V
* Bold is default

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General SMBus serial interface information for the 9LRS3197

How to Write: How to Read:

• Controller (host) sends a start bit. • Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H) • Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge • ICS clock will acknowledge
• Controller (host) sends the beginning byte location = N • Controller (host) sends the begining byte
• ICS clock will acknowledge location = N
• Controller (host) sends the data byte count = X • ICS clock will acknowledge
• ICS clock will acknowledge • Controller (host) will send a separate start bit.
• Controller (host) starts sending Byte N through • Controller (host) sends the read address D3 (H)
Byte N + X -1 • ICS clock will acknowledge
• ICS clock will acknowledge each byte one at a time • ICS clock will send the data byte count = X
• Controller (host) sends a Stop bit • ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit

Index Block Write Operation Index Block Read Operation

Controller (Host) ICS (Slave/Receiver) Controller (Host) ICS (Slave/Receiver)
T starT bit T starT bit
Slave Address D2(H) Slave Address D2(H)
WR WRite WR WRite
ACK ACK
Beginning Byte = N Beginning Byte = N
ACK ACK
Data Byte Count = X RT Repeat starT
ACK Slave Address D3(H)
Beginning Byte N RD ReaD
ACK ACK
X Byte

Data Byte Count = X

ACK
Beginning Byte N
Byte N + X - 1 ACK
ACK
X Byte

P stoP bit

Byte N + X - 1
N Not acknowledge
P stoP bit

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Byte 0 FS Readback and PLL Selection Register
Bit Name Description Type 0 1 Default
7 FSLC CPU Freq. Sel. Bit R Latch
6 Reserved Reserved RW - - 0
5 Reserved Reserved RW - - 1
RW
4 iAMT_EN Set via SMBus Legacy Mode iAMT Enabled 0
(Sticky "1")
3 Reserved Reserved RW 0
2 Reserved Reserved RW Reserved Reserved 0
SATA (SRC2 100MHz_SS) SATA (100MHz non_SS)
1 SATA_SEL Select source for SATA clock RW 0
= SRC_Main = SATA PLL
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-
0 PD_Restore RW Configuration Not Saved Configuration Saved 1
on and go to latches open state
This bit is ignored and treated at '1' if device is in
iAMT mode.

Byte 1 DOT96 Select and PLL3 Quick Config Register,

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 1
6 CK505 PLL1_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0
5 Reserved Reserved RW - - 1
4 PLL3_CF3 PLL3 Quick Config Bit 3 RW 0
3 PLL3_CF2 PLL3 Quick Config Bit 2 RW 0
See Table 2: pin 6/7 Configuration
2 PLL3_CF1 PLL3 Quick Config Bit 1 RW 1
1 PLL3_CF0 PLL3 Quick Config Bit 0 RW 0
0 Reserved Reserved RW - - 1

Byte 2 Output Enable Register

Bit Name Description Type 0 1 Default
Output enable for REF0, if disabled output is tri-
7 REF_3L_OE RW Output Disabled Output Enabled 1
stated
6 Reserved Reserved RW - - 1
5 Reserved Reserved RW - - 1
4 Reserved Reserved RW - - 1
3 Reserved Reserved RW - - 1
2 Reserved Reserved RW - - 1
1 Reserved Reserved RW - - 1
0 Reserved Reserved RW - - 1

Byte 3 Output Enable Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 1
6 Reserved Reserved RW - - 1
5 Reserved Reserved RW - - 1
4 Reserved Reserved RW - - 1
3 Reserved Reserved RW - - 1
2 Reserved Reserved RW - - 1
1 Reserved Reserved RW 1
0 Reserved Reserved RW - - 1

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Byte 4 Output Enable and Spread Spectrum Disable Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 1
6 SATA_OE Output enable for SATA RW Output Disabled Output Enabled 1
5 SRC1_OE Output enable for SRC1 RW Output Disabled Output Enabled 1
4 DOT96_OE Output enable for DOT96 RW Output Disabled Output Enabled 1
3 CPU1_OE Output enable for CPU1 RW Output Disabled Output Enabled 1
2 CPU0_OE Output enable for CPU0 RW Output Disabled Output Enabled 1
00=All Spread OFF
1 SSC_EN1 (MSB) SSC_EN1 (MSB) RW 1
01=Reserved
10=Reserved
0 SSC_EN0 (LSB) SSC_EN0 (LSB) RW 11=All Spread ON 1

Byte 5 Reserved Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 1
6 Reserved Reserved RW - - 1
5 Reserved Reserved RW - - 1
4 Reserved Reserved RW - - 1
3 Reserved Reserved RW - - 1
2 Reserved Reserved RW - - 1
1 Reserved Reserved RW - - 1
0 Reserved Reserved RW - - 1

Byte 6 Slew Rate Control Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 0
6 Reserved Reserved RW - - 0
5 REF Slew Slew Rate Control RW 2 V/ns 1 V/ns 0
4 Reserved Reserved RW - - 0
3 27MHz Slew Slew Rate Control RW 2 V/ns 1 V/ns 0
2 Reserved Reserved RW - - 0
1 Reserved Reserved RW - - 0
0 Reserved Reserved RW - - 0

Byte 7 Vendor ID/ Revision ID

Bit Name Description Type 0 1 Default
7 Rev Code Bit 3 R 0
6 Rev Code Bit 2 R 0
Revision ID
5 Rev Code Bit 1 R 0
4 Rev Code Bit 0 R 0
Vendor specific
3 Vendor ID bit 3 R 0
2 Vendor ID bit 2 Vendor ID R 0
1 Vendor ID bit 1 ICS is 0001, binary R 0
0 Vendor ID bit 0 R 1

Byte 8 Device ID and Output Enable Register

Bit Name Description Type 0 1 Default
7 Device_ID3 R 1
6 Device_ID2 Table of Device identifier codes, used for R 0
See Device ID Table
5 Device_ID1 differentiating between CK505 package options, etc. R 0
4 Device_ID0 R 0
3 Reserved Reserved RW - - 0
2 Reserved Reserved RW - - 0
1 27MHz_nonSS_OE Output enable for 27MHz_nonSS RW Disabled Enabled 1
0 27MHz_SS_OE Output enable for 27MHz_SS RW Disabled Enabled 1

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Byte 9 Output Control Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 0
6 Reserved Reserved R - - 0
5 Reserved Reserved RW - - 1
4 Reserved Reserved RW - - 0
3 Reserved Reserved RW - - 0
2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1
See Table 3: V_IO Selection
1 IO_VOUT1 IO Output Voltage Select RW 0
(Default is 0.8V)
0 IO_VOUT0 IO Output Voltage Select (Least Significant Bit) RW 1

Byte 10 Output Control Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW - - 0
6 Reserved Reserved RW - - 0
5 Reserved Reserved RW - - 0
4 Reserved Reserved RW - - 0
3 Reserved Reserved RW - - 0
2 Reserved Reserved RW - - 0
1 CPU 1 Stop Enable Enables control of CPU1 with CPU_STOP# RW Free Running Stoppable 1
0 CPU 0 Stop Enable Enables control of CPU 0 with CPU_STOP# RW Free Running Stoppable 1

Byte 11 Reserved Register

Bit Name Description Type 0 1 Default
7 Reserved Reserved RW 0
6 Reserved Reserved RW 0
5 Reserved Reserved RW 0
4 Reserved Reserved RW 0
3 Reserved Reserved RW - - 0
2 CPU1_AMT_EN M1 mode clk enable RW Disable Enable 1
1 PCI-E_GEN2 Determines if PCI-E Gen2 compliant R non-Gen2 PCI-E Gen2 Compliant 1
0 Reserved Reserved RW - - 1

Byte 12 Byte Count Register

Bit Name Description Type 0 1 Default
7 Reserved RW 0
6 Reserved RW 0
5 BC5 RW 0
4 BC4 RW 0
3 BC3 Read Back byte count register, RW 1
2 BC2 max bytes = 32 RW 1
1 BC1 RW 0
0 BC0 RW 1

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Absolute Maximum Ratings - DC Parameters
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V 7
Maximum Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 3.8 V 7
Maximum Input Voltage VIH 3.3V Inputs 4.6 V 4,5,7
Minimum Input Voltage VIL Any Input GND - 0.5 V 4,7
°
Storage Temperature Ts - -65 150 C 4,7
Input ESD protection ESD prot Human Body Model 2000 V 6,7
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied, nor guaranteed.
3
Maximum input voltage is not to exceed VDD

Electrical Characteristics - Input/Supply/Common Output DC Parameters

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Ambient Operating Temp Tambient - 0 70 °C
Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V
Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.9975 3.465 V
Input High Voltage VIHSE Single-ended 3.3V inputs 2 VDD + 0.3 V 3
Input Low Voltage VILSE Single-ended 3.3V inputs VSS - 0.3 0.8 V 3
Low Threshold Input- FSC = '1' Voltage VIH_FSC 3.3 V +/-5% 0.7 3.5 V
Low Threshold Input-Low Voltage VIL_FSC 3.3 V +/-5% VSS - 0.3 0.35 V
Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 2
Inputs with pull up or pull down resistors
Input Leakage Current IINRES -200 200 uA
V IN = VDD , VIN = GND
Output High Voltage VOHSE Single-ended outputs, IOH = -1mA 2.4 V 1
Output Low Voltage VOLSE Single-ended outputs, IOL = 1 mA 0.4 V 1
IDDOP3.3 Full Active, CL = Full load; Idd 3.3V 125 mA
Operating Supply Current
IDDOP IO Full Active, CL = Full load; IDD IO 28 mA
Input Frequency Fi VDD = 3.3 V 15 MHz
Pin Inductance Lpin 7 nH
CIN Logic Inputs 1.5 5 pF
Input Capacitance COUT Output pin capacitance 6 pF
CINX X1 & X2 pins 6 pF
From VDD Power-Up or de-assertion of PD to 1st
Clk Stabilization T STAB 1.8 ms
clock
Tfall_SE TFALL 10 ns
Fall/rise time of all 3.3V control inputs from 20-80%
Trise_SE TRISE 10 ns
SMBus Voltage V DD 2.7 5.5 V
Low-level Output Voltage VOLSMB @ IPULLUP 0.4 V
Current sinking at VOLSMB = 0.4 V IPULLUP SMB Data Pin 4 mA
SCLK/SDATA (Max VIL - 0.15) to
TRI2C 1000 ns
Clock/Data Rise Time (Min VIH + 0.15)
SCLK/SDATA (Min VIH + 0.15) to
T FI2C 300 ns
Clock/Data Fall Time (Max VIL - 0.15)
Maximum SMBus Operating Frequency F SMBUS 100 kHz
Spread Spectrum Modulation Frequency fSSMOD Triangular Modulation 30 33 kHz

Electrical Characteristics - Input/Supply/Common Output DC ParametersDC Parameters: (unless otherwise noted, guaranteed by design and
characterization, not 100% tested in production).
1
Signal is required to be monotonic in this region.
2
input leakage current does not include inputs with pull-up or pull-down resistors
3
3.3V referenced inputs are: SCLK, SDATA, and CKPWRGD if selected.
4
Intentionally blank
5
Maximum VIH is not to exceed VDD
6
Human Body Model
7
Operation under these conditions is neither implied, nor guaranteed.
8
Frequency Select pins which have tri-level input

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AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate tSLR Averaging on 2.5 5 V/ns 2, 3
Falling Edge Slew Rate tFLR Averaging on 2.5 5 V/ns 2, 3
Slew Rate Variation tSLVAR Averaging on 20 % 1, 6
Differential Voltage Swing VSWING Averaging off 300 mV 2
Crossing Point Voltage VXABS Averaging off 300 550 mV 1,4,5
Crossing Point Variation VXABSVAR Averaging off 140 mV 1,4,9
Maximum Output Voltage VHIGH Averaging off 1150 mV 1,7
Minimum Output Voltage VLOW Averaging off -300 mV 1,8
Duty Cycle DCYC Averaging on 45 55 % 2
CPU Skew CPUSKEW Averaging on 100 ps
SRC_SATA Skew SRCSKEW Differential Measurement 300 ps 1
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Measurement taken for single ended waveform on a component test board (not in system)
2
Measurement taken from differential waveform on a component test board. (not in system)
3
Slew rate emastured through V_swing voltage range centered about differential zero
4
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
5
Only applies to the differential rising edge (Clock rising, Clock# falling)
6
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where
Clock rising meets Clock# falling. The median cross point is used to calculate the voltage
7
The max voltage including overshoot.
8
The min voltage including undershoot.
9
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to
limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute

Clock Jitter Specifications - Low Power Differential Outputs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
CPU Jitter - Cycle to Cycle CPUJC2C Differential Measurement 85 ps 1,2
SRC Jitter - Cycle to Cycle SRCJC2C Differential Measurement 125 ps 1,2,3
SATA Jitter - Cycle to Cycle SATAJC2C Differential Measurement 125 ps 1,2
DOT Jitter - Cycle to Cycle DOTJC2C Differential Measurement 250 ps 1,2
tjphasePLL PCIe Gen 1 86 ps (p-p) 1,2
PCIe Gen 2 ps
SRC Phase Jitter tjphaseLo 3 1,4
10kHz < f < 1.5MHz (RMS)
PCIe Gen 2 ps
tjphaseHigh 3.1 1,4
1.5MHz < f < Nyquist (50MHz) (RMS)
*TA = 0 - 70°C; Supply Voltage VDD = 3.3V+/-5%, Rs = 0ohms, CL = 2pF
1
Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.
2
JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system
performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver requirements.
3
Phase jitter requirement: The deisgnated Gen2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is
performed on a component test board under quiet condittions with all outputs on.
4
See http://www.pcisig.com for complete specs

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Electrical Characteristics - REF-14.318MHz

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values -100 100 ppm 2, 4
Clock period Tperiod 14.318MHz output nominal 69.82033 69.86224 ns 2, 3
Absolute min/max period Tabs 14.318MHz output nominal 69.83400 70.84800 ns 2
CLK High Time THIGH 29.97543 38.46654 V
CLK Low time TLOW 29.57543 38.26654 V
Output High Voltage VOH IOH = -1 mA 2.4 V
Output Low Voltage VOL IOL = 1 mA 0.4 V
VOH @MIN = 1.0 V,
Output High Current IOH -33 -33 mA
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
Output Low Current IOL 30 38 mA
VOL @MAX = 0.4 V
Rising Edge Slew Rate tSLR Measured between 0.8V and 2.0V 1 4 V/ns 1
Falling Edge Slew Rate tFLR Measured between 2.0V and 0.8V 1 4 V/ns 1
Duty Cycle dt1 VT = 1.5 V 45 55 % 2
Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 1000 ps 2

NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Edge rate is measured between 0.8V to 2.0V.
2
Duty cycle, Peroid and Jitter are measured with respect to 1.5V
3
The average period over any 1us period of time

4
Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz

Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
-50 50 1,2
Long Accuracy ppm see Tperiod min-max values ppm
-15 15 1,2,3
Clock period Tperiod 27.000MHz output nominal 37.0365 37.0376
Output High Voltage VOH IOH = -1 mA 2.4 V 1
Output Low Voltage VOL IOL = 1 mA 0.55 V 1
V OH @MIN = 1.0 V -29 mA 1
Output High Current IOH
VOH@MAX = 3.135 V -23 mA 1
VOL @ MIN = 1.95 V 29 mA 1
Output Low Current IOL
VOL @ MAX = 0.4 V 27 mA 1
Rising Edge Rate tslewr/r Measured between 0.8V and 2.0V 1 4 V/ns 1
Falling Edge Rate tslewr/f Measured between 2.0V and 0.8V 1 4 V/ns 1
Duty Cycle dt1 VT = 1.5 V 45 55 % 1
tltj Long Term (10us) 800 ps 1,4
Jitter tjpk-pk -250 250 ps 1
tjcyc-cyc VT = 1.5 V 500 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
At nominal voltage and temperature
4
27MHz-Non-spread only

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THERMALLY ENHANCED, VERY THIN, FINE PITCH

QUAD FLAT / NO LEAD PLASTIC PACKAGE

DIMENSIONS DIMENSIONS
ICS 32L
SYMBOL MIN. MAX. SYMBOL TOLERANCE
A 0.8 1.0 N 32
A1 0 0.05 ND 8
A3 0.20 Reference NE 8
b 0.18 0.3 D x E BASIC 5.00 x 5.00
e 0.50 BASIC D2 MIN. / MAX. 3.0/ 3.3
E2 MIN. / MAX. 3.0/ 3.3
Marking Diagram L MIN. / MAX. 0.30 / 0.50

Ordering Information

Part / Order Number Shipping Packaging Package Temperature

9LRS3197AKLF Trays 32-pin MLF 0 to +70° C
9LRS3197AKLFT T ape and Reel 32-pin MLF 0 to +70° C

"A" is the device revision designator (will not correlate to the datasheet revision)
"LF" denotes Pb-free, R oH S compliant package

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Revision History
Rev. Issue Date Description Page #
A 01/17/11 Release to final
Updated "Electrical Characteristics - Input/Supply/Common Output D C
B 07/29/11 Parameters" table
C 08/22/11 Updated Electrical parameters and ordering info table 9-12

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