FemtoClock® NG Universal Frequency IDT8T49N205I

Translator with Phase Build-Out

DATA SHEET

General Description Features

The IDT8T49N205I is a highly flexible FemtoClock® NG general • Fourth Generation FemtoClock® NG technology
purpose, low phase noise Frequency Translator / Synthesizer with
Phase Build-Out (PBO) suitable for networking and communications
• Universal Frequency Translator/Frequency Synthesizer
applications. It is able to generate any output frequency in the • Zero ppm frequency translation
0.98MHz - 312.5MHz range and most output frequencies in the
312.5MHz - 1,300MHz range (see Table 3 for details). A wide range
• Two outputs, individually programmable as LVPECL or LVDS
of input reference clocks and a range of low-cost fundamental mode • Both outputs may be set to use 2.5V or 3.3V output levels
crystal frequencies may be used as the source for the output
frequency.
• Programmable output frequency: 0.98MHz up to 1,300MHz

The IDT8T49N205I has three operating modes to support a very • Two differential inputs support the following input types:
broad spectrum of applications: LVPECL, LVDS, LVHSTL, HCSL
1 Frequency Synthesizer • Input frequency range: 8kHz - 710MHz

• Synthesizes output frequencies from a 16MHz - 40MHz • Phase Build-Out minimizes output phase change on switchover
fundamental mode crystal. • Crystal input frequency range: 16MHz - 40MHz
• Fractional feedback division is used, so there are no • Two factory-set register configurations for power-up default state
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy. • Power-up default configuration pin or register selectable

2) High-Bandwidth Frequency Translator • Configurations customized via One-Time Programmable ROM

• Applications: PCI Express, Computing, General Purpose • Settings may be overwritten after power-up via I2C

• Translates any input clock in the 16MHz - 710MHz frequency • I2C Serial interface for register programming
range into any supported output frequency. • RMS phase jitter at 155.52MHz, using a 40MHz crystal
• This mode has a high PLL loop bandwidth in order to track input (12kHz - 20MHz): 378fs (typical), Low Bandwidth Mode (FracN)
reference changes, such as Spread-Spectrum Clock • Output supply voltage modes:
modulation, so it will not attenuate much jitter on the input VCC/VCCA/VCCO
reference. 3.3V/3.3V/3.3V
3) Low-Bandwidth Frequency Translator 3.3V/3.3V/2.5V
2.5V/2.5V/2.5V
• Applications: Networking & Communications.
• -40°C to 85°C ambient operating temperature
• Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz
Pin Assignment
range and makes use of an external crystal to provide
LOCK_IND

significant jitter attenuation.

VCCO
OE0

OE1
nQ0

nQ1
VCC

VEE

This device provides two factory-programmed default power-up

Q0

Q1

configurations burned into One-Time Programmable (OTP) memory.

The configuration to be used is selected by the CONFIG pin. The two 30 29 28 27 26 25 24 23 22 21
configurations are specified by the customer and are programmed by CLK_ACTIVE 31 20 nc
IDT during the final test phase from an on-hand stock of blank nc 32 19 nc
devices. The two configurations may be completely independent of LF0 33 IDT8T49N205I 18 S_A0
one another. LF1 34 17 S_A1
40 Lead VFQFN
VEE 35 16 CONFIG
One usage example might be to install the device on a line card with 6mm x 6mm x 0.925mm
VCCA 36 15 SCLK
two optional daughter cards: an OC-12 option requiring a 622.08MHz EPad 4.65mm x 4.65mm
HOLDOVER 37 14 SDATA
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet NL Package
CLK0BAD 38 13 VCC
option requiring a 125MHz LVPECL clock translated from the same Top View
CLK1BAD 39 12 PLL_BYPASS
19.44MHz input reference.
XTALBAD 40 11 nc
To implement other configurations, these power-up default settings 1 2 3 4 5 6 7 8 9 10
can be overwritten after power-up using the I2C interface and the
CLK1
VCC
CLK_SEL

nCLK1
XTAL_IN

VCC
VEE
CLK0
nCLK0
XTAL_OUT

device can be completely reconfigured. However, these settings

would have to be re-written next time the device powers-up.

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Complete Block Diagram

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Pin Descriptions and Characteristics

Table 1. Pin Descriptions
Number Name Type Description

1 XTAL_IN Crystal Oscillator interface designed for 12pF parallel resonant crystals.
Input
2 XTAL_OUT XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.
3, 7, 13, 29 VCC Power Core supply pins. All must be either 3.3V or 2.5V.
Input clock select. Selects the active differential clock input.
LVCMOS/LVTTL interface levels.
4 CLK_SEL Input Pulldown
0 = CLK0, nCLK0 (default)
1 = CLK1, nCLK1
5 CLK0 Input Pulldown Non-inverting differential clock input.
Pullup/ Inverting differential clock input. VCC/2 default when left floating (set by the
6 nCLK0 Input
Pulldown internal pullup and pulldown resistors).
8, 21, 35 VEE Power Negative supply pins.
9 CLK1 Input Pulldown Non-inverting differential clock input.
Pullup/ Inverting differential clock input. VCC/2 default when left floating (set by the
10 nCLK1 Input
Pulldown internal pullup and pulldown resistors).
11, 19,
nc Unused No connect. These pins are to be left unconnected.
20, 32
Bypasses the VCXO PLL. In bypass mode, outputs are clocked off the
PLL_BYPAS falling edge of the input reference. LVCMOS/LVTTL interface levels.
12 Input Pulldown
S 0 = PLL Mode (default)
1 = PLL Bypassed
14 SDATA I/O Pullup I2C Data Input/Output. Open drain.
15 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels.
Configuration Pin. Selects between one of two factory programmable
pre-set power-up default configurations. The two configurations can have
different output/input frequency translation ratios, different PLL loop
16 CONFIG Input Pulldown bandwidths, etc. These default configurations can be overwritten after
power-up via I2C if the user so desires. LVCMOS/LVTTL interface levels.
0 = Configuration 0 (default)
1 = Configuration 1
17 S_A1 Input Pulldown I2C Address Bit 1. LVCMOS/LVTTL interface levels.
18 S_A0 Input Pulldown I2C Address Bit 0. LVCMOS/LVTTL interface levels.
Active High Output Enable for Q1, nQ1. LVCMOS/LVTTL interface levels.
22 OE1 Input Pullup 0 = Output pins high-impedance
1 = Output switching (default)
Differential output pair. Output type is programmable to LVDS or LVPECL
23, 24 nQ1, Q1 Output
interface levels.
25 VCCO Power Output supply pins for Q1, nQ1 and Q0, nQ0 outputs. Either 2.5V or 3.3V.
Differential output pair. Output type is programmable to LVDS or LVPECL
26, 27 nQ0, Q0 Output
interface levels.
Active High Output Enable for Q0, nQ0. LVCMOS/LVTTL interface levels.
28 OE0 Input Pullup 0 = Output pins high-impedance
1 = Output switching (default)
Lock Indicator - indicates that the PLL is in a locked condition.
30 LOCK_IND Output
LVCMOS/LVTTL interface levels.

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Number Name Type Description

Indicates which of the two differential clock inputs is currently selected.
LVCMOS/LVTTL interface levels.
31 CLK_ACTIVE Output
0 = CLK0, nCLK0 differential input pair
1 = CLK1, nCLK1 differential input pair
33, 34 LF0, LF1 Analog I/O Loop filter connection node pins. LF0 is the output. LF1 is the input.
Analog supply voltage. See Applications section for details on how to
36 VCCA Power
connect this pin.
Alarm output reflecting if the device is in a holdover state. LVCMOS/LVTTL
interface levels.
37 HOLDOVER Output
0 = Device is locked to a valid input reference
1 = Device is not locked to a valid input reference
Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.
38 CLK0BAD Output 0 = Input Clock 0 is switching within specifications
1 = Input Clock 0 is out of specification
Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.
39 CLK1BAD Output 0 = Input Clock 1 is switching within specifications
1 = Input Clock 1 is out of specification
Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.
40 XTALBAD Output 0 = crystal is switching within specifications
1 = crystal is out of specification
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 3.5 pF
RPULLUP Input Pullup Resistor 51 k
RPULLDOWN Input Pulldown Resistor 51 k

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Functional Description
The IDT8T49N205I is designed to provide two copies of almost any device may be designed into a communications line card that
desired output frequency within its operating range (0.98 - 1300MHz) supports different I/O modules such as a standard OC-12 module
from any input source in the operating range (8kHz - 710MHz). It is running at 622.08MHz or a (255/237) FEC rate OC-12 module
capable of synthesizing frequencies from a crystal or crystal running at 669.32MHz. The different I/O modules would result in a
oscillator source. The output frequency is generated regardless of different level on the CONFIG pin which would select different divider
the relationship to the input frequency. The output frequency will be ratios within the IDT8T49N205I for the two different card
exactly the required frequency in most cases. In most others, it will configurations. Access via I2C would not be necessary for operation
only differ from the desired frequency by a few ppb. IDT configuration using either of the internal configurations.
software will indicate the frequency error, if any. The IDT8T49N205I
can translate the desired output frequency from one of two input Operating Modes
clocks. Again, no relationship is required between the input and
output frequencies in order to translate to the output clock rate. In this The IDT8T49N205I has three operating modes which are set by the
frequency translation mode, a low-bandwidth, jitter attenuation option MODE_SEL[1:0] bits. There are two frequency translator modes -
is available that makes use of an external fixed-frequency crystal or low bandwidth and high bandwidth and a frequency synthesizer
crystal oscillator to translate from a noisy input source. If the input mode. The device will operate in the same mode regardless of which
clock is known to be fairly clean or if some modulation on the input configuration is active.
needs to be tracked, then the high-bandwidth frequency translation
mode can be used, without the need for the external crystal. Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configurations
The input clock references and crystal input are monitored of the device.
continuously and appropriate alarm outputs are raised both as
register bits and hard-wired pins in the event of any Output Dividers & Supported Output Frequencies
out-of-specification conditions arising. Clock switching is supported In all 3 operating modes, the output stage behaves the same way, but
in manual, revertive & non-revertive modes. different operating frequencies can be specified in the two
configurations.
The IDT8T49N205I has two factory-programmed configurations that
may be chosen from as the default operating state after reset. This is The internal VCO is capable of operating in a range anywhere from
intended to allow the same device to be used in two different 1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of
applications without any need for access to the I2C registers. These the desired output frequency that results in a VCO operating
defaults may be over-written by I2C register access at any time, but frequency within that range. The output divider stage N[10:0] is
those over-written settings will be lost on power-down. Please limited to selection of integers from 2 to 2046. Please refer to Table 3
contact IDT if a specific set of power-up default settings is desired. for the values of N applicable to the desired output frequency.

Configuration Selection Table 3. Output Divider Settings & Frequency Ranges

The IDT8T49N205I comes with two factory-programmed default Register Frequency Minimum Maximum
configurations. When the device comes out of power-up reset the Setting Divider fOUT fOUT
selected configuration is loaded into operating registers. The Nn[10:0] N (MHz) (MHz)
IDT8T49N205I uses the state of the CONFIG pin or CONFIG register
bit (controlled by the CFG_PIN_REG bit) to determine which 0000000000x 2 997.5 1300
configuration is active. When the output frequency is changed either 00000000010 2 997.5 1300
via the CONFIG pin or via internal registers, the output behavior may
not be predictable during the register writing and output settling 00000000011 3 665 866.7
periods. Devices sensitive to glitches or runt pulses may have to be
00000000100 4 498.75 650
reset once reconfiguration is complete.
00000000101 5 399 520
Once the device is out of reset, the contents of the operating registers
0000000011x 6 332.5 433.3
can be modified by write access from the I2C serial port. Users that
have a custom configuration programmed may not require I2C 0000000100x 8 249.4 325
access.
0000000101x 10 199.5 260
It is expected that the IDT8T49N205I will be used almost exclusively ... Even N 1995 / N 2600 / N
in a mode where the selected configuration will be used from device
power-up without any changes during operation. For example, the 1111111111x 2046 0.98 1.27

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Frequency Synthesizer Mode

This mode of operation allows an arbitrary output frequency to be The input reference frequency range is now extended up to 710MHz.
generated from a fundamental mode crystal input. For improved A pre-divider stage P is needed to keep the operating frequencies at
phase noise performance, the crystal input frequency may be the phase detector less than 100MHz.
doubled. As can be seen from the block diagram in Figure 1, only the
upper feedback loop is used in this mode of operation. It is Low-Bandwidth Frequency Translator Mode
recommended that CLK0 and CLK1 be left unused in this mode of As can be seen from the block diagram in Figure 3, this mode
operation. involves two PLL loops. The lower loop with the large integer dividers
is the low bandwidth loop and it sets the output-to-input frequency
The upper feedback loop supports a delta-sigma fractional feedback translation ratio.This loop drives the upper DCXO loop (digitally
divider. This allows the VCO operating frequency to be a non-integer controlled crystal oscillator) via an analog-digital converter.
multiple of the crystal frequency. By using an integer multiple only,
lower phase noise jitter on the output can be achieved, however the
use of the delta-sigma divider logic will provide excellent
performance on the output if a fractional divisor is used.

Figure 3. Low Bandwidth Frequency Translator Mode

Block Diagram
The pre-divider stage is used to scale down the input frequency by
an integer value to achieve a frequency in this range. By dividing
Figure 1. Frequency Synthesizer Mode Block Diagram down the fed-back VCO operating frequency by the integer divider
High-Bandwidth Frequency Translator Mode M1[16:0] to as close as possible to the same frequency, exact output
This mode of operation is used to translate one of two input clocks of frequency translations can be achieved. For improved phase noise
the same nominal frequency into an output frequency with little jitter performance, the crystal input frequency may be doubled. The phase
attenuation. As can be seen from the block diagram in Figure 2, detector of the lower loop is designed to work with frequencies in the
similarly to the Frequency Synthesizer mode, only the upper 8kHz - 16kHz range. For improved phase noise performance, the
feedback loop is used. crystal input frequency may be doubled.

Alarm Conditions & Status Bits

The IDT8T49N205I monitors a number of conditions and reports their
status via both output pins and register bits. All alarms will behave as
indicated below in all modes of operation, but some of the conditions
monitored have no valid meaning in some operating modes. For
example, the status of CLK0BAD, CLK1BAD and CLK_ACTIVE are
not relevant in Frequency Synthesizer mode. The outputs will still be
active and it is left to the user to determine which to monitor and how
to respond to them based on the known operating mode.

CLK_ACTIVE - indicates which input clock reference is being used to

derive the output frequency.

LOCK_IND - This status is asserted on the pin & register bit when the
PLL is locked to the appropriate input reference for the chosen mode
of operation. The status bit will not assert until frequency lock has
been achieved, but will de-assert once lock is lost.
Figure 2. High Bandwidth Frequency Translator Mode
Block Diagram

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XTALBAD - indicates if valid edges are being received on the crystal The IDT8T49N205I will only switch input references on command
input. Detection is performed by comparing the input to the feedback from the user. The user must either change the CLK_SEL register bit
signal at the upper loop’s Phase / Frequency Detector (PFD). If three (if in Manual via Register) or CLK_SEL input pin (if in Manual via Pin).
edges are received on the feedback without an edge on the crystal
input, the XTALBAD alarm is asserted on the pin & register bit. Once Automatic Switching Mode
an edge is detected on the crystal input, the alarm is immediately When the AUTO_MAN[1:0] field is set to either of the automatic
deasserted. selection modes (Revertive or Non-Revertive), the IDT8T49N205I
determines which input reference it prefers / starts from by the state
CLK0BAD - indicates if valid edges are being received on the CLK0 of the CLK_SEL register bit only. The CLK_SEL input pin is not used
reference input. Detection is performed by comparing the input to the in either Automatic switching mode.
feedback signal at the appropriate Phase / Frequency Detector
(PFD). When operating in high-bandwidth mode, the feedback at the When starting from an unlocked condition, the device will lock to the
upper PFD is used. In low-bandwidth mode, the feedback at the lower input reference indicated by the CLK_SEL register bit. It will not pay
PFD is used. If three edges are received on the feedback without an attention to the non-selected input reference until a locked state has
edge on the divided down (÷P) CLK0 reference input, the CLK0BAD been achieved. This is necessary to prevent ‘hunting’ behavior during
alarm is asserted on the pin & register bit. Once an edge is detected the locking phase.
on the CLK0 reference input, the alarm is deasserted.
Once the IDT8T49N205I has achieved a stable lock, it will remain
CLK1BAD - indicates if valid edges are being received on the CLK1 locked to the preferred input reference as long as there is a valid clock
reference input. Behavior is as indicated for the CLK0BAD alarm, but on it. If at some point, that clock fails, then the device will
with the CLK1 input being monitored and the CLK1BAD output pin & automatically switch to the other input reference as long as there is a
register bits being affected. valid clock there. If there is not a valid clock on either input reference,
the IDT8T49N205I will go into holdover (Low Bandwidth Frequency
HOLDOVER - indicates that the device is not locked to a valid input Translator mode) or free-run (High Bandwidth Frequency Translator
reference clock. This can occur in Manual switchover mode if the mode) state. In either case, the HOLDOVER alarm will be raised.
selected reference input has gone bad, even if the other reference
input is still good. In automatic mode, this will only assert if both input The device will recover from holdover / free-run state once a valid
references are bad. clock is re-established on either reference input. If clocks are valid on
both input references, the device will choose the reference indicated
Input Reference Selection and Switching by the CLK_SEL register bit.

When operating in Frequency Synthesizer mode, the CLK0 and If running from the non-preferred input reference and a valid clock
CLK1 inputs are not used and the contents of this section do not returns, there is a difference in behavior between Revertive and
apply. Except as noted below, when operating in either High or Low Non-revertive modes. In Revertive mode, the device will switch back
Bandwidth Frequency Translator mode, the contents of this section to the reference indicated by the CLK_SEL register bit even if there
apply equally when in either of those modes. is still a valid clock on the non-preferred reference input. In
Non-revertive mode, the IDT8T49N205I will not switch back as long
Both input references CLK0 and CLK1 must be the same nominal as the non-preferred input reference still has a valid clock on it.
frequency. These may be driven by any type of clock source,
including crystal oscillator modules. A difference in frequency may Switchover Behavior of the PLL
cause the PLL to lose lock when switching between input references. Even though the two input references have the same nominal
Please contact IDT for the exact limits for your situation. frequency, there may be minor differences in frequency and
potentially large differences in phase between them. The
The global control bits AUTO_MAN[1:0] dictate the order of priority IDT8T49N205I has two options: Phase Build-Out or Phase-Slope
and switching mode to be used between the CLK0 and CLK1 inputs. Limiting to determine how it will adjust its output to the new input
reference when operating in Low-Bandwidth mode. Only
Manual Switching Mode Phase-Slope limiting is available in High-Bandwidth mode. The
When the AUTO_MAN[1:0] field is set to Manual via Pin, then the PBO_DISABLE bit is used to determine which method is used in
IDT8T49N205I will use the CLK_SEL input pin to determine which Low_bandwidth mode.
input to use as a reference. Similarly, if set to Manual via Register,
then the device will use the CLK_SEL register bit to determine the In Phase Slope Limiting operation, the IDT8T49N205I will adjust the
input reference. In either case, the PLL will lock to the selected output phase at a fixed maximum rate until the output phase and
reference if there is a valid clock present on that input. frequency are now aligned to the new input reference. Phase will
always be adjusted so that no unacceptably short clock periods are
If there is not a valid clock present on the selected input, the generated on the output of the IDT8T49N205I. Please contact IDT if
IDT8T49N205I will go into holdover (Low Bandwidth Frequency more information on the maximum phase slope adjustment rate is
Translator mode) or free-run (High Bandwidth Frequency Translator needed.
mode) state. In either case, the HOLDOVER alarm will be raised.
This will occur even if there is a valid clock on the non-selected In Phase Build-Out operation, the device will absorb most of the
reference input. The device will recover from holdover / free-run state phase difference between the two inputs (or between the input and
once a valid clock is re-established on the selected reference input. current VCO setting if recovering from holdover). Please refer to
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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Table 6 for exact limits. Any phase difference that is not absorbed will Output Configuration
be reflected on the output at the same maximum rate as in Phase
Slope Limiting operation. The two outputs of the IDT8T49N205I both provide the same clock
frequency. Both must operate from the same output voltage level of
Holdover / Free-run Behavior 3.3V or 2.5V, although this output voltage may be less than or equal
When both input references have failed (Automatic mode) or the to the core voltage (3.3V or 2.5V) the rest of the device is operating
selected input has failed (Manual mode), the IDT8T49N205I will from. The output voltage level used on the two outputs is supplied on
enter holdover (Low Bandwidth Frequency Translator mode) or the VCCO pin.
free-run (High Bandwidth Frequency Translator mode) state .
The two outputs are individually selectable as LVDS or LVPECL
If operating in Low Bandwidth Frequency Translation mode, the PLL output types via the Q0_TYPE and Q1_TYPE register bits. These
will continue to reference itself to the local oscillator and will hold its two selection bits are provided in each configuration to allow different
output phase and frequency in relation to that source. Output stability output type settings under each configuration.
is determined by the stability of the local oscillator in this case.
The two outputs can be enabled individually also via both register
However, if operating in High Bandwidth Frequency Translation control bits and input pins. When both the OEn register bit and OEn
mode, the PLL no longer has any frequency reference to use and the pin are enabled, then the appropriate output is enabled. The OEn
VCO will return to the center of its tuning range. Similarly, if operating register bits default to enabled so that by default the outputs can be
in Low-Bandwidth mode and no initial frequency lock has been directly controlled by the input pins. Similarly, the input pins are
achieved, the VCO will stay at or return to the center of its tuning provisioned with weak pull-ups so that if they are left unconnected,
range. the output state can be directly controlled by the register bits. When
the differential output is in the disabled state, it will show a high
If the device is programmed to perform Manual switching, once the impedance condition.
selected input reference recovers, the IDT8T49N205I will switch back
to that input reference. If programmed for either Automatic mode, the
device will switch back to whichever input reference has a valid clock
first.

The switchover that results from returning from holdover or free-run

is handled in the same way as a switch between two valid input
references as described in the previous section.

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Serial Interface Configuration Description

The IDT8T49N205I has an I2C-compatible configuration interface to and write block transfers can be stopped after any complete byte
access any of the internal registers (Table 4D) for frequency and PLL transfer. It is recommended to terminate I2C the read or write transfer
parameter programming. The IDT8T49N205I acts as a slave device after accessing byte #23.
on the I2C bus and has the address 0b11011xx, where xx is set by
For full electrical I2C compliance, it is recommended to use external
the values on the S_A0 & S_A1 pins (see Table 4A for details). The
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
interface accepts byte-oriented block write and block read
have a size of 50k typical.
operations. An address byte (P) specifies the register address (Table
4D) as the byte position of the first register to write or read. Data Note: if a different device slave address is desired, please contact
bytes (registers) are accessed in sequential order from the lowest to IDT.
the highest byte (most significant bit first, see table 4B, 4C). Read

Table 4A. I2C Device Slave Address

1 1 0 1 1 S_A1 S_A0 R/W

Table 4B. Block Write Operation

Bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ...
Slave Address Data Byte Data Byte Data Byte
Description
START Address W (0) ACK Byte (P) ACK (P) ACK (P+1) ACK ... ACK STOP

Length (bits) 1 7 1 1 8 1 8 1 8 1 8 1 1

Table 4C. Block Read Operation

Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ...
A A A A A A
Slave W Address Repeate Slave R Data Data Byte Data Byte
Description START C C C C C C STOP
Address (0) Byte (P) d START Address (1) Byte (P) (P+1) ...
K K K K K K

Length (bits) 1 7 1 1 8 1 1 7 1 1 8 1 8 1 8 1 1

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Register Descriptions
Please consult IDT for configuration software and/or programming guides to assist in selection of optimal register settings for the desired
configurations.
Table 4D. I2C Register Map
Binary Register Bit
Register
Reg Address D7 D6 D5 D4 D3 D2 D1 D0

0 00000 MFRAC0[17] MFRAC0[16] MFRAC0[15] MFRAC0[14] MFRAC0[13] MFRAC0[12] MFRAC0[11] MFRAC0[10]

1 00001 MFRAC1[17] MFRAC1[16] MFRAC1[15] MFRAC1[14] MFRAC1[13] MFRAC1[12] MFRAC1[11] MFRAC1[10]

2 00010 MFRAC0[9] MFRAC0[8] MFRAC0[7] MFRAC0[6] MFRAC0[5] MFRAC0[4] MFRAC0[3] MFRAC0[2]

3 00011 MFRAC1[9] MFRAC1[8] MFRAC1[7] MFRAC1[6] MFRAC1[5] MFRAC1[4] MFRAC1[3] MFRAC1[2]

4 00100 MFRAC0[1] MFRAC0[0] MINT0[7] MINT0[6] MINT0[5] MINT0[4] MINT0[3] MINT0[2]

5 00101 MFRAC1[1] MFRAC1[0] MINT1[7] MINT1[6] MINT1[5] MINT1[4] MINT1[3] MINT1[2]

6 00110 MINT0[1] MINT0[0] P0[16] P0[15] P0[14] P0[13] P0[12] P0[11]

7 00111 MINT1[1] MINT1[0] P1[16] P1[15] P1[14] P1[13] P1[12] P1[11]

8 01000 P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3]

9 01001 P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3]

10 01010 P0[2] P0[1] P0[0] M1_0[16] M1_0[15] M1_0[14] M1_0[13] M1_0[12]

11 01011 P1[2] P1[1] P1[0] M1_1[16] M1_1[15] M1_1[14] M1_1[13] M1_1[12]

12 01100 M1_0[11] M1_0[10] M1_0[9] M1_0[8] M1_0[7] M1_0[6] M1_0[5] M1_0[4]

13 01101 M1_1[11] M1_1[10] M1_1[9] M1_1[8] M1_1[7] M1_1[6] M1_1[5] M1_1[4]

14 01110 M1_0[3] M1_0[2] M1_0[1] M1_0[0] N0[10] N0[9] N0[8] N0[7]

15 01111 M1_1[3] M1_1[2] M1_1[1] M1_1[0] N1[10] N1[9] N1[8] N1[7]

16 10000 N0[6] N0[5] N0[4] N0[3] N0[2] N0[1] N0[0] BW0[6]

17 10001 N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] BW1[6]

18 10010 BW0[5] BW0[4] BW0[3] BW0[2] BW0[1] BW0[0] Q1_TYPE0 Q0_TYPE0

19 10011 BW1[5] BW1[4] BW1[3] BW1[2] BW1[1] BW1[0] Q1_TYPE1 Q0_TYPE1

20 10100 MODE_SEL[1] MODE_SEL[0] CONFIG CFG_PIN_REG OE1 OE0 Rsvd Rsvd

21 10101 CLK_SEL AUTO_MAN[1] AUTO_MAN[0] 0 ADC_RATE[1] ADC_RATE[0] LCK_WIN[1] LCK_WIN[0]

22 10110 1 0 1 0 DBL_XTAL 0 PBO_DISABLE 1

23 10111 CLK_ACTIVE HOLDOVER CLK1BAD CLK0BAD XTAL_BAD LOCK_IND Rsvd Rsvd

Register Bit Color Key

Configuration 0 Specific Bits
Configuration 1 Specific Bits
Global Control & Status Bits

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The register bits described in Table 4E are duplicated, with one set configuration they apply to is enabled. Replace the lowercase n in the
applying for Configuration 0 and the other for Configuration 1. The bit field description with 0 or 1 to find the field’s location in the bitmap
functions of the bits are identical, but only apply when the in Table 4D.

Table 4E. Configuration-Specific Control Bits

Register Bits Function
Determines the output type for output pair Q0, nQ0 for Configuration n.
Q0_TYPEn 0 = LVPECL
1 = LVDS
Determines the output type for output pair Q1, nQ1 for Configuration n.
Q1_TYPEn 0 = LVPECL
1 = LVDS
Pn[16:0] Reference Pre-Divider for Configuration n.
M1_n[16:0] Integer Feedback Divider in Lower Feedback Loop for Configuration n.
M_INTn[7:0] Feedback Divider, Integer Value in Upper Feedback Loop for Configuration n.
M_FRACn[17:0] Feedback Divider, Fractional Value in Upper Feedback Loop for Configuration n.
Nn[10:0] Output Divider for Configuration n.
Internal Operation Settings for Configuration n.
Please use IDT IDT8T49N205I Configuration Software to determine the correct settings for these bits for the
BWn[6:0]
specific configuration. Alternatively, please consult with IDT directly for further information on the functions of these
bits.The function of these bits are explained in Tables 4J and 4K.

Table 4F. Global Control Bits

Register Bits Function
PLL Mode Select
00 = Low Bandwidth Frequency Translator
MODE_SEL[1:0] 01 = Frequency Synthesizer
10 = High Bandwidth Frequency Translator
11 = High Bandwidth Frequency Translator
Configuration Control. Selects whether the configuration selection function is under pin or register control.
CFG_PIN_REG 0 = Pin Control
1 = Register Control
Configuration Selection. Selects whether the device uses the register configuration set 0 or 1. This bit only has an
CONFIG
effect when the CONFIG_PIN_REG bit is set to 1 to enable register control.
Output Enable Control for Output 0. Both this register bit and the corresponding Output Enable pin OE0 must be
asserted to enable the Q0, nQ0 output.
OE0
0 = Output Q0, nQ0 disabled
1 = Output Q0, nQ0 under control of the OE0 pin
Output Enable Control for Output 1. Both this register bit and the corresponding Output Enable pin OE1 must be
asserted to enable the Q1, nQ1 output.
OE1
0 = Output Q1, nQ1 disabled
1 = Output Q1, nQ1 under control of the OE1 pin
Rsvd Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed
Selects how input clock selection is performed.
00 = Manual Selection via pin only
AUTO_MAN[1:0] 01 = Automatic, non-revertive
10 = Automatic, revertive
11 = Manual Selection via register only

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In manual clock selection via register mode, this bit will command which input clock is selected. In the automatic
modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect.
CLK_SEL
0 = CLK0
1 = CLK1
Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the crystal input frequency.
00 = Crystal Frequency / 16
ADC_RATE[1:0] 01 = Crystal Frequency / 8
10 = Crystal Frequency / 4 (recommended)
11 = Crystal Frequency / 2
Sets the width of the window in which a new reference edge must fall relative to the feedback edge:
00 = 125nsec (recommended),
LCK_WIN[1:0] 01 = 500nsec,
10 = 2sec,
11 = 8sec
Disables the use of Phase Build-Out when switching between inputs:
PBO_DISABLE 0 = PBO Enabled
1 = PBO Disabled and only Phase-Slope Limiting used
DBL_XTAL When set, this bit will double the frequency of the crystal input before applying it to the Phase-Frequency Detector.

Table 4G. Global Status Bits

Register Bits Function
Status Bit for input clock 0. This function is mirrored in the CLK0BAD pin.
CLK0BAD 0 = input 0 good
1 = input 0 bad. Self clears when input clock returns to good status
Status Bit for input clock 1. This function is mirrored in the CLK1BAD pin.
CLK1BAD 0 = input 0 good
1 = input 0 bad. Self clears when input clock returns to good status
Status Bit. This function is mirrored on the XTALBAD pin.
XTALBAD 0= crystal input good
1 = crystal input bad. Self-clears when the XTAL clock returns to good status
Status bit. This function is mirrored on the LOCK_IND pin.
LOCK_IND 0 = PLL unlocked
1 = PLL locked
Status Bit. This function is mirrored on the HOLDOVER pin.
HOLDOVER 0 = Input to phase detector is within specifications and device is tracking to it
1 = Phase detector input not within specifications and DCXO is frozen at last value
Status Bit. Indicates which input clock is active. Automatically updates during fail-over switching. Status also
CLK_ACTIVE
indicated on CLK_ACTIVE pin.

Table 4H. BW[6:0] Bits

Mode BW[6] BW[5] BW[4] BW[3] BW[2] BW[1] BW[0]
Synthesizer Mode PLL2_LF[1] PLL2_LF[0] DSM_ORD DSM_EN PLL2_CP[1] PLL2_CP[0] PLL2_LOW_Icp
High-Bandwidth Mode PLL2_LF[1] PLL2_LF[0] DSM_ORD DSM_EN PLL2_CP[1] PLL2_CP[0] PLL2_LOW_Icp
Low-Bandwidth Mode ADC_GAIN[3] ADC_GAIN[2] ADC_GAIN[1] ADC_GAIN[0] PLL1_CP[1] PLL1_CP[0] PLL2_LOW_Icp

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Table 4I. Functions of Fields in BW[6:0]

Register Bits Function
Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes.
PLL2_LF[1:0]
Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4L for settings.
DSM_ORD Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation
Enables Delta-Sigma Modulator
DSM_EN 0 = Disabled - feedback in integer mode only
1 = Enabled - feedback in fractional mode
Upper loop PLL charge pump current settings:
00 = 173A (defaults to this setting in Low Bandwidth Mode)
PLL2_CP[1:0] 01 = 346A
10 = 692A
11 = reserved
Reduces Charge Pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register
PLL2_LOW_Icp
settings or high VCO operating frequency (>2.4GHz).
ADC_GAIN[3:0] Gain setting for ADC in Low Bandwidth Mode.
Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode):
00 = 800A
PLL1_CP[1:0] 01 = 400A
10 = 200A
11 = 100A

Table 4J. Upper Loop (PLL2) Bandwidth Settings

Desired
Bandwidth PLL2_CP PLL2_LOW_ICP PLL2_LF
Frequency Synthesizer Mode
200kHz 00 1 00
400kHz 01 1 01
800kHz 10 1 10
2MHz 10 1 11
High Bandwidth Frequency Translator Mode
200kHz 00 1 00
400kHz 01 1 01
800kHz 10 1 10
4MHz 10 0 11

NOTE: To achieve 4MHz bandwidth, reference to the phase detector should be 80MHz.

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Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item Rating
Supply Voltage, VCC 3.6V
Inputs, VI
XTAL_IN 0V to 2V
Other Inputs -0.5V to VCC + 0.5V
Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current 50mA
Surge Current 100mA
Outputs, IO (LVDS)
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, JA 32.4C/W (0 mps)
Storage Temperature, TSTG -65C to 150C

DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.30 3.3 VCC V
VCCO Output Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 320 mA
ICCA Analog Supply Current 30 mA

Table 5B. LVPECL Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.30 3.3 VCC V
VCCO Output Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 320 mA
ICCA Analog Supply Current 30 mA

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Table 5C. LVPECL Power Supply DC Characteristics, VCC = VCCO = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 2.375 2.5 2.625 V
VCCA Analog Supply Voltage VCC – 0.26 2.5 VCC V
VCCO Output Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 304 mA
ICCA Analog Supply Current 26 mA

Table 5D. LVDS Power Supply DC Characteristics, VCC = VCCO = 3.3V±5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.30 3.3 VCC V
VCCO Output Supply Voltage 3.135 3.3 3.465 V
ICC Power Supply Current 273 mA
ICCA Analog Supply Current 30 mA
ICCO Output Supply Current 42 mA

Table 5E. LVDS Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.30 3.3 VCC V
VCCO Output Supply Voltage 2.375 2.5 2.625 V
ICC Power Supply Current 273 mA
ICCA Analog Supply Current 30 mA
ICCO Output Supply Current 42 mA

Table 5F. LVDS Power Supply DC Characteristics, VCC = VCCO = 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 2.375 2.5 2.625 V
VCCA Analog Supply Voltage VCC – 0.26 2.5 VCC V
VCCO Output Supply Voltage 2.375 2.5 2.625 V
ICC Power Supply Current 263 mA
ICCA Analog Supply Current 26 mA
ICCO Output Supply Current 42 mA

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Table 5G. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC = 3.3V 2.2 VCC + 0.3 V
VIH Input High Voltage
VCC = 2.5V 1.7 VCC + 0.3 V
VCC = 3.3V -0.3 0.8 V
VIL Input Low Voltage
VCC = 2.5V -0.3 0.7 V
CLK_SEL, CONFIG,
Input VCC = VIN = 3.465V or 2.625V 150 µA
PLL_BYPASS, S_A[1:0]
IIH High
Current OE0, OE1,
VCC = VIN = 3.465V or 2.625V 5 µA
SCLK, SDATA
CLK_SEL, CONFIG, VCC = 3.465V or 2.625V,
Input -5 µA
PLL_BYPASS, S_A[1:0] VIN = 0V
IIL Low
Current OE0, OE1, VCC = 3.465V or 2.625V,
-150 µA
SCLK, SDATA VIN = 0V
HOLDOVER, SDATA VCC = 3.465V, IOH = -8mA 2.6 V
Output
CLK_ACTIVE,
VOH High
LOCK_IND, XTALBAD, VCC = 2.625V, IOH = -8mA 1.8 V
Voltage
CLK0BAD, CLK1BAD
HOLDOVER, SDATA
Output
CLK_ACTIVE, VCC = 3.465V or 2.625V,
VOL Low 0.5 V
LOCK_IND, XTALBAD, IOL = 8mA
Voltage
CLK0BAD, CLK1BAD

Table 5H. Differential DC Characteristics, VCC = VCCO = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Input
CLK0, nCLK0, CLK1,
IIH High VCC = VIN = 3.465V or 2.625V 150 µA
nCLK1
Current
VCC = 3.465V or 2.625V, VIN =
Input CLK0, CLK1 -5 µA
0V
IIL Low
Current VCC = 3.465V or 2.625V, VIN =
nCLK0, nCLK1 -150 µA
0V
VPP Peak-to-Peak Voltage 0.15 1.3 V
Common Mode Input Voltage;
VCMR VEE + 0.5 VCC – 1.0 V
NOTE 1

NOTE 1: Common mode input voltage is defined as the crosspoint voltage.

Table 5I. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO – 1.1 VCCO – 0.7 V
VOL Output Low Voltage NOTE 1 VCCO – 2.0 VCCO – 1.5 V
VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

NOTE 1: Outputs terminated with 50 to VCCO – 2V.

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Table 5J. LVPECL DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO – 1.1 VCCO – 0.7 V
VOL Output Low Voltage NOTE 1 VCCO – 2.0 VCCO – 1.5 V
VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

NOTE 1: Outputs terminated with 50 to VCCO – 2V.

Table 5K. LVDS DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.125 1.375 V
VOS VOS Magnitude Change 50 mV

Table 5L. LVDS DC Characteristics, VCC = 3.3V ± 5% or 2.5V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.125 1.375 V
VOS VOS Magnitude Change 50 mV

Table 6. Input Frequency Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
XTAL_IN, XTAL_OUT
16 40 MHz
NOTE 1
Input High Bandwidth Mode 16 710 MHz
fIN CLK0, nCLK0,
Frequency
CLK1, nCLK1 Low Bandwidth Mode 0.008 710 MHz
SCLK 5 MHz

NOTE 1: For the input crystal and CLKx, nCLKx frequency range, the M value must be set for the VCO to operate within the 1995MHz to
2600MHz range.

Table 7. Crystal Characteristics

Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 16 40 MHz
Equivalent Series Resistance (ESR) 100 
Shunt Capacitance 7 pF

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AC Electrical Characteristics
Table 8. AC Characteristics, VCC = VCCO = 3.3V±5% or 2.5V±5%, or
VCC = 3.3V±5%, VCCO = 2.5V±5% (LVPECL Only), VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 0.98 1300 MHz
fVCO VCO Frequency 1995 2600 MHz
Synth Mode (Integer FB),
fOUT = 400MHz, 40MHz XTAL, 245 385 fs
Integration Range: 12kHz – 40MHz
Synth Mode (FracN FB),
fOUT = 698.81MHz, 40MHz XTAL, 355 605 fs
Integration Range: 12kHz – 20MHz
LVDS output (NOTE 1), HBW Mode,
fIN = 133.33MHz, fOUT = 400MHz, 320 460 fs
RMS Phase Jitter;
tjit(Ø) Integration Range: 12kHz – 20MHz
Integer Divide Ratio
LVPECL output,
LBW Mode (FracN), 40MHz XTAL,
379 610 fs
fIN = 10MHz, fOUT = 155.52MHz,
Integration Range: 12kHz – 20MHz
LVPECL output,
LBW Mode (FracN), 40MHz XTAL,
396 650 fs
fIN = 25MHz, fOUT = 161.1328125MHz,
Integration Range: 12kHz – 20MHz

Cycle-to-Cycle Jitter; Frequency Synthesizer Mode 40 ps

tjit(cc)
NOTE 2, 5 Frequency Translator Mode 40 ps
tsk(o) Output Skew; NOTE 2, 3, 5 35 ps
LVPECL
2.0 6.5 ps
RMS Period Outputs
tjit(per)
Jitter; NOTE 5 LVDS
2.0 4.5 ps
Outputs
fIN0 = 8kHz, fIN1 = 8kHz with 40usec
tERR Initial Phase Error 4.5 ns
phase offset, Low-Bandwidth mode
High-Bandwidth mode, 800kHz loop BW;
tPWL Switchover Phase Slope 1.5 ms / s
fOUT = 100MHz, 4µS phase error
LVPECL
Output 20% to 80% 95 485 ps
Outputs
tR / tF Rise/Fall Time;
NOTE 5 LVDS
20% to 80% 128 498 ps
Outputs
LVPECL
Output fOUT < 600MHz 47 53 %
Outputs
odc Duty Cycle;
NOTE 5 LVDS
fOUT  600MHz 45 55 %
Outputs
from falling edge of the 8th SCLK for a
Output Re-configuration 200 ns
tSET register change
Settling Time NOTE 4
from edge on CONFIG pin 10 ns

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

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has been reached under these conditions.

NOTE 1: Measured using a Rohde & Schwarz SMA100 Signal Generator, 9kHz to 6GHz as the input source.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: This settling time does not include PLL re-calibration and locking if required. Since those times are highly dependent on the specific
configuration, please contact IDT for times if PLL re-configuration is performed as part of the configuration change.
NOTE 5: Measurements are collected with the following output frequencies: 19.44MHz, 38.88MHz, 66.6667Mhz, 125MHz, 156.25MHz,
161.1328125MHz, 311.04MHz, 400MHz, 480MHz, 622.08MHz 1000MHz, 1200MHz, 1300MHz.

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Typical Phase Noise at 400MHz (3.3V)

Noise Power (dBc / Hz)

Offset Frequency (Hz)

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Parameter Measurement Information

2V 2V

2V 2V

VCC, VCC,
VCCO VCCO
VCCA VCCA

-1.3V+0.165V -0.5V±0.125V

3.3 Core/3.3V LVPECL Output Load Test Circuit 2.5 Core/2.5V LVPECL Output Load Test Circuit

2.8V±0.04V
2V
2.8V±0.04V

VCC
Qx
SCOPE VCC,
VCCO
VCCO VCCA
VCCA

nQx
VEE

-0.5V±0.125V

3.3 Core/2.5V LVPECL Output Load Test Circuit 3.3 Core/3.3V LVDS Output Load Test Circuit

3.3V±5%

2.5V±5%

SCOPE VCC SCOPE

VCC, Qx Qx
VCCA
2.5V±5%
POWER SUPPLY VCCO V VCCO + + –
CCA
+ Float GND – POWER
SUPPLY
nQx nQx Float GND

2.5 Core/2.5V LVDS Output Load Test Circuit 3.3 Core/2.5V LVDS Output Load Test Circuit

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Parameter Measurement Information, continued

VCC
nQx

nCLKx Qx

CLKx nQy

Qy
VEE

Differential Input Levels Output Skew

VOH

nQx VREF

Qx VOL

tcycle n tcycle n+1 tPER(n) n = 1...10000 cycles

tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles

10000
tjit(per) = n=1 (tPER(n) – tPER mean)2 / (n – 1)

Cycle-to-Cycle Jitter RMS Period Jitter

nQx nQx
80% 80%
VOD
20% 20%
Qx Qx
tR tF

LVDS Output Rise/Fall Time LVPECL Output Rise/Fall Time

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Parameter Measurement Information, continued

Offset Voltage Setup RMS Phase Jitter

nQx

Qx

Differential Output Duty Cycle/Output Pulse Width/Period Differential Output Voltage Setup

IDT8T49N205ANLGI REVISION B JULY 9, 2013 23 ©2013 Integrated Device Technology, Inc.

IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Applications Information

Recommendations for Unused Input and Output Pins

Inputs: Outputs:
CLKx/nCLKx Inputs LVPECL Outputs
For applications not requiring the use of either differential input, both All unused LVPECL output pairs can be left floating. We recommend
CLKx and nCLKx can be left floating. Though not required, but for that there is no trace attached. Both sides of the differential output
additional protection, a 1k resistor can be tied from CLKx to ground. pair should either be left floating or terminated.
It is recommended that CLKx, nCLKx be left unconnected in
frequency synthesizer mode. LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
LVCMOS Control Pins with 100 across. If they are left floating there should be no trace
All control pins have internal pullups or pulldowns; additional attached.
resistance is not required but can be added for additional protection.
A 1k resistor can be used. LVCMOS Outputs
All unused LVCMOS outputs can be left floating. There should be no
trace attached.

Recommended Values for Low-Bandwidth Mode Loop Filter

External loop filter components are not needed in Frequency
Synthesizer or High-Bandwidth modes. In Low-Bandwidth mode, the
loop filter structure and components shown in Figure 11 are
recommended. Please consult IDT if other values are needed.

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Wiring the Differential Input to Accept Single-Ended Levels

Figure 4 shows how a differential input can be wired to accept single line impedance. For most 50 applications, R3 and R4 can be 100.
ended levels. The reference voltage V1 = VCC/2 is generated by the The values of the resistors can be increased to reduce the loading for
bias resistors R1 and R2. The bypass capacitor (C1) is used to help slower and weaker LVCMOS driver. When using single-ended
filter noise on the DC bias. This bias circuit should be located as close signaling, the noise rejection benefits of differential signaling are
to the input pin as possible. The ratio of R1 and R2 might need to be reduced. Even though the differential input can handle full rail
adjusted to position the V1 in the center of the input voltage swing. LVCMOS signaling, it is recommended that the amplitude be
For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and reduced. The datasheet specifies a lower differential amplitude,
R2 value should be adjusted to set V1 at 1.25V. The values below are however this only applies to differential signals. For single-ended
for when both the single ended swing and VCC are at the same applications, the swing can be larger, however VIL cannot be less
voltage. This configuration requires that the sum of the output than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
impedance of the driver (Ro) and the series resistance (Rs) equals of the recommended components might not be used, the pads
the transmission line impedance. In addition, matched termination at should be placed in the layout. They can be utilized for debugging
the input will attenuate the signal in half. This can be done in one of purposes. The datasheet specifications are characterized and
two ways. First, R3 and R4 in parallel should equal the transmission guaranteed by using a differential signal.

VCC VCC VCC

VCC
R3
100 R1
1K

Ro RS Zo = 50 Ohm
+

Receiv er
Driver V1
R4 -
100
Ro + Rs = Zo C1
R2
1K
0.1uF

Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by one can be done in one of two ways. First, R1 and R2 in parallel should
side of a differential driver through an AC coupling capacitor. The equal the transmission line impedance. For most 50 applications,
XTAL_OUT pin can be left floating. The amplitude of the input signal R1 and R2 can be 100. This can also be accomplished by removing
should be between 500mV and 1.8V and the slew rate should not be R1 and changing R2 to 50. The values of the resistors can be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be increased to reduce the loading for a slower and weaker LVCMOS
reduced from full swing to at least half the swing in order to prevent driver. Figure 5B shows an example of the interface diagram for an
signal interference with the power rail and to reduce internal noise. LVPECL driver. This is a standard LVPECL termination with one side
Figure 5A shows an example of the interface diagram for a high of the driver feeding the XTAL_IN input. It is recommended that all
speed 3.3V LVCMOS driver. This configuration requires that the sum components in the schematics be placed in the layout. Though some
of the output impedance of the driver (Ro) and the series resistance components might not be used, they can be utilized for debugging
(Rs) equals the transmission line impedance. In addition, matched purposes. The datasheet specifications are characterized and
termination at the crystal input will attenuate the signal in half. This guaranteed by using a quartz crystal as the input.

VCC
XTAL_OUT

R1
100
C1
Ro Rs Zo = 50 ohms
XTAL_IN

R2 .1uf
100
Zo = Ro + Rs
LVCMOS Driver

Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface

XTAL_OUT

C2
Zo = 50 ohms
XTAL_IN

Zo = 50 ohms .1uf

LVPECL Driver R1 R2
50 50

R3
50

Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other with the vendor of the driver component to confirm the driver
differential signals. Both VSWING and VOH must meet the VPP and termination requirements. For example, in Figure 8A, the input
VCMR input requirements. Figures 6A to 6E show interface examples termination applies for IDT open emitter LVHSTL drivers. If you are
for the CLK/nCLK input driven by the most common driver types. The using an LVHSTL driver from another vendor, use their termination
input interfaces suggested here are examples only. Please consult recommendation.

3.3V
3.3V 3.3V
1.8V
Zo = 50Ω
Zo = 50Ω CLK
CLK
Zo = 50Ω
Zo = 50Ω nCLK
nCLK Differential
LVPECL
Differential Input
LVHSTL R1 R2
Input 50Ω 50Ω
R1 R2
IDT 50Ω 50Ω
LVHSTL Driver
R2
50Ω

Figure 6A. CLK/nCLK Input Driven by an Figure 6B. CLK/nCLK Input Driven by a
IDT Open Emitter LVHSTL Driver 3.3V LVPECL Driver

3.3V
3.3V
3.3V 3.3V
3.3V
Zo = 50Ω

CLK
CLK
R1
100Ω
nCLK
nCLK
LVPECL Differential Zo = 50Ω
Input Receiver
LVDS

Figure 6C. CLK/nCLK Input Driven by a Figure 6D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V LVPECL Driver

3.3V 3.3V

*R3
CLK

nCLK
*R4 Differential
HCSL Input

Figure 6E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

LVDS Driver Termination

For a general LVDS interface, the recommended value for the standard termination schematic as shown in Figure 7A can be used
termination impedance (ZT) is between 90 and 132. The actual with either type of output structure. Figure 7B, which can also be
value should be selected to match the differential impedance (Z0) of used with both output types, is an optional termination with center tap
your transmission line. A typical point-to-point LVDS design uses a capacitance to help filter common mode noise. The capacitor value
100 parallel resistor at the receiver and a 100 differential should be approximately 50pF. If using a non-standard termination, it
transmission-line environment. In order to avoid any is recommended to contact IDT and confirm if the output structure is
transmission-line reflection issues, the components should be current source or voltage source type. In addition, since these
surface mounted and must be placed as close to the receiver as outputs are LVDS compatible, the input receiver’s amplitude and
possible. IDT offers a full line of LVDS compliant devices with two common-mode input range should be verified for compatibility with
types of output structures: current source and voltage source. The the output.

LVDS ZO  ZT LVDS
Driver ZT Receiver

Figure 7A. Standard Termination

ZT
LVDS ZO  ZT 2 LVDS
Driver C ZT Receiver
2
Figure 7B. Optional Termination

LVDS Termination

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for transmission lines. Matched impedance techniques should be used
LVPECL outputs. The two different layouts mentioned are to maximize operating frequency and minimize signal distortion.
recommended only as guidelines. Figures 8A and 8B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
The differential outputs are low impedance follower outputs that exist and it would be recommended that the board designers
generate ECL/LVPECL compatible outputs. Therefore, terminating simulate to guarantee compatibility across all printed circuit and clock
resistors (DC current path to ground) or current sources must be component process variations.
used for functionality. These outputs are designed to drive 50

3.3V
R3 R4
125 125
3.3V
3.3V
Zo = 50
+

_
LVPECL Input
Zo = 50
R1 R2
84 84

Figure 8A. 3.3V LVPECL Output Termination Figure 8B. 3.3V LVPECL Output Termination

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Termination for 2.5V LVPECL Outputs

Figure 10A and Figure 9B show examples of termination for 2.5V level. The R3 in Figure 9B can be eliminated and the termination is
LVPECL driver. These terminations are equivalent to terminating 50 shown in Figure 9C.
to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground

2.5V
2.5V VCCO = 2.5V
2.5V
VCCO = 2.5V
R1 R3 50
250 250
+
50
+
50
–
50
– 2.5V LVPECL Driver
R1 R2
2.5V LVPECL Driver 50 50
R2 R4
62.5 62.5

R3
18

Figure 9A. 2.5V LVPECL Driver Termination Example Figure 9B. 2.5V LVPECL Driver Termination Example

2.5V
VCCO = 2.5V

50
+

50
–

2.5V LVPECL Driver

R1 R2
50 50

Figure 9C. 2.5V LVPECL Driver Termination Example

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and and dependent upon the package power dissipation as well as
the electrical performance, a land pattern must be incorporated on electrical conductivity requirements. Thus, thermal and electrical
the Printed Circuit Board (PCB) within the footprint of the package analysis and/or testing are recommended to determine the minimum
corresponding to the exposed metal pad or exposed heat slug on the number needed. Maximum thermal and electrical performance is
package, as shown in Figure 10. The solderable area on the PCB, as achieved when an array of vias is incorporated in the land pattern. It
defined by the solder mask, should be at least the same size/shape is recommended to use as many vias connected to ground as
as the exposed pad/slug area on the package to maximize the possible. It is also recommended that the via diameter should be 12
thermal/electrical performance. Sufficient clearance should be to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
designed on the PCB between the outer edges of the land pattern desirable to avoid any solder wicking inside the via during the
and the inner edges of pad pattern for the leads to avoid any shorts. soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
While the land pattern on the PCB provides a means of heat transfer to eliminate any solder voids between the exposed heat slug and the
and electrical grounding from the package to the board through a land pattern. Note: These recommendations are to be used as a
solder joint, thermal vias are necessary to effectively conduct from guideline only. For further information, please refer to the Application
the surface of the PCB to the ground plane(s). The land pattern must Note on the Surface Mount Assembly of Amkor’s Thermally/
be connected to ground through these vias. The vias act as “heat Electrically Enhance Lead frame Base Package, Amkor Technology.
pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER SOLDER
PIN EXPOSED HEAT SLUG PIN

PIN PAD GROUND PLANE LAND PATTERN PIN PAD

THERMAL VIA (GROUND PAD)

Figure 10. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

IDT8T49N205ANLGI REVISION B JULY 9, 2013 31 ©2013 Integrated Device Technology, Inc.

IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Schematic Layout
Figure 11 (next page), shows an example of the UFT (8T49N205) In order to achieve the best possible filtering, it is highly
application schematic. Input and output terminations shown are recommended that the 0.1µF capacitors on the device side of the
intended as examples only and may not represent the exact user ferrite beads be placed on the device side of the PCB as close to the
configuration. Refer to the pin description and functional tables in the power pins as possible. This is represented by the placement of
datasheet to ensure the logic control inputs are properly set. these capacitors in the schematic. If space is limited, the ferrite beads
and 10µf capacitors connected to 3.3V can be placed on the opposite
In this example, the device is operated at VCC=3.3V. For 2.5V option, side of the PCB. If space permits, place all filter components on the
please refer to the “Termination for 2.5V LVPECL Outputs” for output device side of the board.
termination recommendation. A 12pF parallel resonant Fox
FX325BS Series 16MHz to 40MHz crystal is used in this example. Power supply filter recommendations are a general guideline to be
Different crystal frequencies may be used. The C1 = C2 = 5pF are used for reducing external noise from coupling into the devices. The
recommended for frequency accuracy. If different crystal types are filter performance is designed for a wide range of noise frequencies.
used, please consult IDT for recommendations. For different board This low-pass filter starts to attenuate noise at approximately 10 kHz.
layout, the C1 and C2 may be slightly adjusted for optimizing If a specific frequency noise component is known, such as switching
frequency accuracy. It is recommended that the loop filter power supplies frequencies, it is recommended that component
components be laid out for the 3-pole option. This will also allow values be adjusted and if required, additional filtering be added.
either 2-pole or 3-pole filter to be used. The 3-pole filter can be used Additionally, good general design practices for power plane voltage
for additional spur reduction. If a 2-pole filter construction is used, the stability suggests adding bulk capacitance in the local area of all
LF0 and LF1 pins must be tied-together and to the filter. devices.

As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The UFT (8T49N205) provides
separate VCC, VCCA and VCCO power supplies to isolate any high
switching noise from coupling into the internal PLL.

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

O utpu t Te rmina tion Exa mple -

L VDS outp ut sh own (Not e 3)

Zo = Zo_D if f = 100-ohm
+
R1
VC C 100
-
C4 C5 C6 C7

0. 1uF 0. 1uF 0.1uF 0.1uF

3. 3V F B1
VC C O
m uR ata, BLM18BB221SN 1 VC C O
C 14 C 15
C13
0.1uF 10uF 0.1uF R 17 R4

125 125
3. 3V Zo = 50-ohm
FB2 R2 10 +
VC C
m uR ata, BLM18BB221SN 1 Zo = 50-ohm
C9 C 10 C 12 C 11
C8 -
0.1uF 10uF 0.1uF 0. 1uF 10uF R6 R7

84 84
U2
25

13
29

36
3
7
16MH z to 40MH z
1
2
p
F

C1 X1 Fox FX325BS VC C O 27
V CC
VC C
VC C
V CC

VC C A
5pF Q0 26
Q0
Outp ut T ermi nati on E xamp le -
28 OE0
1 OE0 (Note 1)
LVPE CL o utpu t sh own (Not e 3)
2 XTAL_IN 24
C2
5pF (Note 1) XTAL_OU T Q1 23
(Note 2)C LK_SEL 4 Q1 22 OE1 (Note 1)
CLK0 5 CLK_SEL OE1
6 CLK0 30 LOCK_ IND
9 CLK0 LOC K_IN D 31 CLK_ACTIVE
L VDS Input 10 CLK1 U FT C LK_A CTI VE 37 HO LDOVER
R5
T ermi natio n (Note 1) CLK1 H OLD OVER 38 CL KBAD
E xamp le - 100 (Note 2)P LL_BYP ASS 12 CLK0BAD 39 CL K1BAD
(Note 1)S _A0 18 PLL_BY PASS CLK1BAD 40 XTALBAD
( Note 3) S_A0 XTALBAD
nC LK0 (Note 1)S _A1 17
SCLK 15 S_A1 34 2- pole loop
SDA TA 14 SC LK LF1 3-pole loop filter LF1 filter - (opt ional)
V CC (Note 1)C ON FIG 16 SD ATA 33
V EE

CON FI G LF0
VEE
VEE

(Note 2) LF0
nc
nc

nc
nc

C3
R9 R 10 R3
35

20
11
8
21

19

32

0. 001uF
125 125 R11 220K
L VPEC L Inp ut R 12 Rs 1 470K
CLK1 4. 7K 4.7K Rs 470K Cp1
T ermi natio n C s1
E xamp le - nC LK1 Cp Cs 0. 001uF
( Note 3) V CC 1uF
0.001uF 1uF
R 14 R15

84 84

Logic In put Pin Exam ples

Notes
VC C Set Logic VC C Set Logic
Input to '1' Input to '0' Note 1: CE0, OE1, CLK_SEL, PLL_BYPASS, S_A0 and S_A1 are digital control input s. If
external pull-up/down needed, see "Logic Input Pin Examples" shown at left. Please note
RU 1 RU2 t hat OE0 and OE1 are internally pulled up so no external pull-ups are required to enable
1K No t Installed t hem.
To Logic To Logic
Input pins Input pins Note 2: CLK_SEL, PLL_BYPASS and CONFIG are internally pulled down. No external
compononents required to select default condition.
RD 1 RD 2
Not Installed 1K Note 3: Other configurations are supported. Please contact IDT for details.

Figure 11. IDT8T49N205I Application Schematic

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

LVPECL Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8T49N205I.
Equations and example calculations are also provided.

1. Power Dissipation.
The total power dissipation for the IDT8T49N205I is the sum of the core power plus the output power dissipated due to loading.
The following is the output power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to loading.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 320mA = 1108.8W
• Power (outputs)MAX = 33.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 33.2mW = 66.4mW
Total Power_MAX (3.465V, with all outputs switching) = 1108.8mW + 66.4mW = 1175.2mW

2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.4°C/W per Table 9 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.175W * 32.4°C/W = 123.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).

Table 9. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection

JA by Velocity
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 12.

VCCO

Q1

VOUT

RL
50Ω

VCCO - 2V

Figure 12. LVPECL Driver Circuit and Termination

To calculate output power dissipation due to loading, use the following equations which assume a 50 load, and a termination voltage of VCCO
– 2V.

• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.7V

(VCCO_MAX – VOH_MAX) = 0.7V
• For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.5V
(VCCO_MAX – VOL_MAX) = 1.5V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.7V)/50] * 0.7V = 18.2mW

Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.5V)/50] * 1.5V = 15mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

LVDS Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8T49N205I.
Equations and example calculations are also provided.

1. Power Dissipation.
The total power dissipation for the IDT8T49N205I is the sum of the core power plus the output power dissipation due to the load.
The following is the output power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (273mA + 30mA) = 1049.895mW

• Power (outputs)MAX = VCCO_MAX * ICCO_MAX = 3.465V * 42mA = 145.53mW
Total Power_MAX = 1049.895mW + 145.53mW = 1195.425mW

2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.4°C/W per Table 10 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.195W * 32.4°C/W = 123.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).

Table 10. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W

IDT8T49N205ANLGI REVISION B JULY 9, 2013 36 ©2013 Integrated Device Technology, Inc.

IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Reliability Information
Table 11. JA vs. Air Flow Table for a 40 Lead VFQFN
JA vs. Air Flow
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W

Transistor Count
The transistor count for IDT8T49N205I is: 53,727

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IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

40 Lead VFQFN Package Outline and Package Dimensions

IDT8T49N205ANLGI REVISION B JULY 9, 2013 38 ©2013 Integrated Device Technology, Inc.

IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

40 Lead VFQFN Package Outline and Package Dimensions, continued

40 Lead VFQFN, D2/E2 EPAD Dimensions: 4.65mm x 4.65mm

IDT8T49N205ANLGI REVISION B JULY 9, 2013 39 ©2013 Integrated Device Technology, Inc.

IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

Ordering Information
Table 12. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

8T49N205A-dddNLGI IDT8T49N205A-dddNLGI “Lead-Free” 40 Lead VFQFN Tray -40C to +85C
8T49N205A-dddNLGI8 IDT8T49N205A-dddNLGI “Lead-Free” 40 Lead VFQFN Tape & Reel -40C to +85C
NOTE: For the specific -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document.

IDT8T49N205ANLGI REVISION B JULY 9, 2013 40 ©2013 Integrated Device Technology, Inc.

IDT8T49N205I Data Sheet FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT

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