Si 5 3 3 8 - EVB

Si5330/34/35/38 E VALUATION B OA RD U SER ’ S G UIDE

Description EVB Features

The Si5338-EVB is used for evaluating the Si5330/34/  Fully powered from a single USB port.
35/38 family of any-frequency, any-output clock  Onboard 25 MHz XTAL allows standalone
generators and clock buffers. asynchronous operation on the Si5334/35/38.
 GUI programmable VDD supply allows device to
operate from 3.3, 2.5, or 1.8 V.
 GUI programmable VDDO supplies allow each of the
four outputs to have its own supply voltage
selectable from 3.3, 2.5, 1.8, or 1.5 V
 GUI-controlled voltage, current, and power
measurements of VDD and all four VDDO supplies.
 Voltage supply jumpers allow easy access for use of
external supplies or current measurements.
 Input signal jumpers allow external control of pin
functions such as output enable, phase inc/dec,
frequency inc/dec, and I2C_LSB.

Rev. 1.5 3/20 Copyright © 2020 by Silicon Labs Si5338-EVB

Si5338-EVB
1. Functional Block Diagram
A functional block diagram of the EVB is shown in Figure 1. The MCU performs the USB to I2C conversion,
controls the voltage regulators, monitors the INTR pin, and controls the four status LEDS. It also provides control of
the eight input pins when the INx_CTRL jumpers are populated. There are five programmable voltage regulators
(VDD, VDDO0, VDDO1, VDDO2, VDDO3), which supply power to the Si533x device. VDD and VDDO jumpers
allow the option of powering the device from external supplies, or as a convenient point for measuring current. I2C
jumpers allow disconnection of the Si533x device from the I2C bus to allow external control from another I2C
master.
For the Si5334, Si5335, and Si5338 devices, the EVB is shipped with an onboard 25 MHz XTAL to allow
stand-alone asynchronous operation. For Si5335 emulation, synchronization to an external reference is done via
IN1 and IN2. Removal of the XTAL and addition of two 0 ohm resistors is required. IN3, IN4, IN5, and IN6 are not
available as external clock inputs for Si5335.

To
I2C VReg To VReg
VReg
Bus I2C VReg
VReg
VDD Bus
XTAL Jumpers
VDDO
Jumpers
VDD
*
IN1 VDDO0
0
*
IN2 CLK0A
term * *
0 term

CLK0B

IN3
term * *
term
VDDO1
IN4
CLK1A
term * *
term

IN5 CLK1B

IN6
Si5338
VDDO2

IN7/SCL CLK2A
term * *
term

IN8/SDA CLK2B
I2C
Jumpers
VDDO3

CLK3A
I2C Bus

term * *
term

CLK3B
INTR

INx_CTRL
Jumpers

* indicates unpopulated components

Status
MCU
LEDs
USB
Connector
Reset
Switch

Figure 1. EVB Functional Block Diagram

2 Rev. 1.5
 Si5338-EVB
2. Quick Start
1. Install the ClockBuilder Pro software.
2. Connect a USB cable from the EVB to the PC where the software was installed.
3. Leave the jumpers as installed from the factory, and launch ClockBuilder Pro.

3. Jumpers
The Si5338-EVB is shipped with jumpers installed on the following positions:
VDD—Connects
the Si533x VDD pin to the VDD programmable voltage regulator.
VDDO0—Connects the Si533x VDDO0 pin to the VDDO0 programmable voltage regulator.
VDDO1—Connects the Si533x VDDO1 pin to the VDDO1 programmable voltage regulator.
VDDO2—Connects the Si533x VDDO2 pin to the VDDO2 programmable voltage regulator.
VDDO3—Connects the Si533x VDDO3 pin to the VDDO3 programmable voltage regulator.

SCL—Connects the Si533x SCL pin to the I2C bus from the MCU.
SDA—Connects the Si533x SDA pin to the I2C bus from the MCU.
The INx-CTRL jumpers are optional jumpers for enabling MCU control of the Si533x input pins. This feature may
be available in future software releases.
4. Status LEDS
There are four status LEDs on the Si5338-EVB:
RDY (Green)—Indicates that the EVB is operating normally. This LED should always be on.
I2C (Green)—Indicates when there is active I2C communication between the MCU and the Si533x device
or between the MCU and voltage regulators.
USB (Green)—Indicates when there is active communication between the PC and the MCU over the USB
bus.
INTR (Red)—The MCU has detected that the interrupt pin of the Si533x device is enabled. The most
probable cause for an interrupt is because the Si533x has lost its input signal or the PLL has lost lock. The
“Status” tab of the GUI will identify the event that caused the interrupt to occur.

Rev. 1.5 3
Si5338-EVB
5. Inputs
The Si5338-EVB has six SMA connectors (IN1-IN6) for receiving external signals. Two of the signals are
differential, and two are single-ended.
5.1. Differential Inputs (IN1/IN2, IN5/IN6)
The differential inputs only need a differential voltage swing of 300 mV to operate, which makes them compatible
with most differential signal types. See “AN408: Termination Options for Any-Frequency, Any-Output Clock
Generators and Clock Buffers—Si5338, Si5334, Si5330”, or Si5335 data sheet if applicable, for details on
interfacing with compatible signal types. It is also possible to lock the Si5334/35/38 to an external signal generator
using one side of the differential input and grounding its complementary side. Take care not to exceed the max
differential voltage of 1.2 V on these inputs. The board is shipped with a 25 MHz XTAL connected to IN1/IN2. The
XTAL removal and resistor changes are required for Si5335 evaluation with an input clock since only IN1 and IN2
are available for input clocking with Si5335. Note that regardless of device, any external input to IN1 & IN2 must be
limited to 1.2 V peak-to-peak (see Figure 2 for resistor locations). When evaluating the Si5330, the XTAL must be
removed. The differential input on pins IN5/IN6 is ac-coupled with a 100  line termination (R39).

Figure 2. Optional Termination Resistors for Differential Inputs IN1/IN2

5.2. Single-Ended Inputs (IN3, IN4) [Not supported in Si5335]
These inputs are dc-coupled to the device. They are compatible with a signal swing as low as 100 mV and a
maximum of 3.63 V. The signal should have a minimum amount of dc bias to ensure that it is never below ground
level.
The EVB provides pads for optional input terminations. These may be necessary when interfacing to SSTL and
HSTL signals.
Note: For details on populated vs. non-populated components, refer to "8. Bill of Materials" on page 9.

4 Rev. 1.5
 Si5338-EVB
6. Outputs (CLKxA/CLKxB)
Each of the four differential output drivers is capacitively coupled to the SMA connectors; so, the output signal will
have no dc bias. If a signal with dc bias is required, the ac coupling capacitors can be replaced with a 0  resistor.
The EVB provides pads for optional output terminations. These may be necessary when interfacing to SSTL and
HSTL signals.
6.1. Evaluating LVPECL Output Clocks
The EVB by default is populated to allow evaluating of all output clock formats with the exception of LVPECL
outputs. To evaluate LVPECL signals on the Si5338-EVB, a few components must be soldered down on the board.
Take CLK0 for example of. Note that CLK0 has R85, R121/R122, R1/R4, R2/R5, R3/R6, C4/C7, and C15/C17
attached to the nets of interest. The EVB comes with only R121/R122 and C15/C17 installed. This allows support
of all output types except LVPECL.
Evaluating an ac-coupled LVPECL clock on CLK0 requires a bias resistor of 130 or 200  to ground on each of the
output lines depending on driver VDDO. Refer to AN408, or Si5335 data sheet if applicable, for termination details.
Make the following changes depending on the CLK0 VDDO voltage:
For 3.3 V LVPECL (ac-coupled)
ꞏ Place 200  resistors in place of R1 and R4.
ꞏ Place 0  resistors in place of C4 and C7.
For 2.5 V LVPECL (ac-coupled)
ꞏ Place 130  resistors in place of R1 and R4.
ꞏ Place 0  resistors in place of C4 and C7.
The LVPECL output may also be dc-coupled to an LVPECL receiver. To dc-couple the CLK0 output, make the
component changes below. Note that R2, R3, R5, and R6 depend on VDDO.
Place0  resistors in place of C15 and C17.
Place 50  resistors in place of R1 and R4.
Place C4 and C7
Select R2 and R3 (and similarly R5 and R6) to give a termination voltage of VTT = VDDO – 2 V.
For LVPECL termination on CLK1, 2, and 3 follow the guidelines above and refer to the schematics in “7.
Si5338-EVB Schematics” as needed.
6.2. Evaluating SSTL/HSTL Output Clocks
To support SSTL/HSTL outputs, either single-ended or differential, replace the output dc blocking capacitors with a
0  resistor. For example, for CLK0 output, replace C15 with 0  resistor for single-ended, or replace both C15 &
C17 with 0  for differential output. Do the same for CLK1,2,3 as needed. Remember to properly terminate at the
receiver input.
The Si5338-EVB can support on-board termination of SSTL/HSTL outputs, if on-board terminated, measurement
of the clock output at the SMA connector would require a high impedance measurement device to prevent
overloading of the output. If on-board output termination is desired, the following components must be installed
(using CLK0 as an example.)

For 1.8 or 2.5 V VDDO: R2 = 2 k, R3 = 2 k, R1 = 50 , C4 = 0.1 µF

For 3.3 V VDDO: R2 = 2.42 k, R3 = 2 k, R1 = 50 , C4 = 0.1 µF

Follow similar guidelines for CLK1,2,3 as required. Refer to AN408, or Si5335 data sheet if applicable, for more
details on clock termination.

Rev. 1.5 5
6
SMA
C15 J1

CLK0A
VDDO0
0.1uF

R1
R2
130
2K

R3
C4
2K 0.1uF

SMA
C17 J4

Si5338 CLK0B
VDDO0
0.1uF

R4
R5 130
J2 2K
C2
SMA
IN1
R6
0.01uF C7
2K
0.1uF
VDDO1

J3
C3 R79
SMA
0
Si5338-EVB

IN2
VDDO2
0.01uF SMA
C5
0.1uF C40 J5
+3.3V
Dummy XTAL used for trace matching
CLK1A
R81
25MHz VDDO1
0 0.1uF
4 GND GND 2 VDDO0
R7
4.99K R8
R9
3 1 INTR C9 130
XTAL2 XTAL1 0.1uF 2K
Test Point
R80
U7 TP12
0 R11
C14
2K 0.1uF

VDDO3
U1 C8
VDD SMA
0.1uF
C41 J6
3 XTAL2 XTAL1 1 R83
0
R82 CLK1B
0 VDDO1
4 GND GND 2 0.1uF
C11
25MHz 0.1uF
R14
R15 130
7. Si5338-EVB Schematics

R84 C12
0 2K
0.1uF
R10 R39
C13

7
24
20
16
15
11
Place R close to XTAL pins 0.1uF R16
C18
100 100 U2 Place close to output pins 2K 0.1uF

VDD
VDD
R12 0 R85 100

VDDO0
VDDO1
VDDO2
VDDO3
J7 R121 0
R77 0 1 22
SMA IN1 CLK0A
R122 0
IN3 2 21
IN2 CLK0B
0 R86 100
R13
R123 0
3 IN3 CLK1A 18
R124 0
4 IN4 CLK1B 17
J8 R87 100
R78 0 R44 0 Si5338
SMA R125 0
IN4 5 IN5 CLK2A 14
R126 0
6 IN6 CLK2B 13
0 R88 100
R45
R127 0
INTRPT 8 INTR CLK3A 10
VTT_IN3
R128 0
VTT_IN4 12 9
Test Point SCL_5338 IN7/SCL CLK3B
Test Point
TP2 19

GND
GND
TP1 SDA_5338 IN8/SDA

23
25
R47 R95 R115 R116 R117 R118 R119 R120
R30 R17 R31
R18 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
2K 49.9 2K 49.9
C58
+ C93 SMA
+ J9
C44
10uF
10uF R25 R26
R34 R35 R21 R22 R23 R24 CLK2A
C22 C23 1K 1K R28 R29
2K 2K 1K 1K 1K 1K VDDO2
0.1uF 0.1uF 49.9 49.9
0.1uF

Rev. 1.5
R20 R19
2K 130

Place the 49.9 ohm resistor and

R27
.1uf cap very close to the 5338 C20
2K 0.1uF
pins. The 2K resistors can be
further away.
SMA
C45 J10

CLK2B
VDDO2
0.1uF
IN1_DRV IN5_DRV IN3_DRV
SCL_DRV
J11 R33 R32
C26
SMA 2K 130
IN4_DRV
IN5 IN2_DRV IN6_DRV SDA_DRV

0.01uF R36
2K C24
0.1uF

J13
C27
SMA
IN6

0.01uF

SMA
C53 J12

CLK3A
VDDO3
0.1uF

R37
R38
130
2K

R40 C28
2K 0.1uF

SMA
C54 J14

CLK3B
VDDO3
0.1uF

R41
R42
130
2K

R43
C30
2K 0.1uF

Figure 3. Si5338-EVB Main Schematic

 R97
+1.2V +3.3V
+3.3V
825
C31 C32 R98
511
0.1uF 0.1uF

1
6
U3
IN1_DRIVE 2 J15 CLKIN
A
B 5 1 2 IN1_DRV
IN1_EN

VCCA
VCCB
+3.3V 4

GND
OEB
U4 +2.5V Ref NLSV1T244

3
3 VIN VOUT 1

C34 R46 R100

C33

GND
1uF 1.02K +1.2V +3.3V
4.7uF +3.3V
2.5V

2
C35 C36 825
R99
511
R49 0.1uF 0.1uF
C37

1
6
1.02K 0.1uF U5
IN2_DRIVE 2 J16 CLKINB
A
B 5 1 2 IN2_DRV
IN2_EN

VCCA
VCCB
+5V_USB +5V_USB +5V_USB 4

GND
+3.3V OEB
NLSV1T244

3
2.7V to 5.5V 0.9V to 5.5V
C38 C39
R50 R51 U6
1K 1K
0.1uF 0.1uF
8 VCCB VCCA 1

SCL_5V 7 SCLB SCLA 2 +3.3V +5V_USB

SDA_5V 6 SDAB SDAA 3

SCL SDA
5 4 Test Point Test Point
EN GND J17 CMOS
+5V_USB TP4 TP3
IN3_DRIVE 1 2
0.1uF IN3_DRV
C42
PCA9517A
C43
0.1uF

R76
1K

10
11
12
I2C_5V_EN 46
+3.3V +3.3V P1.0
+3.3V +3.3V 45

VDD
P1.1

VBUS
44

REGIN
P1.2 IN1_DRIVE
P1.3 43
P1.4 42
P1.5 41
R55 R53 40
R52 R54 U8 P1.6
2K 2K 39 IN2_DRIVE
2K 2K P1.7 J18 CMOSFB
C8051F340 IN4_DRIVE 1 2
38 IN3_DRIVE IN4_DRV
P2.0 IN4_DRIVE
P2.1 37
36 IN5_DRIVE
P2.2 IN6_DRIVE
J19 47 P0.7 P2.3 35
48 34 SCL_5338_DRV
INTRPT P0.6 P2.4 SDA_5338_DRV
SCL_5338 4 4 3 3 1 P0.5 P2.5 33
2 2 1 1 2 P0.4 P2.6 32
3 31 R102
P0.3 P2.7 +1.2V +3.3V
SDA_5338 4
HEADER 2x2 R111 P0.2 +3.3V
5 P0.1 P3.0 30
0 6 29 IN1_EN
P0.0 P3.1 825
28 I2C_5V_EN C46 C47 R101
P3.2 IN2_EN 511
P3.3 27
26 IN5_EN
P3.4 0.1uF 0.1uF
25 IN6_EN
1
6

P3.5 U10
8 D+ P3.6 24
9 23 IN5_DRIVE 2 J20 FBCLK
D- P3.7 A
B 5 1 2 IN5_DRV
IN5_EN
VCCA
VCCB

22 +3.3V 4
GND

P4.0 OEB
P4.1 21
13 20 NLSV1T244
3

RST/C2CK P4.2 R110

14 C2D P4.3 19 0
18 R96
P4.4
P4.5 17 0
+5V_USB 16
P4.6 R104
15
MCU +1.2V

GND
P4.7 +3.3V
+3.3V

7
825
C49 C50 R103

Rev. 1.5
C48 +3.3V
511
+
0.1uF 0.1uF
1
6

10uF R60
U11
J21 1K R61 FBCLKB
IN6_DRIVE 2 J22
USB Type B A
B 5 1 2 IN6_DRV
1 IN6_EN
VCCA
VCCB

4
GND

2 +3.3V OEB
3 1K NLSV1T244
3

4
GND 1 1 2 2
S1 3 4
Test Point 3 4
+5V_USB +5V_USB 5 6 +3.3V

6
5
TP11 5 6
SW PUSHBUTTON 7 7 8 8
9 9 10 10 1K R62 Red D3
C52 R65 1K
INTR
1uF J23
C51 D1 C55 D2
0.1uF MMBD3004S-7-F 0.1uF MMBD3004S-7-F CONN SOCKET 5x2 Shrouded Green D4 220
R67
USB

Green D5 220 J24 SCL

R68
I2C SCL_5338_DRV 1 2 SCL_DRV
+5V_USB
+5V_USB
Green D6
R69 220
RDY

C57
C56 0.1uF

13
13
0.1uF
U13 U14
VDDO0 VDDO0_pin
4 4

VDD
VDD
S1 S1 R63 1.02K
VDDO1 8 VDDO1_pin 8
D D
5 S2 5 S2
VDDO2 VDDO2_pin R64
6 6 1.02K C87
VDDO3 S3 VDDO3_pin S3 C59 +
A0 16 A0 16
7 7 1uF J25 SDA
VDD S4 VDD_pin S4
15 15 10uF SDA_5338_DRV 1 2
A1 A1 SDA_DRV
+3.3V 12 S5 12 S5
11 S6 SCL 1 SCL_5V 11 S6 SCL 1 SCL_5V

R66 10 S7 SDA 3 SDA_5V 10 S7 SDA 3 SDA_5V

+5V_USB
412
9 S8 9 S8
RESETB 2 RESETB 2

GND
GND Address is 1001101

14
14
ADG728 Address is 1001100 ADG728

Figure 4. Si5338-EVB MCU Schematic

Si5338-EVB

7
8
VDDO0 VDDO1 VDDO3
VDDO2
Test Point Test Point Test Point
Test Point
TP5 VDDO1_pin TP6 TP8
VDDO0_pin VDDO0 TP7
J27 VDDO1 VDDO3
J26 VDDO2_pin J28 VDDO2 VDDO3_pin J29
1 2
1 2 1 2
1 2
C89
C60 JUMPER C63
C88 JUMPER C61 1uF JUMPER C65
1uF C62 + C90 C66 JUMPER C67
1uF + C64 +
1uF 1uF C91 1uF +
1uF
10uF 1uF
10uF +5V_USB 9 16 10uF
+5V_USB 9 16 U16 1 10uF
U15 1
NC NC NC
NC NC NC 2 12
2 12 IN OUT
IN OUT
3 13 R106 10
C68 3 13 R105 10 C69 IN OUT
1uF IN OUT 1uF
4 MAX8869 14 9 16
4 MAX8869 14 IN OUT U17 1
IN OUT
5 15 +5V_USB
5 15 IN OUT NC NC NC
IN OUT 2 12
IN OUT
U18 1 9 16
7 6 +5V_USB C70 3 13 R108 10
7 6 SHDNB RSTB 1uF IN OUT
SHDNB RSTB NC NC NC
8 17 2 12 4 MAX8869 14
8 17 C71 SS EPAD IN OUT IN OUT
SS EPAD +5V_USB VDDO1_int_en
3 13 R107 10 5 15
GND SET C72 C73 IN OUT IN OUT
GND SET
0.01uF 1uF 4 MAX8869 14
VDDO0_int_en C74 10 11 IN OUT
10 11 0.01uF 7 SHDNB RSTB 6
0.1uF 5 15
IN OUT
VDDO3_int_en 8 SS EPAD 17

7
10
U19 7 6
Si5338-EVB

SHDNB RSTB +5V_USB GND SET C75

8 SS EPAD 17 0.01uF
1 24 10 11

VDD
B1 B2

VLOGIC
2 23 GND SET C76 C77
A1 A2 0.1uF
0.01uF
3 22 VDDO2_int_en 10 11
W1 W2

7
10
U20
4 B3 B4 21

5 20 1 24

VDD
A3 A4 +5V_USB B1 B2

VLOGIC
+5V_USB 6 AD5263 19 2 23
W3 W4 A1 A2

R70 3 W1 W2 22
9 17 VDDO1_int_en
DIS NC/O2 10K
4 B3 B4 21 +5V_USB
SDA_5V 11 16 VDDO0_int_en
SDI/SDA SDO/O1
5 A3 A4 20
SCL_5V 12 CLK/SCL SHDN_B 15
+5V_USB 6 AD5263 19
W3 W4
13 CSB/AD0 RESB/AD1 14
R71
9 17 VDDO3_int_en
DIS NC/O2 10K

VSS
GND
SDA_5V 11 16 VDDO2_int_en
SDI/SDA SDO/O1

8
Address is 0101100

18
SCL_5V 12 CLK/SCL SHDN_B 15

+5V_USB 13 CSB/AD0 RESB/AD1 14

VSS
VDD
8GND
Test Point
TP13 18 Address is 0101101

J30 VDD
VDD_pin

1 2

JUMPER C79

C92 C78
+
Voltage +3.3V
1uF 1uF 10uF
Test Point
TP10

Rev. 1.5
+5V_USB
U21 1 9 16
Regulators +3.3V
NC NC NC
2 IN OUT 12

3 13 R109 10
IN OUT GND GND GND GND
C80
4 MAX8869 14 Test Point Test Point Test Point Test Point
1uF IN OUT C82
TP14 TP15 TP16 TP17 +
5 IN OUT 15 C81
10uF 1uF
7 SHDNB RSTB 6
+5V_USB
8 SS EPAD 17
U22 1 9 16
+5V_USB
GND SET C83
NC NC NC
0.01uF C84 2 12
VDD_int_en 10 11 IN OUT
0.1uF
C85 3 IN OUT 13
1uF

7
10
U23 4 MAX8869 14
IN OUT
+5V_USB 5 15
1 24 IN OUT

VDD
B1 B2 R72 10K

VLOGIC
2 A1 A2 23
7 SHDNB RSTB 6
3 W1 W2 22
8 SS EPAD 17
4 21 C86
B3 B4
GND SET 0.01uF
5 A3 A4 20
10 11
+5V_USB 6 AD5263 19
W3 W4 +5V_USB R74
R73 10K
9 DIS NC/O2 17

SDA_5V 11 16 VDD_int_en 47.5K

SDI/SDA SDO/O1
R75
SCL_5V 12 CLK/SCL SHDN_B 15 15.4K
13 CSB/AD0 RESB/AD1 14

VSS
8GND

18
Address is 0101110

Figure 5. Si5338-EVB Voltage Regulation Schematic

 Si5338-EVB
8. Bill of Materials

Table 1. Si5338-EVB Bill of Materials

Item NI Qty Reference Value Manufacturer Part Number
1 10 C2,C3,C26,C27,C71,C72, 0.01 µF Venkel C0402X7R100-103M
C75,C76,C83,C86
2 35 C15,C17,C31,C32,C35,C36,C3 0.1 µF Venkel C0402X7R100-104K
7,C38,C39,C40,C41,C42,C43,
C44,C45,C46,C47,C49,C50,C5
1,C53,C54,C55,C56,C57,C74,
C77,C84,C5,C8,C9,C11,C12
C13
4 1 C33 4.7 µF Venkel C1206X7R100-475M
5 3 C34,C52,C59 1 µF Venkel C1206X7R250-105K
6 7 C48,C61,C63,C65,C67, 10 µF Kemet B45196H5106M309
C79,C82
7 17 C60,C62,C64,C66,C68,C69, 1 µF Venkel C0603X7R100-105K
C70,C73,C78,C80,C81,C85,
C88,C89,C90,C91,C92
8 2 D1,D2 MMBD3004S-7-F Diodes Inc. MMBD3004S-7-F
9 1 D3 Red Panasonic LN1271RAL
10 3 D4,D5,D6 Green Panasonic LN1371G
11 14 J1,J2,J3,J4,J5,J6,J7,J8, SMA Johnson 142-0701-801
Components
J9,J10,J11,J12,J13,J14
12 13 J15,J16,J17,J18,J20,J22, JUMPER Samtec TSW-102-07-T-S
J24,J25,J26,J27,J28,J29,J30
13 1 J19 HEADER 2x2 Samtec TSW-102-07-T-D
14 1 J21 USB Type B Tyco 292304-1
15 1 J23 CONN SOCKET 5x2 Tyco 5103309-1
Shrouded
18 1 R7 4.99K Venkel CR0402-16W-4991F
19 1 R39 100 Venkel CR0201-20W-1000F
20 7 R44,R45,R77,R78,R96,R110,R 0 Venkel CR0402-16W-000
111
21 2 R28,R29 49.9 Venkel CR0402-16W-49R9F
22 13 R21,R22,R23,R24,R25,R26, 1K Venkel CR0402-16W-102J
R50,R51,R60,R61,R62,R65,R7
6
23 4 R46,R49,R63,R64 1.02K Venkel TFCR0402-16W-E-1021B
25 4 R52,R53,R54,R55 2K Venkel CR0402-16W-2001F
26 1 R66 412 Venkel TFCR0402-16W-E-4120B
27 3 R67,R68,R69 220 Venkel CR0402-16W-221J
28 4 R70,R71,R72,R73 10K Venkel CR0402-16W-103J
29 1 R74 47.5K Venkel CR0603-10W-4752F
30 1 R75 15.4K Venkel CR0603-10W-1542F
31 6 R79,R80,R81,R82,R83,R84 0 Venkel CR0603-16W-000

Rev. 1.5 9
Si5338-EVB
Table 1. Si5338-EVB Bill of Materials (Continued)
Item NI Qty Reference Value Manufacturer Part Number
32 4 R97,R100,R102,R104 825 Venkel CR0603-10W-8250F
33 4 R98,R99,R101,R103 511 Venkel CR0603-10W-5110F
34 5 R105,R106,R107,R108,R109 10 Venkel CR2512-2W-10R0D
35 8 R121,R122,R123,R124, 0 Venkel CR0201-20W-000F
R125,R126,R127,R128
36 1 S1 SW PUSHBUTTON Mountain Switch 101-0161-EV
37 1 TP11 Test Point Kobiconn 151-207
38 1 U1 25 MHz Epson FA-238 25.0000MB
39 1 U2 Si5338 SiLabs Si5338N-A-GMR
40 4 U3,U5,U10,U11 NLSV1T244 On Semi NLSV1T244MUTBG
41 1 U4 2.5 V Analog Devices AD1582BRT
42 1 U6 PCA9517A NXP PCA9517AD
43 1 U8 C8051F340 SiLabs C8051F340-GQ
44 2 U13,U14 ADG728 Analog Devices ADG728BRUZ
45 6 U15,U16,U17,U18,U21,U22 MAX8869 MAXIM MAX8869EUE50
46 3 U19,U20,U23 AD5263 Analog Devices AD5263BRUZ20
47 4 Standoffs SPC Technology 2397
48 4 Screws Richco NSS-4-4-01
49 7 Jumpers Sullins SPC02SYAN
Do Not Populate
2 NI 9 C4,C7,C14,C18, 0.1 µF Venkel C0402X7R100-104K
C22,C23,C20, C24,C28,C30,
6 NI 3 C58, C93, C87 10 µF Kemet B45196H5106M309
16 NI 8 R1,R4,R8,R14,R19,R32,R37, 130 Venkel CR0402-16W-131F
R41
17 NI 20 R2,R3,R5,R6,R9,R11,R15, 2K Venkel TFCR0402-16W-E-2001B
R16,R20,R27,R30,R31,R33,
R34,R35,R36,R38,R40,R42,
R43
19 NI 5 R10,R85,R86,R87,R88 100 Venkel CR0201-20W-1000F
20 NI 2 R12,R13 0 Venkel CR0402-16W-000
24 NI 8 R47,R95,R115,R116,R117, 49.9 Venkel CR0402-16W-49R9F
R118,R119,R120
21 NI 2 R17,R18 49.9 Venkel CR0402-16W-49R9F
37 NI 12 TP1,TP2,TP3,TP4,TP5,TP6, Test Point Kobiconn 151-207
TP7,TP8,TP9,TP10,TP12,TP13
38 NI 1 U7 25 MHz Epson FA-238 25.0000MB-W

10 Rev. 1.5
 Si5338-EVB
REVISION HISTORY
Revision 1.5
March, 2020
Replaced ClockBuilder Desktop instructions with ClockBuilder Pro instructions.
Revision 1.4
November, 2011
Added "6.1. Evaluating LVPECL Output Clocks" on page 5.
Added references to the Si5335.

Revision 1.3
July, 2011
Added "8. Bill of Materials" on page 9.
Revision 1.2
June, 2010
Changed “Any Rate Clock Generator” to “ClockBuilder Desktop” throughout.
Changed “MultiSynth Clock Programmer” to “ClockBuilder Desktop” throughout.
Updated Figure 3 on page 6.
Removed “Uninstaller Option” figure.
Updated Figure 8 on page 9.

Revision 1.1
August, 2009
Changed “Si533x configuration” to “Any Rate Clock Generator” throughout.
Changed “Si5338 Programmer” to “MultiSynth Clock Programmer” throughout.
Updated Table 1, “Programs,” on page 7.
Updated Figures 3, 4, and 8.

Revision 1.0
November, 2008
Replaced the voltage input terminal block with programmable regulators.
The board is entirely powered from USB power.
Added an additional LED to indicate MCU ready.
Added jumpers on all input pins to allow external control of features, such as output enable, and frequency
and phase increment and decrement.
Revision 0.1
September, 2008
Initial release.

Rev. 1.5 11
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