DATASHEET

EL4585 FN7175
Horizontal Genlock, 8FSC Rev 4.00
September 3, 2009

The EL4585 is a PLL (Phase Lock Loop) sub-system, Features

designed for video applications and also suitable for general
purpose use up to 36MHz. In video applications, this device • 36MHz, general purpose PLL
generates a TTL/CMOS-compatible pixel clock (CLK OUT) • 8FSC timing (use the EL4584 for 4FSC)
which is a multiple of the TV horizontal scan rate and phase
• Compatible with EL4583 sync separator
locked to it.
• VCXO, Xtal, or LC tank oscillator
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog • < 2ns jitter (VCXO)
composite video signal with the EL4583 sync separator. An • User-controlled PLL capture and lock
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video • Compatible with NTSC and PAL TV formats
timing such as VTR head switching. The lock detector output • 8 pre-programmed popular TV scan rate clock divisors
indicates correct lock.
• Single 5V, low current operation
The divider ratio is four ratios for NTSC and four similar
• Pb-Free Available (RoHS Compliant)
ratios for the PAL video timing standards by external
selection of three control pins. These four ratios have been Applications
selected for common video applications including 8FSC,
6FSC, 27MHz (CCIR 601 format) and square picture • Pixel clock regeneration
elements used in some workstation graphics. To generate • Video compression engine (MPEG) clock generator
4FSC, 3FSC, 13.5MHz (CCIR 601 format) etc., use the
• Video capture or digitization
EL4584, which does not have the additional divide-by-two
stage of the EL4585. • PIP (Picture in Picture) timing generator
For applications where these frequencies are inappropriate • Text or graphics overlay timing
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used. Ordering Information
FREQUENCIES AND DIVISORS PART PART PKG.
NUMBER MARKING PACKAGE DWG. #
6FSC CCIR 601 SQUARE EL4585CN EL4585CN 16 Ld PDIP E16.3
FUNCTION (Note 1) (Note 2) (Note 3) 8FSC
EL4585CS EL4585CS 16 Ld SOIC MDP0027
Divisor (Note 4) 1702 1728 1888 2270 EL4585CS-T7* EL4585CS 16 Ld SOIC MDP0027
PAL FOSC (MHz) 26.602 27.0 29.5 35.468 EL4585CS-T13* EL4585CS 16 Ld SOIC MDP0027
Divisor (Note 4) 1364 1716 1560 1820 EL4585CSZ EL4585CSZ 16 Ld SOIC MDP0027
(Note 5) (Pb-free)
NTSC FOSC (MHz) 21.476 27.0 24.546 28.636
EL4585CSZ-T7* EL4585CSZ 16 Ld SOIC MDP0027
NOTES: (Note 5) (Pb-free)
1. 6FSC frequencies do not yield integer divisors. EL4585CSZ-T13* EL4585CSZ 16 Ld SOIC MDP0027
(Note 5) (Pb-free)
2. CCIR 601 divisors yield 1440 pixels in the active portion of each
line for NTSC and PAL. *Please refer to TB347 for details on reel specifications.
NOTES:
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL. 5. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
4. Divisor does not include ÷ 2 block.
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet
or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. For 3FSC and 4FSC clock frequency operation, see EL4584
datasheet.

Demo Board
A demo PCB is available for this product.

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EL4585

Pinout
EL4585
(16 LD SOIC, PDIP)
TOP VIEW

PROG B 1 16 PROG A

PROG C 2 15 CLK OUT

OSC/VCO OUT 3 14 VSS (D)

VDD (A) 4 13 EXT DIV

OSC/VCO IN 5 12 LOCK DET

VSS (A) 6 11 VDD (D)

CHARGE PUMP OUT 7 10 HSYNC IN

DIV SELECT 8 9 COAST

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EL4585

Absolute Maximum Ratings (TA = +25°C) Thermal Information

VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Thermal Resistance (Typical, Note 7) JA (°C/W)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C 16 Lead PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V 16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Operating Conditions Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36MHz
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTE:
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

DC Electrical Specifications VDD = 5V, TA = +25°C unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

IDD VDD = 5V (Note 8) 2 4 mA

VIL Input Low Voltage 1.5 V

VIH Input High Voltage 3.5 V

IIL Input Low Current All inputs except COAST, VIN = 1.5V -100 nA

IIH Input High Current All inputs except COAST, VIN = 3.5V 100 nA
IIL Input Low Current COAST pin, VIN = 1.5V -100 -60 µA

IIH Input High Current COAST pin, VIN = 3.5V 60 100 µA

VOL Output Low Voltage Lock Det, IOL = 1.6mA 0.4 V

VOH Output High Voltage Lock Det, IOH = -1.6mA 2.4 V

VOL Output Low Voltage CLK, IOL = 3.2mA 0.4 V

VOH Output High Voltage CLK, IOH = -3.2mA 2.4 V

VOL Output Low Voltage OSC Out, IOL = 200µA 0.4 V

VOH Output High Voltage OSC Out, IOH = -200µA 2.4 V

IOL Output Low Current Filter Out, VOUT = 2.5V 200 300 µA
IOH Output High Current Filter Out, VOUT = 2.5V -300 -200 µA

IOL/IOH Current Ratio Filter Out, VOUT = 2.5V 1.05 1.0 0.95

ILEAK Filter Out Coast Mode, VDD > VOUT > 0V -100 ±1 100 nA
NOTE:
8. All inputs to 0V, COAST floating.

AC Electrical Specifications VDD = 5V, TA = +25°C unless otherwise noted

PARAMETER CONDITIONS MIN TYP MAX UNIT

VCO Gain @ 20MHz Test circuit 1 15.5 dB

HSYNC S/N Ratio VDD = 5V (Note 9) 35 dB

Jitter VCXO oscillator 1 ns

Jitter LC oscillator (Typ) 10 ns

NOTE:
9. Noisy video signal input to EL4583, HSYNC input to EL4585. Test for positive signal lock.

FN7175 Rev 4.00 Page 3 of 15

September 3, 2009
EL4585

Pin Descriptions
Pin NUMBER PIN NAME FUNCTION

1, 2, 16 PROG B, C, A Digital inputs to select ÷ N value for internal counter. See Table 1 for values.

3 OSC/VCO OUT Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4 VDD (A) Analog positive supply for oscillator, PLL circuits.

5 OSC/VCO IN Input from external VCO.

6 VSS (A) Analog ground for oscillator, PLL circuits.

7 CHARGE PUMP Connect to loop filter. If the HSYNC phase is leading or HSYNC frequency > CLK ÷ 2N, current is pumped
OUT into the filter capacitor to increase VCO frequency. If HSYNC phase is lagging or frequency < CLK ÷ 2N,
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.

8 DIV SELECT Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ 2N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷N.

9 COAST Three-state logic input. Low (< 1/3*VCC) = normal mode, Hi Z (or 1/3 to 2/3*VCC) = fast lock mode,
High (> 2/3*VCC) = coast mode.

10 HSYNC IN Horizontal sync pulse (CMOS level) input.

11 VDD (D) Positive supply for digital, I/O circuits.

12 LOCK DET Lock detect output. Low level when PLL is locked. Pulses high when out of lock.

13 EXT DIV External divide input when DIV SEL is low, internal ÷ 2N output when DIV SEL is high.

14 VSS (D) Ground for digital, I/O circuits.

15 CLK OUT Buffered output of the VCO.

TABLE 1. VCO DIVISORS

PROG A (PIN 16) PROG B (PIN 1) PROG C (PIN 2) DIV VALUE (N)
0 0 0 1702

0 0 1 1728

0 1 0 1888
0 1 1 2270

1 0 0 1364

1 0 1 1716

1 1 0 1560

1 1 1 1820

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EL4585

Timing Diagrams

~200ns ± 50ns

H-SYNC
(INPUT)

EXT. DIV.
(INPUT OR
OUTPUT)

PLL LOCKED CONDITION (PHASE ERROR = 0)

~200ns

HSYNC
tH

t0

EXT. DIV
- + E = ttH  360°
tH = HSYNC PERIOD
t = PHASE ERROR PERIOD

+
CHARGE
PUMP -OFF OFF

OUT OF LOCK CONDITION

Test Circuit

+ 3
VOUT
-
300k

0.1µF
VIN
5

10mVRMS

TEST CIRCUIT 1

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EL4585

Typical Performance Curves

FIGURE 1. IDDvs FOSC FIGURE 2. OSC GAIN @ 20MHz vs TEMP

FIGURE 3. TYPICAL VARACTOR FIGURE 4. OSC GAIN vs FOSC

FIGURE 5. CHARGE PUMP DUTY CYCLE vs E

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EL4585

Typical Performance Curves (Continued)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD CONDUCTIVITY TEST BOARD
1.8 2.0
1.6 1.8
POWER DISSIPATION (W)

POWER DISSIPATION (W)

1.4 1.6
1.23W 1.43W
1.2 1.4
1.25W
PDIP16 1.2 PDIP16
1.0 0.91W
JA = +81°C/W JA = +70°C/W
1.0
0.8
0.8 SO16 (0.150”)
0.6
SO16 (0.150”) 0.6 JA = +80°C/W
0.4 JA = +110°C/W
0.4
0.2 0.2
0 0
0 25 50 75 85 100 125 150 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)

FIGURE 6. POWER DISSIPATION vs AMBIENT FIGURE 7. POWER DISSIPATION vs AMBIENT

TEMPERATURE TEMPERATURE

EL4585 Block Diagram

Description Of Operation is sent to the CLK out pin, divided by two, then sent to the
divide by N counter. The divisor N is determined by the state
The horizontal sync signal (CMOS level, falling leading edge)
of pins 1, 2, and 16 and is described in Table 1. The divided
is input to HSYNC input (pin 10). This signal is delayed about
signal is sent, along with the delayed HSYNC input, to the
200ns, the falling edge of which becomes the reference to
phase/frequency detector, which compares the two signals
which the clock output will be locked (See “Timing Diagrams”
for phase and frequency differences. Any phase difference is
on page 5). The clock is generated by the signal on pin 5,
converted to a current at the charge pump output, (pin 7). A
OSC IN. There are 2 general types of VCO that can be used
VCO with a positive frequency deviation with control voltage
with the EL4585, LC and crystal controlled. Additionally,
must be used. Varactors have negative capacitance slope
each type can be either built up using discrete components,
with voltage, resulting in positive frequency deviation with
including a varactor as the frequency controlling element, or
increasing control voltage for the oscillators in Figures 10
complete, self contained modules can be purchased with
and 11.
everything inside a metal can. These modules are very
forgiving of PCB layout, but cost more than discrete VCO
solutions. The VCO or VCXO is used to regulate the clock. The VCO should be tuned so that its frequency of oscillation
An LC tank resonator has greater “pull” than a crystal is very close to the required clock output frequency when the
controlled circuit, but will also be more likely to drift over voltage on the varactor is 2.5V. VCXO and VCO modules are
time, and thus will generate more jitter. The “pullability” of the already tuned to the desired frequency, so this step is not
circuit refers to the ability to pull the frequency of oscillation necessary if using one of these units. The output range of
away from its center frequency by modulating the voltage on the charge pump output (pin 7) is 0V to 5V, and it can source
the control pin of the VCO module or varactor, and is a or sink a maximum of about 300µA, so all frequency control
function of the slope and range of the capacitance-voltage must be accomplished with variable capacitance from the
curve of the varactor or VCO module used. The VCO signal

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EL4585

varactor within this range. Crystal oscillators are more stable modulate the VCO frequency. Modulation will continue until
than LC oscillators, which translates into lower jitter, but LC the phase and frequency of CLK ÷ 2N exactly match the
oscillators can be pulled from their mid-point values further, HSYNC input. When the phase and frequency match (with
resulting in a greater capture and locking range. If the some offset in phase that is a function of the VCO
incoming horizontal sync signal is known to be very stable, characteristics), the error signal goes to zero, lock detect no
then a crystal oscillator circuit can be used. If the HSYNC longer pulses high, and the charge pump enters a high
signal experiences frequency variations of greater than impedance state. The clock is now locked to the HSYNC
about 300ppm, an LC oscillator should be considered, as input. As long as phase and frequency differences remain
crystal oscillators are very difficult to pull this far. When small, the PLL can adjust the VCO to remain locked and lock
HSYNC input frequency is greater than CLK frequency ÷ 2N, detect remains low.
charge pump output (pin 7) sources current into the filter
Fast Lock Mode
capacitor, increasing the voltage across the varactor, thus
tending to increase VCO frequency. Conversely, charge Fast Lock mode is enabled by either allowing coast to float,
pump output pulls current from the filter capacitor when or pulling it to mid supply (between 1/3 and 2/3*VCC). In this
HSYNC frequency is less than CLK ÷ 2N, forcing the VCO mode, lock is achieved much faster than in normal mode, but
frequency lower. the clock divisor is modified on the fly to achieve this. If the
phase detector detects an error of enough magnitude, the
Loop Filter clock is either inhibited or reset to attempt a “fast lock” of the
The loop filter controls how fast the VCO will respond to a signals. Forcing the clock to be synchronized to the HSYNC
change in phase comparator output stimulus. Its input this way allows a lock in approximately 2 H-cycles, but
components should be chosen so that fast lock can be the clock spacing will not be regular during this time. Once
achieved, yet with a minimum of VCO “hunting”, preferably in the near lock condition is attained, charge pump output
one to two oscillations of charge pump output, assuming the should be very close to its lock-on value, and placing the
VCO frequency starts within capture range. If the filter is device into normal mode should result in a normal lock very
under-damped, the VCO will over and under-shoot the quickly. Fast lock mode is intended to be used where HSYNC
desired operating point many times before a stable lock becomes irregular, until a stable signal is again obtained.
takes place. It is possible to under-damp the filter so much
Coast Mode
that the loop itself oscillates, and VCO lock is never
achieved. If the filter is over-damped, the VCO response Coast mode is enabled by pulling COAST (pin 9) high
time will be excessive and many cycles will be required for a (above 2/3*VCC). In coast mode the internal phase detector
lock condition. Over-damping is also characterized by an is disabled and filter out remains in high impedance mode to
easily unlocked system because the filter can’t respond fast keep filter out voltage and VCO frequency as constant as
enough to perturbations in VCO frequency. A severely over possible. VCO frequency will drift as charge leaks from the
damped system will seem to endlessly oscillate, like a very filter capacitor, and the voltage changes the VCO operating
large mass at the end of a long pendulum. Due to parasitic point. Coast mode is intended to be used when noise or
effects of PCB traces and component variables, it will take signal degradation result in loss of horizontal sync for many
some trial and error experimentation to determine the best cycles. The phase detector will not attempt to adjust to the
values to use for any given situation. Use the component resultant loss of signal so that when horizontal sync returns,
tables as a starting point, but be aware that deviations from sync lock can be re-established quickly. However, if much
these values are not out of the ordinary. VCO drift has occurred, it may take as long to re-lock as
when restarting.
External Divide
Lock Detect
DIV SEL (pin 8) controls the use of the internal divider. When
high, the internal divider is enabled and EXT DIV (pin 13) Lock detect (pin 12) will go low when lock is established. Any
outputs the CLK out divided by 2N. This is the signal to DC current path from charge pump out will skew EXT DIV
which the horizontal sync input will lock. When divide select relative to HSYNC in, tending to offset or add to the 200ns
is low, the internal divider output is disabled, and external internal delay, depending on which way the extra current is
divide becomes an input from an external divider, so that a flowing. This offset is called static phase error, and is always
divisor other than one of the 8 pre-programmed internal present in any PLL system. If, when the part stabilizes in a
divisors can be used. locked mode, lock detect is not low, adding or subtracting
from the loop filter series resistor R2 will change this static
Normal Mode phase error to allow LDET to go low while in lock. The goal is
Normal mode is enabled by pulling COAST (pin 9) low to put the rising edge of EXT DIV in sync with the falling
(below 1/3*VCC). If HSYNC and CLK ÷ 2N have any phase or edge of HSYNC + 200ns (see “Timing Diagrams” on
frequency difference, an error signal is generated and sent page 5). Increasing R2 decreases phase error, while
to the charge pump. The charge pump will either force decreasing R2 increases phase error. (Phase error is
current into or out of the filter capacitor in an attempt to

FN7175 Rev 4.00 Page 8 of 15

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EL4585

positive when EXT DIV lags HSYNC.) The resistance needed

will depend on VCO design or VCXO module selection.

Applications Information
Choosing External Components
1. To choose LC VCO components, first pick the desired
operating frequency. For our example we will use
28.636MHz, with an HSYNC frequency of 15.734kHz.
2. Choose a reasonable inductor value (1µ to 5µH works
well). We choose 3.3µH.
3. Calculate CT needed to produce FOSC.
FIGURE 9. TYPICAL XTAL VCO
1
F OSC = -----------------------
2 LC T Typical Application
(EQ. 1)
1 1
C T = --------------------- = ----------------------------------------------------------------------- = 9.4pF
2 2 2 2
4 F L 4  28.636e6   3.3e – 6 

4. From the varactor data sheet find CV @ 2.5V, the desired

lock voltage. CV=23pF for our SMV1204-12 for example.
5. C2 should be about 10CV, so we choose C2=220pF for
our example.
6. Calculate C1. Since:
C1 C2 CV
C T = -------------------------------------------------------------------------- (EQ. 2)
 C1 C2  +  C1 CV  +  C2 CV 

then: Horizontal genlock provides clock for an analog-to-digital

C2 CT CV converter, digitizing analog video.
C 1 = -------------------------------------------------------------------------- (EQ. 3)
 C2 CV  –  C2 CT  –  CT CV 
XTAL VCO COMPONENT VALUES (APPROXIMATE)

For our example, C1=17pF. (A trim capacitor may be used FREQUENCY R1 C1 C2

(MHz) (k) (pF) (µF)
for fine tuning.) Examples for each frequency using the
internal divider is shown in Figure 8. 26.602 300 15 0.001

27.0 300 15 0.001

29.5 300 15 0.001

35.468 300 15 0.001

21.476 300 15 0.001

24.546 300 15 0.001

28.636 300 15 0.001

The oscillators are arranged as Colpitts oscillators

FIGURE 8. TYPICAL LC VCO (see Figure 8), and the structure is redrawn here to emphasize
the split capacitance used in a Colpitts oscillator. It should be
LC VCO COMPONENT VALUES (APPROXIMATE) (Note)
noted that this oscillator configuration is just one of literally
FREQUENCY L1 C1 C2 hundreds possible, and the configuration shown here does not
(MHz) (µH) (pF) (pF) necessarily represent the best solution for all applications.
26.602 3.3 22 220 Crystal manufacturers are very informative sources on the
27.0 3.3 21 220 design and use of oscillators in a wide variety of applications,
29.5 2.7 22 220 and the reader is encouraged to become familiar with them.
35.468 2.2 16 220
21.476 4.7 26 220
24.546 3.9 22 220
28.636 3.3 17 220
NOTE: Use shielded inductors for optimum performance.

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EL4585

probably is not) linear about the lock point (2.5V). Its

value depends on the VCO configuration and the varactor
transfer function CV = F(VC), where VC is the reverse
bias control voltage, and CV is varactor capacitance.
Since F(VC) is nonlinear, it is probably best to build the
VCO and measure KVCO about 2.5V. The results of one
such measurement are shown below. The slope of the
curve is determined by linear regression techniques and
equals KVCO. For our example, KVCO = 9.06 Mrad/s/V.

FIGURE 10. COLPITTS OSCILLATOR

C1 is to adjust the center frequency, C2 DC isolates the
control from the oscillator, and V1 is the primary control
device. C2 should be much larger than CV so that V1 has
maximum modulation capability. The frequency of oscillation
is given by Equation 4:
1
F = -----------------------
2 LC T
(EQ. 4)
C1 C2 Cv
C T = --------------------------------------------------------------------------
 C1 C2  +  C1 CV  +  C1 CV 
FIGURE 11. FOSC vs VC, LC VCO

Choosing Loop Filter Components 5. Now we can solve for C3, C4, and R3 in Equation 7:
The PLL, VCO, and loop filter can be described as:
K d K VCO  4.77e – 5   9.06e6 
C 3 = ------------------------ = ------------------------------------------------------ = 0.01F
2 2
N n  1820   5000 
C3
C 4 = ------- = 0.001F (EQ. 7)
10

2N 2  2   1820   1   5000 

Where: R 3 = ------------------------ = ------------------------------------------------------ = 42.1k
K d K VCO  4.77e – 5   9.06e6 
Kd = phase detector gain in A/rad
We choose R3 = 43k for convenience.
F(s) = loop filter impedance in V/A
6. Notice R2 has little effect on the loop filter design. R2
KVCO = VCO gain in rad/s/V should be large, around 100k, and can be adjusted to
N = Total internal or external divisor (see 3 below) compensate for any static phase error T at lock, but if
made too large, will slow loop response. If R2 is made
It can be shown that for the loop filter shown in Equation 5: smaller, T (see “Timing Diagrams” on page 5) increases,
and if R2 increases, T decreases. For LDET to be low at
K d K VCO C3 2Nn
C 3 = ------------------------ C 4 = ------- R 3 = ------------------------ (EQ. 5) lock, |T| < 50ns. C4 is used mainly to attenuate high
2 10 K d K VCO
N n frequency noise from the charge pump. The effect these
components have on-time to lock is illustrated in
Figure 12.
Where n = loop filter bandwidth, and  = loop filter damping
factor. Lock Time
1. Kd = 300µA/2rad = 4.77e-5A/rad for the EL4585. Let T = R3C3. As T increases, damping increases, but so
does lock time. Decreasing T decreases damping and
2. The loop bandwidth should be about HSYNC
frequency/20, and the damping ratio should be 1 for speeds up loop response, but increases overshoot and thus
optimum performance. For our example, increases the number of hunting oscillations before lock.
n = 15.734kHz/20=787 Hz5000 rad/S. Critical damping (=1) occurs at minimum lock time.
3. N = 910x2 = 1820 from Table 1. Because decreased damping also decreases loop stability, it
is sometimes desirable to design slightly overdamped (>1),
F VCO 28.636M trading lock time for increased stability.
N = -------------------- = ---------------------------- = 1820 = 910x2 (EQ. 6)
F Hsync 15.73426k

4. KVCO represents how much the VCO frequency changes

for each volt applied at the control pin. It is assumed (but

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EL4585

XTAL LOOP FILTER COMPONENTS (APPROXIMATE)

.

FREQUENCY R2 R3 C3 C4
(MHz) (k) (M) (pF) (pF)

26.602 100 4.3 68 6.8

27.0 100 4.3 68 6.8

29.5 100 4.3 68 6.8

35.468 100 4.3 68 6.8

21.476 100 4.3 68 6.8
FIGURE 12. TYPICAL LOOP FILTER
24.546 100 4.3 68 6.8

LC LOOP FILTER COMPONENTS (APPROXIMATE) 28.636 100 4.3 68 6.8

FREQUENCY R2 R3 C3 C4
(MHz) (k) (k) (µF) (µF) PCB Layout Considerations
It is highly recommended that power and ground planes be
26.602 100 39 0.01 0.001
used in layout. The oscillator and filter sections constitute a
27.0 100 39 0.01 0.001 feedback loop and thus care must be taken to avoid any
29.5 100 43 0.01 0.001 feedback signal influencing the oscillator except at the
control input. The entire oscillator/filter section should be
35.468 100 51 0.01 0.001
surrounded by copper ground to prevent unwanted
21.476 100 30 0.01 0.001 influences from nearby signals. Use separate paths for
24.546 100 36 0.01 0.001 analog and digital supplies, keeping the analog (oscillator
section) as short and free from spurious signals as possible.
28.636 100 43 0.01 0.001
Careful attention must be paid to correct bypassing. Keep
lead lengths short and place bypass caps as close to the
supply pins as possible. If laying out a PCB to use discrete
components for the VCO section, care must be taken to
avoid parasitic capacitance at the OSC pins 3 and 5, and
FILTER out (pin 7). Remove ground and power plane copper
above and below these traces to avoid making a capacitive
connection to them. It is also recommended to enclose the
oscillator section within a shielded cage to reduce external
influences on the VCO, as they tend to be very sensitive to
“hand waving” influences, the LC variety being more
sensitive than crystal controlled oscillators. In general, the
higher the operating frequency, the more important these
considerations are. Self contained VCXO or VCO modules
are already mounted in a shielding cage and therefore do
not require as much consideration in layout. Many crystal
manufacturers publish informative literature regarding use
and layout of oscillators which should be helpful.

FN7175 Rev 4.00 Page 11 of 15

September 3, 2009
EL4585

EL4585/4 Demo Board

+5V

+5V

The VCO and loop filter section of the EL4583/4/5 Demo Board can be implemented in the following configurations:

FIGURE 13. VCXO

FIGURE 14. XTAL FIGURE 15. LC TANK

FN7175 Rev 4.00 Page 12 of 15

September 3, 2009
EL4585

Component Sources
Inductors
• Dale Electronics
E. Highway 50
PO Box 180
Yankton, SD 57078-0180
(605) 665-9301
Crystals, VCXO, VCO Modules
• Connor-Winfield
2111 Comprehensive Drive
Aurora, IL 60606
(708) 851-4722
• Piezo Systems
100 K Street
PO Box 619
Carlisle, PA 17013
(717) 249-2151
• Reeves-Hoffman
400 West North Street
Carlisle, PA 17013
(717) 243-5929
• SaRonix
151 Laura Lane
Palo Alto, CA 94043
(415) 856-6900
• Standard Crystal
9940 Baldwin Place
El Monte, CA 91731
(818) 443-2121
Varactors
• Sky Works Solutions Inc.
20 Sylvan Road
Woburn, MA 01801
(781) 376-3000
www.skyworksinc.com
• Motorola Semiconductor Products
2100 E. Elliot
Tempe, AZ 85284
(602) 244-6900
Note: These sources are provided for information purposes
only. No endorsement of these companies is implied by this
listing.

FN7175 Rev 4.00 Page 13 of 15

September 3, 2009
EL4585

Small Outline Package Family (SO)

A

D h X 45°

N (N/2)+1

A
PIN #1
I.D. MARK
E E1
c
SEE DETAIL “X”

1 (N/2)
B
L1
0.010 M C A B

e
H
C
A2

GAUGE
SEATING PLANE 0.010
PLANE
A1 L 4° ±4°
0.004 C 0.010 M C A B b DETAIL X

MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16 SO16 (0.300”) SO20 SO24 SO28
SYMBOL SO-8 SO-14 (0.150”) (SOL-16) (SOL-20) (SOL-24) (SOL-28) TOLERANCE NOTES
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994

FN7175 Rev 4.00 Page 14 of 15

September 3, 2009
EL4585

Dual-In-Line Plastic Packages (PDIP)

E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C
L B1 0.045 0.070 1.15 1.77 8, 10
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.735 0.775 18.66 19.68 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES:
E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7
Publication No. 95.
L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3. N 16 16 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendic-
ular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

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FN7175 Rev 4.00 Page 15 of 15

September 3, 2009