NCP81148

Advance Information
Synchronous Buck Controller
with Auto Power Saving
Mode and Built-In LDO
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NCP81148 is a dual synchronous buck controller that is optimized
for converting the battery voltage or adaptor voltage into multiple
power rails required in desktop and notebook system. NCP81148 MARKING
consists of two buck switching controllers with fixed 5.0 V output on DIAGRAM
channel 2, 3.3 V on channel 1 and two on−board LDOs with three
outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81148 supports 1 81148
ALYWG
high efficiency, fast transient response and provides power good 28 PIN QFN, 4x4 G
signals. ON Semiconductor proprietary adaptive−ripple control MN SUFFIX
enables seamless transition from CCM to DCM, where converter runs CASE 485AR
at reduced switching frequency with much higher efficiency at light
81148 = Specific Device Code
load. The part operates with supply voltage ranging from 5.5 V to A = Assembly Location
28 V. NCP81148 is available in a 28−pin QFN package. L = Wafer Lot
Y = Year
Features W = Work Week
• Wide Input Voltage Range: from 5.5 V to 28 V G = Pb−Free Package
• Built−in 5 V / 60 mA LDO (Note: Microdot may be in either location)
• Built−in selectable 3.3 V or 12 V / 10 mA LDO
• Three Selectable Fixed Frequency 300 KHz, 400 KHz or 600 KHz
PIN CONNECTIONS
• 180 Interleaved Operation Between the Two Channels in

5V_LDOOUT
5V_LDOBYP

LDO2_OUT
5V_LDOEN
Continue−Conduction−Mode (CCM)

LDO2_EN
• Selected Power−Saving Mode/Forced PWM Mode

SKIP
• Transient−Response−Enhancement (TRE) Control

VIN
• Input Supply Voltage Feed Forward Control 28
• Resistive or Lossless Inductor’s DCR Current Sensing GH2
1
GH1
• Over−Temperature Protection BST2 BST1
SWN2 SWN1
• Internal Fixed 8.5 ms Soft−Start GL2 GND GL1/FSET
• Fixed Output Voltages 5 V and 3.3 V PGND2 PGND1
CSP2 CSP1
• Power Good Outputs for Both Channels CSN2 CSN1
• Built−in Adaptive Gate Drivers
• Output Discharge Operation
FB2
COMP2

EN1/SS1
PG

COMP1
FB1
EN2/SS2

• Built−in Over−Voltage, Under−Voltage Protection

• Accurate Over−Current Protection
(Top View)
• Thermal Shutdown

Applications
ORDERING INFORMATION
• Desktop / Notebook Computers
Device Package Shipping†
• System Power Supplies
NCP81148MNTWG QFN−28 4,000 /
• I/O Power Supplies (Pb−Free) Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please
This document contains information on a new product. Specifications and information
refer to our Tape and Reel Packaging Specification
herein are subject to change without notice.
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

January, 2014 − Rev. P0 NCP81148/D
 NCP81148

VIN 5V_LDOOUT

−
+ +
5V_LDOEN ENABLE − 5V_LDOBYP

LDO LDO2_OUT
VREF

−
+
LDO2_EN ENABLE

SKIP
CSP1 + CSA
CSN1 − BST1
Control Logic
Ramp Generator GH1
And
COMP1 Vbias PWM Logic
SW1
VREF
+ E/A
SS
FB1 −
OC & TRE Detection 5V_LDOOUT

UVLO,
UVP, OVP,
EN1 Power Good GL1/
PG1 Vbias FSET
PG OCP, TSD and
Protection PGND1
GND PG2 VIN

Switcher 1 Shown

Figure 1. Block Diagram

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 NCP81148

Table 1. PIN DESCRIPTIONS

Pin
No. Symbol Description
1, 21 GH1, GH2 Gate driver output of the top N−channel MOSFET.
2, 20 BST1, BST2 Top gate driver input supply, a bootstrap capacitor connection between SWNx and this pin.
3, 19 SWN1, SWN2 Switch node between the top MOSFET and bottom MOSFET.
4 GL2 Gate driver output of bottom N−channel MOSFET in channel2.
18 GL1/FSET Gate driver output of bottom N−channel MOSFET in channel1. And it is also used to set up switching
frequency by connecting a resistor from this pin to ground.

5, 17 PGND1, PGND2 Power ground for channel 1 & 2.

6, 16 CSP1, CSP2 Inductor current differential sense non−inverting input.
7, 15 CSN1, CSN2 Inductor current differential sense inverting input.
8, 14 FB1, FB2 Output voltage feed back.
9, 13 COMP1, COMP2 Output of the error amplifier.
10, 12 EN1, EN2 Channel 1 and channel 2 enable pin. Short this pin to ground to disable the switcher channel. Pull this
pin high to enable the switcher channel.

11 PG Power good indicator for both output voltages. Open−drain output.

22 VIN Battery or Adaptor input voltage
23 LDO2_OUT Second internal LDO output. A capacitor of minimum 1.0 mF is recommended to connect between this
pin and ground.
24 LDO2_EN Enable for second internal LDO
− Tie to VCC to setup LDO2 output at 12 V
− Tie to 1/2VCC to setup LDO2 output at 3.3 V
− Tie to ground to disable LDO
25 SKIP DCM programming pin:
− Ground this pin to setup automatic CCM−DCM transfer with 33 KHz minimum switching
frequency limitation;
− Connect this pin to VCC to force CCM operation;
− Leave this pin open to give automatic CCM−DCM transfer with 33 KHz minimum switching
frequency for channel 1 but forced CCM for channel 2.

26 5V_LDOEN Enable for internal 5 V LDO.

27 5V_LDOOUT The output for internal 5 V LDO. A capacitor of minimum 4.7 mF is recommended to connect between
this pin and ground.
28 5V_LDOBYP 5 V LDO bypass pin.
E−Pad GND.

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 NCP81148

5V_LDO LDO2_OUT
(3.3 V)
10 K VIN
10 K

EN5
VOUT1 SKIP

5V_LDOOUT
5V_LDOBYP

LDO2_OUT
5V_LDOEN
22 mFx2

LDO2_EN
SKIP

VIN
28 27 26 25 24 23 22
GH2
GH1
BST2 1 21
Vout2 0.1 mF BST1
2 20 0.1 mF 3.3 mH Vout1
5.0 V / 6.0 V SWN2 3.3 V / 6.0 A
3 SWN1
19
GL2 GL1/FSET
4 AGND 18
PGND2 PGND1
5 17
CSP2
6 16 CSP1
CSN2 CSN1
7 15
8 9 10 11 12 13 14
FB2

FB1
COMP1
COMP2

EN1/SS1
EN2/SS2
PG

Figure 2. Application Circuit

Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)

VIN to GND, 5V_LDOEN to GND −0.3 V (DC) to 28 V −1.0 V for T < 100 n
SWN1, SWN2 to GND −0.6 V to 28 V, −10.0 V for T < 20 ns
BST1, BST2 to GND −0.6 V to 34 V
GH1, GH2 to GND −0.6 V to 34 V, −5.0 V for T < 100 ns
PGND1, PGND2 −0.3 V to 0.3 V
All other pin −0.3 V to 6.0 V, −1.0 V for T < 100 ns
Operating Temperature Range, TA −40°C to +125°C
Junction Temperature, TJ −40°C to +150°C
Storage Temperature Range, TS −55°C to +150°C
Pkg Power Dissipation (TA = +25°C), PD (Note 2) 2.45 W max
RqJA = 51°C/W
RqJ−Lead = 26°C/W
RqJ−BoardTop = 3.2°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Operation at −40°C to 0°C guaranteed by design, not production tested.
2. These data are based on JEDEC JESD51.7 highly conductive PCB multiple layer PCB (2 power and/or 2 ground planes 76 mm x 76 mm
1 oz each) connected by 20 thermal vias. 100 sq mm Cu heat spreader, 2 oz.

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 NCP81148

Table 3. ELECTRICAL CHARACTERISTICS

(VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; −40°C < TA < 125°C for min/max values unless noted otherwise)
Parameter Symbol Test Conditions Min Typ Max Units
POWER SUPPLY
Input Supply Voltage VIN 5.5 28 V
INTERNAL LDO OUTPUT
5V_LDOOUT Voltage VIN =12 V, I5V_LDOOUT = 60 mA 4.85 5.0 5.15 V
5V_LDOOUT Current VIN =12 V, EN1 = EN2 = 0 100 mA
5V_LDO Switch to Bypass Threshold 4.7 4.95 V
5V_LDOOUT to 5V_IDOBYP Impedance LDOBYP = 5 V 1.0 W
Hysteresis 100 200 mV
LDO2_OUT Voltage LDO2_EN = VCC, VIN = 15 V, 11.4 12 12.6 V
Load Current = 10 mA

LDO2_EN = 1/2 VCC, VIN = 15 V, 3.2 3.3 3.46 V

Load Current = 10 mA

LDO2_OUT Current 10 15 mA
SUPPLY CURRENT
BSTx Quiescent Current IBST VFB = 1.5 V, EN = 5.0 0.3 mA
(No Switching), GH and GL are open

BSTx Shutdown Supply Current IBST_SD EN = 0, BST = 5 V, SWN = 0 6.0 mA

Vin Pin Supply Current Iload = 0 2.0 mA
Shutdown Current IVIN_SD EN1, EN2, LDOEN, LDO2_EN = 0 5.0 mA
EN1, EN2, LDOEN = 5 V, 1.15 mA
LDO2_EN = 5 V

EN1, EN2 = 0, LDOEN = 5 V, 1.57 mA

LDO2_EN = 2.5 V

EN1, EN2 = 0, LDOEN = 5 V, 1.11 mA

LDO2_EN = 0
OSCILLATOR
Oscillator Frequency Fsw Rset = 1.8 k 270 300 330 KHz
Rset = 9.1 k 340 400 460 KHz
Rset = 16 k 540 600 660 KHz
Oscillator Frequency Accuracy ±10 %
ERROR AMPLIFIER
Open Loop DC Gain (Note 3) 80 dB

Open Loop Unity Gain Bandwidth (Note 3) F0dB,EA 10 15 MHz

Open Loop Phase Margin (Note 3) 60 deg
Input Bias Current (Note 3) −200 200 nA
Input Offset Voltage (Note 3) V+ = V− = 0.8 V −1.0 1.0 mV
Slew Rate COMP pin to GND = 10 pF 2.5 V/ms
Maximum Output Voltage 10 mV of overdrive, ISOURCE = 2.0 mA 3.3 V
Minimum Output Voltage 10 mV of overdrive, ISINK = 2.0 mA 0.3 V
Output Source Current 10 mV of overdrive, Vout = 3.5 V 2.0 mA
Output Sink Current 10 mV of overdrive, Vout = 1.0 V 2.0 mA
3. Guaranteed by Design
4. Parameters are for design only, not for product test.

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 NCP81148

Table 3. ELECTRICAL CHARACTERISTICS

(VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; −40°C < TA < 125°C for min/max values unless noted otherwise)
Parameter Symbol Test Conditions Min Typ Max Units
FEEDBACK VOLTAGE
Reference Voltage VREF 792 800 808 mV
Feedback Voltage Line Regulation 5V_LDOOUT = 4.5 V ~ 5.5 V 0.25 %/V
DIFFERENTIAL CURRENT SENSE AMPLIFIER
CSP and CSN Common−mode Input Refer to AGND −0.2 5.5 V
Voltage Range

Current Sense Input to Output Gain (CSP)−(CSN) = 10 mV 200 mA/V

Differential Input Voltage Range −60 60 mV
OVER CURRENT PROTECTION
OCP Threshold Voltage V(CSP)−V(CSN) @ 25°C 35 40 45 mV
V(CSP)−V(CSN) @ 0 ~ 85°C 34 46 mV
OCP Trigger Clock Tick After EN, latch off after trigger # clocks 16
Short Circuit OCP Threshold Voltage 60 mV
GATE DRIVER
GH Pull−High Resistance RH_GH Source, V(BST−GH) = 0.1 2.5 W
GH Pull−Low Resistance RL_GH Sink, V(GH−SWN) = 0.1 V 1.5 W
GL Pull−High Resistance RH_GL Source, V(VCC−GL) = 0.1 V 2.0 W
GL Pull−Low Resistance RL_GL Sink, V(GL−PGND) = 0.1 V 1.0 W
Dead Time GL off to GH on 10 20 30 ns
GH off to GL on 10 20 30 ns
VOLTAGE MONITOR
VCC Start Threshold 3.7 4.2 4.4 V
VCC UVLO Hysteresis 100 200 300 mV
Power Good Threshold PG in from lower 91.5 95 97.5 %
PG hysteresis 5.0 %
Power Good High Delay After soft start is done 500 ms
Power Good Low Delay 1.5 ms
Power Good Sink Current PG = 0.4 V 2.5 5.0 mA
Output Overvoltage Rising Threshold After VCC POR, with respect to VFB 106 110 118 %Vref
Overvoltage Fault Blanking Time 1.5 ms
Output Under-Voltage Trip Threshold After soft start, with respect to VFB 45 50 55 %Vref
Under-voltage Protection Blanking Time tss ms
Under−voltage Protection Delay 2.0 ms
PWM
Minimum Controllable ON Time 50 ns
Minimum OFF Time 100 150 ns
PWM Ramp Offset 0.36 0.4 0.44 V
PWM Ramp Amplitude VIN = 5 V 1.25 V
VIN = 12 V 3.0 V
PWM Comparator Propagation Delay 10 mV to 20 mV overdrive 25 30 ns
3. Guaranteed by Design
4. Parameters are for design only, not for product test.

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 NCP81148

Table 3. ELECTRICAL CHARACTERISTICS

(VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; −40°C < TA < 125°C for min/max values unless noted otherwise)
Parameter Symbol Test Conditions Min Typ Max Units
INTERNAL BST DIODE
Forward Voltage Drop IF = 10 mA, TA = 25°C 0.3 V
Reverse−bias Leakage Current VBST = 34 V, VSW = 28 V, TA = 25°C 0.1 6.0 mA
SOFT−STOP
Output Discharge On−Resistance EN = 0, Vout = 0.5 V 20 30 W
Discharge Threshold in Vcc 0.7 V
SOFT−START
Soft−Start Ramp Time tss From EN assertion to Vout ready 6.0 12 18 ms
EN
EN1/EN2 Threshold HI Threshold 1.4 V
LO Threshold 0.4 V
Hysteresis 200 mV
Source Current, pull high to 5 V in- 0.75 mA
ternally
5V_LDOEN Threshold HI Threshold 1.4 V
LO Threshold 0.4 V
Hysteresis 200 mV
LDO2_EN Vout = 3.3 V 1.5 2.5 3.5 V
Vout = 12 V 4.95 5.5 V
Vout = 0 0.4 V
THERMAL SHUTDOWN
Thermal Shutdown Threshold (Note 3) 150 °C
Thermal Shutdown Hysteresis (Note 3) 40 °C
3. Guaranteed by Design
4. Parameters are for design only, not for product test.

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 NCP81148

DETAILED DESCRIPTION

Overview temperature range of the controller. The reference voltage is

The NCP81148 is a cost effective dual output controllers trimmed using a test configuration that accounts for error
with three selectable LDO outputs suitable for desktop and amplifier offset and bias currents.
server application. It provides one independent LDO which
is 5 V/100 mA, two selectable LDOs which is 12 V or Oscillator Frequency
3.3 V/10 mA, and two synchronous PWM controllers that A fixed precision oscillator is provided. The actual
incorporate all the control and protection circuitry necessary switching frequency is set at 300 KHz, 400 KHz or 600 KHz
to satisfy a wide range of applications. The NCP81148 by the resistor on GL1/FSET pin. The resistor and frequency
PWM switchers employ adaptive−ripple control to provide can be referred to the table below.
seamless transition between CCM and DCM while maintain
FSET resistor 1.8 K 9.1 K 16 K
high efficiency during light load. It also provides fast
transient response and excellent stability. The features of the Switching Frequency 300 KHz 400 KHz 600 KHz
NCP81148 include a precision reference, selectable
switching frequency, an error amplifier, adaptive gate Error Amplifier
driver, programmable soft−start, and very low shutdown The error amplifier’s primary function is to regulate the
current. The protection features of the NCP81148 include converter’s output voltage using a resistor divider connected
fixed/programmable soft−start, over−current protection, from the converter’s output to the FB pin of the controller,
wide input voltage range, power good monitor, over voltage as shown in the Applications Schematic. A type III
and under voltage protection, built in output discharge and compensation network must be connected around the error
thermal shutdown. amplifier to stabilize the converter. It has a bandwidth of
greater than 15 MHz, with open loop gain of at least 80 dB.
5V LDO and Switchover (5V_LDOOUT) The COMP output voltage is clamped to a level above the
The NCP81148 includes a high−current (100 mA) linear oscillator ramp in order to improve large−scale transient
regulator that is configured for 5 V operation, which is bias response.
supply necessary to power up the main analog supply rail for
the IC and provides the current for the gate drivers. When the Soft−Start
3.3 V switching regulator is running and the 5 V switching To limit the start−up inrush current, an internal soft start
regulator is still off (EN2 = 0), the 5 V linear regulator can circuit is used to ramp up the reference voltage from 0 V to
provide about 80 mA to external load, while the remaining its final value linearly. The internal soft start time is 13 ms
20 mA is consumed by the 3.3 V regulator’s MOSFETS’ typically, from EN assertion to Vout ready. It includes a
switching, giving typical switching frequency and delay of 240 ms from EN assertion to the Vout ramp starting.
MOSFETS’ gate capaciatance. Once the 5 V switching 500 ms after both channel Vout ready, the PG (Power Good)
regulator is enabled, this 5V_LDO may be bypassed using is asserted.
5V_LDOBYP input. Typically, a capacitor with 10−mF or
Soft−Stop
higher is needed to keep 5V_LDO stable. Additionally, if Soft−Stop or discharge mode is always on during faults or
VOUT2 voltage exceeds 4.75 V, the 5V_LDO is switched disable. In this mode, a fault (UVP, OCP, TSD) or disable
off and VOUT2 (5V buck output) is connected to
(EN) causes the output to be discharged through an internal
5V_LDOOUT through a bypass FET (typical 1 ohm) to
20−ohm transistor inside of VO terminal. The time constant
provide 5 V rail. With this bypass function, the whole system
of soft−stop is a function of output capacitance and the
efficiency is improving. The 5V_LDOEN pin is high resistance of the discharge transistor.
voltage and can be connected to VIN voltage. However,
5V_LDOEN is not allowed to go beyond VIN pin voltage. Adaptive Non−Overlap Gate Driver
In a synchronous buck converter, a certain dead time is
LDO2_OUT
required between the low side drive signal and high side
The NCP81148 includes 10 mA linear regulators that can drive signal to avoid shoot through. During the dead time,
be programmed for 12 V or 3.3 V operations. LDO2 can be
the body diode of the low side FET free-wheels the current.
enabled only when VCC is present. When LDO2_EN is
The body diode has much higher voltage drop than that of
connected to VCC, LDO2_OUT is programmed at 12 V.
the MOSFET, which reduces the efficiency significantly.
When LDO2_EN is connected to 1/2VCC, LDO2_OUT is
The longer the body diode conducts, the lower the
set at 3.3 V. Typically, a minimum capacitor with 1.0−mF or efficiency. NCP81148 implements adaptive dead time
higher is needed to keep LDO2_OUT stable.
control to minimize the dead time, as well as preventing
Reference Voltage shoot through from happening.
The NCP81148 incorporates an internal reference that
allows output voltages as low as 0.8 V. The tolerance of the
internal reference is guaranteed over the entire operating

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 NCP81148

Forced Pulse Width Modulation (FPWM Mode) Over Voltage Protection (OVP)
The device is operating as force PWM mode if SKIP is When VFB voltage is above 110% (typical) of the
tied to VCC. Under this mode, the low−side gate driver nominal VFB voltage, the top gate drive is turned off and the
signal is forced to be the complement of the high−side gate bottom gate drive is turned on trying to discharge the output.
driver signal. This mode allows reverse inductor current, in It over voltage condition still exists after 1.5 ms, an OV fault
such a way that it provides more accurate voltage regulation is set. The power good will go low at the same time. The
and better (fast) transient response. During the soft start bottom gate drive will be turned off when VFB drops below
operation, the NCP81148 automatically runs as FPWM the under voltage threshold. If then over voltage condition
mode regardless of the SKIP setting at either FPWM or happens again, the high side MOSFET stays off and low side
SKIP mode to make sure to have smooth power up. MOSFET will turn on again till output voltage drops down
to under voltage threshold. Then low side gate will be off.
Power Save Mode (Skip Mode) EN resets or power recycle the device can exit the fault.
If the load current decreases, the converter will enter
power save mode operation when SKIP pin is grounded. Under Voltage Protection (UVP)
During power save mode, the converter skips switching and An UVP circuit monitors the VFB voltage to detect under
operates with reduced frequency but with minimum voltage event. The under voltage limit is 50% (typical) of the
switching frequency of 33 KHz, which minimizes the nominal VFB voltage. If the VFB voltage is below this
quiescent current and maintains high efficiency. If SKIP pin threshold over 1 ms, an UV fault is set and the device is
is open, the channel 1 will enter power saving mode with latched off such that both top and bottom gate drives are off.
reduced load but with minimum switching frequency of EN resets or power recycle the device can exit the fault. UVP
33 KHz and channel 2 will stay in forced PWM mode. is delayed for soft start period (8.5 ms) after EN goes high.

Transient Response Enhancement (TRE) EN1 and EN2

For a conventional trailing−edge PWM controller in EN1 and EN2 are logic level control signals to turn on or
CCM, the minimum response delay time is one switching off buck converters individually. If ENx is below 0.4 V, the
period in the worst case. To further improve transient buck will be off. When ENx is above 1.8 V, the buck is
response, a transient response enhancement circuitry is turning on. In both ENx pins, there are about 0.75 mA source
introduced to the NCP81148. The controller continuously currents to pull them up to 5 V internally.
monitors the COMP signal, which is the output voltage of
the error amplifier, to detect load transient events. A desired Power Good Monitor (PG)
stable close−loop system with the NCP81148 has a ripple NCP81148 provides window comparator to monitor the
voltage in the COMP signal, which peak−to−peak value is output voltage. When the output voltage is above 95% of
normally in a range from 200 mV to 500 mV. There is a regulation voltage, the power good pin outputs a high signal.
threshold voltage made in a way that a filtered COMP signal Otherwise, PG stays low. The PG pin is open drain 5−mA
pluses an offset voltage. Once a large load transient occurs, pull down output. During startup, PG stays low until the
the COMP signal is possible to exceed the threshold and then feedback voltage is within the specified range for 128 clocks
TRE is tripped in a short period, which is typically around or about 0.5 ms. If feedback voltage falls outside the
one normal switching cycle. In this short period, the tolerance band, the PG pin goes low within microseconds.
controller runs at higher frequency and therefore has faster Over Current Protection (OCP)
response. After that the controller comes back to normal The NCP81148 protects converter if over−current occurs.
operation. The current through each channel is continuously monitored
PROTECTIONS with differential current sense. Current limit threshold
Vth_OC between CS+ and CS− is internally fixed to 40 mV.
Under Voltage Lockout (UVLO) The current limit can be programmed by inductor’s DCR
There are two undervoltage lock out protections (UVLO) and current sensing resistor divider with Rs1 and Rs2.
in NCP81148. One is for VIN, which has a typical trip
threshold voltage 3.9 V and trip hysteresis 200 mV. The
other is for VCC (5V_LDOOUT serves as VCC internally),
which has a typical trip threshold voltage 4.2 V and trip
hysteresis 300 mV. If either is triggered, the device resets
and waits for the voltage to rise up over the threshold voltage
and restart the part. Please note this protection function
DOES NOT trigger the fault counter to latch off the part.

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 NCP81148

L V O @ (V in * V O)
DCR I LIM + I LIM(Peak) *
Vin Vout 2 @ V in @ f SW @ L

Rs1 C where Vin is the input supply voltage of the power stage, and
fsw is normal switching frequency.
Rs2 Fig. X+1 shows NTC resistor network to compensate the
temperature drift of DCR.
If inductor current exceeds the current threshold, the
high−side gate driver will be turned off cycle−by−cycle. In
the mean time, an internal OC fault timer will be triggered.
+ Vc − If the fault still exists after 16 clocks, the part latches off,
Figure 3. X both the high−side MOSFET and the low−side MOSFET are
turned off. If the sensed current reaches 60 mV, the part will
L latch off right away. The fault remains set until the system
Vin DCR Vout has shutdown and re−applied VCC and/or the enable signal
EN is toggled.
R C
Pre−Bias Startup
R2 In some applications the controller will be required to start
R1
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
RTHE RNTC This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
+ Vc − them or the converter’s output may be held up by a low
Figure 4. X + 1 current standby power supply. NCP81148 supports pre−bias
The Rs1, Rs2 and C can be calculated as: start up by holding Low side FETs off till soft start ramp
reaches the FB pin voltage.
C @ ǒR S1ńńR S2Ǔ + L
DCR Thermal Shutdown
The inductor peak current limit is: The NCP81148 protects itself from over heating with an
internal thermal monitoring circuit. If the junction
V th_DC R S2
I LIM(Peak) + , where k + temperature exceeds the thermal shutdown threshold the
k @ DCR R S1 ) R S2 voltage at the COMP pin will be pulled to GND and both the
upper and lower MOSFETs will be shut OFF.
The DC current limit is:

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 NCP81148

PACKAGE DIMENSIONS

QFN28 4x4, 0.4P

CASE 485AR
ISSUE A

ÇÇÇÇ
NOTES:
D A B L L 1. DIMENSIONING AND TOLERANCING PER ASME

ÇÇÇÇ
Y14.5M, 1994.
PIN ONE 2. CONTROLLING DIMENSION: MILLIMETERS.
REFERENCE 3. DIMENSION b APPLIES TO PLATED TERMINAL

ÇÇÇÇ
L1 AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.

ÇÇÇÇ
4. COPLANARITY APPLIES TO THE EXPOSED PAD
DETAIL A AS WELL AS THE TERMINALS.
ALTERNATE TERMINAL
E CONSTRUCTIONS MILLIMETERS

ÉÉ
DIM MIN MAX
A 0.80 1.00
EXPOSED Cu MOLD CMPD A1 0.00 0.05

ÉÉ
A3 0.20 REF
0.10 C b 0.15 0.25
D 4.00 BSC
D2 2.50 2.70
0.10 C DETAIL B
TOP VIEW ALTERNATE
E 4.00 BSC
E2 2.50 2.70
CONSTRUCTION
A e 0.40 BSC
DETAIL B
K 0.30 REF
A3 L 0.30 0.50
0.10 C L1 −−− 0.15

0.08 C
NOTE 4 A1 SEATING
SIDE VIEW C PLANE

0.10 C A B
RECOMMENDED
DETAIL A D2 MOUNTING FOOTPRINT
K 4.30
8
28X
2.71
15 0.10 C A B 0.62
28X L
1

E2

2.71 4.30
1

PIN 1
INDICATOR 22
e 28X b PACKAGE
OUTLINE 28X
0.07 C A B 0.40 0.26
BOTTOM VIEW 0.05 C NOTE 3 PITCH
DIMENSIONS: MILLIMETERS

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