NCP5269

Synchronous Buck
Controller with Auto Power
Saving Mode and 2-Bit VID
Inputs for System Agent
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NCP5269 is a synchronous buck controller that is optimized for
converting the battery voltage or adaptor voltage into power supply
rails required in notebook and desktop system. NCP5269 is designed MARKING
for applications requiring dynamically selected slew−rate controlled DIAGRAM
output voltages. The soft−start is programmed by a single capacitor.
5269
Voltage identification logic−inputs select four resistor programmed 20 PIN QFN, 3x3
ALYWG
set−point reference voltages that directly set the output voltage of the MN SUFFIX
G
CASE 485BC
converter between 0.65 V to 1.5 V. NCP5269 supports high efficiency,
fast transient response and provides power good signal. ON 5269 = Specific Device Code
Semiconductor proprietary adaptive−ripple control enables seamless A = Assembly Location
transition from CCM to DCM, where converter runs at reduced L = Wafer Lot
switching frequency with much higher efficiency. The part operates Y = Year
W = Work Week
with input voltage ranging from 3.3 V to 28 V. NCP5269 is available G = Pb−Free Package
in a 20−pin 3 mm x 3 mm QFN package.
(Note: Microdot may be in either location)
Features
• Wide Input Voltage Range: from 3.3 V to 28 V
PIN CONNECTIONS
• Three Selectable Fixed Frequency 300 kHz, 400 kHz or 600 kHz

FBRTN
•

COMP
2−Bit VID Selects Four Independent Voltages from 0.65 V to 1.5 V

CSN
CSP
FB
• ±1.0% System Accuracy
• Differential Remote Output Voltage Sensing 1
EN BST
• Soft Transient Control Reduces Inrush Current and Audio Noise
VCC GH
• Build−in Power−Good Masking Supports Voltage Identification VID1 AGND SWN
(VID) On−The−Fly Transients VID0 VCCP
• Simple Resistor Programming Voltage Levels V3 GL/FSET

• Programmable Soft−Start through a Single Capacitor

V2
V1

PG
VREF

PGND

• Automatic Power−Saving Mode

• Input Supply Voltage Feed Forward Control
(Top View)
• Resistive or Lossless Inductor’s DCR Current Sensing
• Over−Temperature Protection
• Built−in Adaptive Gate Drivers ORDERING INFORMATION
• Output Discharge Operation Device Package Shipping†
• Built−in Over−Voltage, Under−Voltage and Over−Current Protection NCP5269MNTWG QFN20 3000 /
and Power Good Output (Pb−Free) Tape & Reel
• This is a Pb−Free Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
Applications refer to our Tape and Reel Packaging Specification
• Notebooks, Desktops & Servers Brochure, BRD8011/D.
• I/O Supplies
• System Power Supplies
• Graphic Cards

© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:

July, 2013 − Rev. 3 NCP5269/D
 NCP5269

VID0
VID1

VID V3
Precision Decoder & V2
Reference Vref
Selection V1
VREF

+ Internal
− Reference

FBRTN

+
E/A
FB −
OC & TRE Detection
BST

COMP
Control Logic GH
Ramp Generator
And
PWM Logic SW
CSP +
CSA
CSN −

VCC

VCCP
EN UVLO,
PG UVP, OVP,
Power Good GL/FSET
OCP, TSD and
Protection
PGND
AGND

Figure 1. Block Diagram

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 NCP5269

Table 1. PIN DESCRIPTIONS

Pin
No. Symbol Description
1 EN Logic control for enabling the switcher. Applying greater than 1.4 V will turn on the part. Connect to GND to
disable.
2 VCC Supply for analog circuit.
3 VID1 Logic input for reference voltage selector. Use in conjunction with the VID0 pin to select among four set−point
reference voltages.

4 VID0 Logic input for reference voltage selector. Use in conjunction with the VID1 pin to select among four set−point
reference voltages.

5 V3 Voltage set−point programming resistor input.

6 V2 Voltage set−point programming resistor input.
7 V1 Voltage set−point programming resistor input. External reference input when enabled by connecting the V3 pin
to the VCC pin.

8 VREF Soft−start programming capacitor input. Set-point reference voltage programming resistor input. Connects
internally to the inverting input of the VSET voltage set-point amplifier.
9 PG Power good indicator of the output voltage. Open−drain output.
10 PGND Ground reference and high−current return path for the bottom gate driver.
11 GL/FSET Gate driver output of bottom N−channel MOSFET. And it is also used to set up switching frequency by
connecting a resistor from this pin to ground.

12 VCCP Power supply for MOSFET gate drive

13 SWN Switch node between the top MOSFET and bottom MOSFET.
14 GH Gate driver output of the top N−channel MOSFET.
15 BST Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
16 CSP Inductor current differential sense non−inverting input.
17 CSN Inductor current differential sense inverting input.
18 FBRTN Feedback Return Input/Output. This pin remotely senses the output voltage. It is also used as the ground
return for the VID reference voltage and the voltage error amplifier blocks.

19 FB Output voltage feed back.

20 COMP Output of the error amplifier.
AGND Analog ground. Bottom thermal pad.

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 NCP5269

C2 C1

FBRTN
R3
C3 R1
VIN

R2 R4
COMP FB CSN CSP Cin
20 19 18 17 16
FBRTN BST CBOOT
EN 1 15

VCC GH
2 14
5.0 V
SWN Vout
VID1 3 AGND 13
V CCP Lo
VCCP 5 .0 V
VID0 4 12 Cout
V3 GL/FSET
5 11
VREF
Rset4 6 7 8 9 10 CVCCP

V2 V1 PG PGND

CSS VCC

PG
Rset3 Rset2 Rset1
FBRTN
Figure 2. Application Circuit

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating Value
VCC to AGND −0.3 V (DC) to 6.5 V
FBRTN, PGND −0.3 V to +0.3 V
SWN to PGND −5.0 V to 28 V, −10.0 V for T < 100 ns
BST, GH to GND −0.3 V to 34 V
BST to SWN, GH to SWN, VCC to PGND, DL to PGND −0.3 V to 6.5 V
All other pins −0.3 V to 6.5 V
Operating Temperature Range, TA −40°C to +100°C
Junction Temperature, TJ −40°C to +100°C
Storage Temperature Range, TS −55°C to +150°C
Package Characteristic 35 °C/W (Note 1)
Thermal Resistance from Junction−to−Ambient (TA = +25°C), Rthja
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This data is for solder on 4−layer board with 2 oz. copper.

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 NCP5269

Table 3. ELECTRICAL CHARACTERISTICS

(VCC = VCCP = 5.0 V, Vout = 1.0 V, TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter Symbol Test Conditions Min Typ Max Units
POWER SUPPLY
VCC Operation Voltage VCC 4.5 5 5.5 V
VCCP Operation Voltage VCCP 4.5 5 5.5 V
VOLTAGE MONITORING & PROTECTION
VCC Start Threshold 3.9 4.2 4.45 V
VCC UVLO Hysteresis 300 350 400 mV
Power Good Low Voltage IPG(sink) = 4 mA 230 300 mV
Power Good High Leakage Current 1.0 mA
Power Good Startup Delay (Note 2) Measure from SSEND to PG 3.3 ms
pos edge
Power Good Propagation Delay Delay for power good in 3.3 ms
Delay for power good out 1.5 ms
Power Good Threshold Power Good in from high 101.5 105 107.5 %
Power Good in from low 92.5 95 98.5 %
PG hysteresis 5 %
Power Good Masking Time Triggered by any VID Change 425 ms
FB Overvoltage Threshold VOVFB−VID Relative to nominal VID Voltage 150 200 250 mV
Overvoltage Propagation Delay 1.5 ms
FB Over Voltage Threshold During Soft− 2.0 V
Start

FB Under−Voltage Trip Threshold VUVFB−VID Relative to nominal VID Voltage −360 −300 −240 mV
Undervoltage Protection Blanking Time 3.3 ms
SUPPLY CURRENT
VCC Quiescent Current IVCC Vskip = 0 V, VFB = 1.5 V, EN = 5.0 3.9 5 mA
(No Switching),
GH and GL are open
VCC Shutdown Supply Current IVCC_SD EN = 0 V 3 mA
VCCP Quiescent Current IVCCP Vskip = 0 V, VFB = 1.5 V, EN = 5.0 0.3 mA
(No Switching),
GH and GL are open
VCCP Shutdown Supply Current IVCCP_SD EN = 0 V 1 mA
BST Quiescent Current IBST Vskip = 0 V, VFB = 1.5 V, EN = 5.0 0.33 mA
(No Switching),
GH and GL are open
BST Shutdown Supply Current IBST_SD EN = 0, BST = 5 V, SWN = 0 1 mA
FEEDBACK VOLTAGE
Reference Voltage VREF 0.65 V
System Accuracy VID0 = VID1 = High, −1.0 +1.0 %
PWM in CCM mode,
−40°C < TA < 100°C
TA = 25°C −0.35 +0.35 %
Feedback Voltage Line Regulation Vcc = 4.5 V ~ 5.5 V 0.75 %/V
2. Guaranteed by characterization or correlation, not production tested

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 NCP5269

Table 3. ELECTRICAL CHARACTERISTICS

(VCC = VCCP = 5.0 V, Vout = 1.0 V, TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter Symbol Test Conditions Min Typ Max Units
VOLTAGE ERROR AMPLIFIER
Open Loop DC Gain (Note 2) 80 dB

Open Loop Unity Gain Bandwidth F0dB,EA 20 MHz

(Note 2)
FB Input Voltage Range (Note 2) 0 2.0 V
FB Bias Current (Note 2) Relative to CSN = VID −1 1 mA
Slew Rate COMP pin to GND = 10 pF 10 V/ms
Maximum Output Voltage 10 mV of overdrive, 3.3 3.5 V
ISOURCE = 2.0 mA

Minimum Output Voltage 10 mV of overdrive, 0.2 0.3 V

ISINK = 2.0 mA

Output Source Current 10 mV of overdrive, Vout = 3.5 V 2 mA

Output Sink Current 10 mV of overdrive, Vout = 1.0 V 2 mA
DIFFERENTIAL CURRENT SENSE AMPLIFIER
CSP and CSN Common−mode Input Refer to AGND −0.2 2.0 V
Voltage Range

Differential Input Voltage Range −30 30 mV

OVER CURRENT PROTECTION
OCP Threshold V(CSP)−V(CSN), mV
Vo = 1 V 27 30 33
Vo = 0.5 V ~ 1.5 V 26 30 34
2_BITS VID
VID0, VID1 High Threshold Voltage 0.65 V
VID0, VID1 Low Threshold Voltage 0.4 V
VID0, VID1 Input Bias Current VID = 0 V 1 nA
VID0, VID1 Pull Down Current 2.5 mA
Charging current during VID up (Note 2) 73 mA
Discharging current during VID down 90 mA
(Note 2)

VID Delay time Any VID edge to 10% of FB 200 ns

change
EN
EN High Threshold Voltage 1.4 V
EN Low Threshold Voltage 0.4 V
EN Input Bias Current IEN EN = 5 V 10 mA
EN Input Voltage 5.5 V
PWM
Minimum Controllable ON Time (Note 2) 30 ns
Minimum OFF Time (Note 2) 300 400 500 ns
PWM Ramp Amplitude (Note 2) VIN = 5 V 1.25 V
VIN = 12 V 3 V
2. Guaranteed by characterization or correlation, not production tested

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 NCP5269

Table 3. ELECTRICAL CHARACTERISTICS

(VCC = VCCP = 5.0 V, Vout = 1.0 V, TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter Symbol Test Conditions Min Typ Max Units
INTERNAL BST DIODE
Forward Voltage Drop IF = 10 mA, TA = 25°C 0.3 V
Reverse−bias Leakage Current VBST = 34 V, VSW = 28 V, 0.1 1 mA
TA = 25°C
SOFT STOP
Output Discharge On−Resistance EN = 0, Vout = 0.65 V 14 30 W
Discharge Threshold in Vcc 0.6 V
SOFT START
Soft Start Current ISS 20 mA
OSCILLATOR
Oscillator Frequency FSW Rset = 2K 270 300 330 KHz
Oscillator Frequency Accuracy ±10 %
GATE DRIVER
GH Pull−High Resistance (Note 2) RH_GH Source, V(BST−GH) = 0.1 1.3 1.8 W
GH Pull−Low Resistance (Note 2) RL_GH Sink, V(GH−SWN) = 0.1 V 1.1 1.6 W
GL Pull−High Resistance (Note 2) RH_GL Source, V(VCC−GL) = 0.1 V 1.0 1.8 W
GL Pull−Low Resistance (Note 2) RL_GL Sink, V(GL−PGND) = 0.1 V 0.5 0.9 W
GH Source Current 2 A
GH Sink Current 2 A
GL Source Current 2 A
GL Sink Current 4 A
Dead Time GL off to GH on 10 20 30 ns
GH off to GL on 10 20 30
THERMAL SHUTDOWN
Thermal Shutdown Threshold (Note 2) 150 °C
Thermal Shutdown Hysteresis (Note 2) 25 °C
2. Guaranteed by characterization or correlation, not production tested

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 NCP5269

DETAILED DESCRIPTION VOUT R1 FB

− E/A
COMP
Overview +
NCP5269 is designed for applications requiring
R2
dynamically selected slew−rate controlled output voltages. REF
It provides a synchronous PWM controller that incorporates 650 mV
Vset +
all the control and protection circuitry necessary to satisfy a FBRTN −
wide range of applications. The NCP5269 PWM controller
employs adaptive ripple control to provide seamless
VREF SW0
transition between CCM and DCM while maintain high
efficiency during light load. It also provides fast transient R3
response and excellent stability. The features of the CSS V1 SW1
NCP5269 include a 2 bits VID selectable and external
programmable reference, fixed three preset switching R4
frequency, an error amplifier, adaptive gate driver, FBRTN V2 SW2
programmable soft−start, and very low shutdown current.
The protection features of the NCP5269 include R5
V3 SW3
over−current protection, power good monitor, over voltage
and under voltage protection, built in output discharge and
thermal shutdown. R6
FBRTN
Reference Voltage Programming
The NCP5269 incorporates 2−bits VID, which selects Figure 3.
four user−programmed reference voltages that reflect on
Vref pin. NCP5269 measures VFB and VREF pin voltage External Reference Voltage and Output Voltage Setting
relative to FBRTN pin. An internal reference that allows Vset0, Vset1, Vset2 and Vset3 can be calculated based on
output voltages as low as 0.65 V. The tolerance of the the following equations:
internal reference is guaranteed over the entire operating V set0 + V INREF
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error V set1 + V INREF @ 1 )ǒ R3
R4 ) R5 ) R6
Ǔ
amplifier offset and bias currents. The VID truth tables for
each part are listed below.
V set2 + V INREF @ 1 )ǒ R3 ) R4
R5 ) R6
Ǔ
Table 4. NCP5269 VID TRUTH TABLE
VID STATE RESULTS V set3 + V INREF @ 1 )ǒ R3 ) R4 ) R5
R6
Ǔ
VID0 VID1 CLOSE VREF VOUT
And V set3 u V set2 u V set1 u V set0
0 0 SW3 Vset3 VOUT4
0 1 SW2 Vset2 VOUT3
Vset0, Vset1, Vset2 and Vset3 are in the range of
0.65 V~1.5 V. If the required output voltage is higher than
1 0 SW1 Vset1 VOUT2
0.65 V~1.5 V, a feedback voltage divider (a resistor R2 is
1 1 SW0 Vset0 VOUT1 added from FB pin to FBRTN) can be used to boost the
output voltage up. So the output voltage can be calculated
based on the following equations:

ǒ RR Ǔ
V OUT1 + V set0 @ 1 ) 1
2

@ ǒ1 ) Ǔ
R 1
V OUT2 + V set1
R 2

@ ǒ1 ) Ǔ
R 1
V OUT3 + V set2
R 2

@ ǒ1 ) Ǔ
R 1
V OUT4 + V set3
R 2

And V OUT4 u V OUT3 u V OUT2 u V OUT1

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 NCP5269

External Reference Voltage Where:

NCP5269 accepts external reference voltage. To enable • ISA2 is the source/sink current limit of set amplifier
this feature, tie V3 to VCC and feed V1 from external during VID changing, which is 73/90 mA.
reference. Then internal 650 mV reference is replaced by the • VO1 and VO2 are the voltages selected by VID inputs
voltage on V1 pin. The output voltage is programmed by
resistor hooked from FB to FBRTN. VID0 and VID1 are Oscillator Frequency
disabled with this function. Please ground both VID0 and A fixed precision oscillator is provided. The actual
VID1 pins. All the resistors on Vref, V1, V2 and V3 are switching frequency is set at 300 KHz, 400 KHz or 600 KHz
removed. The soft−start cap CSS remains on the Vref pin. by the resistor on GL/FSET pin. The resistor and frequency
The V2 pin can be left open. can be referred to the table below.
The reference voltage on V1 pin can be from 0.5 V to
2.0 V. However, the NCP5269 does not provide GL/FSET Resistor 2K 6K 15K
soft−transient feature, forced CCM operation and PG Switching Frequency 300 KHz 400 KHz 600 KHz
blanking for any reference voltage jump on V1. Therefore,
external slewrate control or R/C is recommended to soften Error Amplifier
the reference voltage change on V1 pin input. In addition, The error amplifier’s primary function is to regulate the
minimum load current is required to discharge the output converter’s output voltage, as shown in the Applications
voltage when the reference voltage on V1 pin moves lower, Schematic. A type III compensation network must be
in order to avoid false PG failure. For example, 1 mA connected around the error amplifier to stabilize the
minimum load current is needed to discharge the output converter. It has a bandwidth of greater than 15 MHz, with
voltage, given 0.5 mF output capacitance and external R = open loop gain of at least 80 dB. The COMP output voltage
10 kW, C = 1 mF on the V1 pin to slow down the reference is clamped to a level above the oscillator ramp in order to
voltage change. The minimum load current requirement is improve large−scale transient response.
proportional to the output capacitance and V1 pin reference
voltage slewrate. The initial reference voltage on V1 pin Soft Stop
should be established prior to EN assertion. Soft−Stop or discharge mode is always on during faults or
disable. In this mode, a fault (UVP, OVP, OCP, TSD) or
Differential Sensing of Output Voltage disable (EN) causes the output to be discharged through an
The NCP5269 combines differential sensing with a high internal 20−ohm transistor inside of VO terminal. The time
accuracy VID DAC, referenced by a precision band gap constant of soft−stop is a function of output capacitance and
source and a low offset error amplifier, to provide accurate the resistance of the discharge transistor.
output voltage. The output voltage is sensed between the FB
and FBRTN pins. FB should be connected through a resistor Adaptive Non−Overlap Gate Driver
to the positive regulation point. FBRTN should be connected In a synchronous buck converter, a certain dead time is
directly to the negative remote sensing point. required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
External Soft−Start and VID Change Slew Rate the body diode of the low side FET free-wheels the current.
To limit the start−up inrush current, a capacitor can be The body diode has much higher voltage drop than that of
connected from Vref pin to ground to ramp up reference the MOSFET, which reduces the efficiency significantly.
voltage slowly. During this period, the set amplifier output The longer the body diode conducts, the lower the
20 mA current to charge capacitor CSS. The soft start period efficiency. NCP5269 implements adaptive dead time
can be calculated by the following equation: control to minimize the dead time, as well as preventing
ǒ
t SS + −R A @ C SS @ LN 1 *
VO
Ǔ
I SA1 @ R A
shoot through from happening.

Automatic Power Saving Mode

Where: If the load current decreases, the converter will enter
• RA is the sum of the series resistors from VREF to power save mode operation. During power save mode, the
ground. RA = R3 + R4 + R5 + R6 converter skips switching and operates with reduced
frequency, which minimizes the quiescent current and
• ISA1 is soft start current 20 mA.
maintains high efficiency.
• Vo is the initial output voltage set by VID
The output current of the set amplifier will change to PROTECTIONS
+73 mA /− 90 mA after soft start period. So during voltage Under Voltage Lockout (UVLO)
steps due to VID bit change, the slew rate of output voltage There is under-voltage lock out protections (UVLO) for
can be calculated as follows: VCC in NCP5269, which has a typical trip threshold voltage

ǒ
t SL + −R A @ C SS @ LN 1 *
V O2 * V O1
I SA2 @ R A
Ǔ 4.2 V and trip hysteresis 300 mV. If UVLO is triggered, the
device resets and waits for the voltage to rise up over the

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 NCP5269

threshold voltage and restart the part. Please note this L

DCR
protection function DOES NOT trigger the fault counter to Vin Vout
latch off the part.
Rs1 C
Over Voltage Protection (OVP)
When VFB voltage is 200 mV (typical) above VREF
Rs2
voltage for over 1.5 ms blanking time, an OV fault is set. At
that moment, the top gate driver is turned off and the bottom
gate driver is turned on trying to discharge the output. The
bottom gate driver will be turned off when VFB drops below
under voltage threshold. EN resets or power recycle the + Vc −
device can exit the fault. OVP is disabled during VID Figure 4. Inductor DCR Current Sensing Circuit
changes. Figure 5 shows NTC resistor network to compensate the
temperature drift of DCR.
Under Voltage Protection (UVP) L
An UVP circuit monitors the VFB voltage to detect under DCR
Vin Vout
voltage event. The under voltage limit is 300 mV (typical)
below VREF voltage. If the VFB voltage is below this R C
threshold over 3.3 ms, an UV fault is set and the device is
latched off such that both top and bottom gate drives are off. R2
EN resets or power recycle the device can exit the fault. UVP R1
is delayed for soft start after EN goes high. UVP is disabled
during VID changes. RTHE RNTC

Power Good Monitor (PG)

+ Vc −
NCP5269 provides window comparator to monitor the FB
voltage. The target voltage window and transition delay Figure 5. Inductor DCR Current Sensing Circuit with
times of the PGOOD comparator are ±5% (typ.) and 3.3−ms Temperature Compensation Network
delay for assertion (low to high), and ±10% (typ) and 1.5−ms If inductor current exceeds the current threshold, the
delay for de−assertion (high to low) during running. The PG high−side gate driver will be turned off cycle−by−cycle. In
pin is open drain 5−mA pull down output. During startup, the mean time, an internal OC fault timer will be triggered.
PG stays low until the feedback voltage is within the If the fault still exists after about 8 clock cycles, the part
specified range for about 3.3 ms. To prevent a false alarm; latches off, both the high−side MOSFET and the low−side
the power−good circuit is masked during any VID change. MOSFET are turned off. The fault remains set until the
The duration of the PG mask is set to approximately 425 ms system has shutdown and re−applied VCC and/or the enable
by an internal timer. signal EN is toggled.
Over Current Protection (OCP) Pre−Bias Startup
The NCP5269 protects converter if over−current occurs. In some applications the controller will be required to start
The current through inductor is continuously monitored switching when its output capacitors are charged anywhere
with differential current sense. Current limit threshold from slightly above 0 V to just below the regulation voltage.
Vth_OC between CS+ and CS− is internally fixed to 30 mV. This situation occurs for a number of reasons: the
The current limit can be programmed by inductor’s DCR converter’s output capacitors may have residual charge on
and current sensing resistor divider with Rs1 and Rs2. them or the converter’s output may be held up by a low
The Rs1, Rs2 and C can be calculated as: current standby power supply. NCP5269 supports pre−bias
start up by holding Low side FETs off till soft start ramp
C @ ǒR S1ńńR S2Ǔ + L
reaches the FB pin voltage.
DCR
The inductor peak current limit is: Thermal Shutdown
V th_DC R S2 The NCP5269 protects itself from over heating with an
I LIM(Peak) + , where k + internal thermal monitoring circuit. If the junction
k @ DCR R S1 ) R S2
temperature exceeds the thermal shutdown threshold, an
The DC current limit is: internal resistor will discharge Vref and the voltage at the
COMP pin will be pulled to GND, and both the upper and
V O @ ǒV in * V OǓ
I LIM + ILIM(Peak) * lower MOSFETs will be shut OFF. When temperature drops
2 @ V in @ fSW @ L below threshold, the part will auto restart with soft− start
where Vin is the input supply voltage of the power stage, and feature.
fsw is normal switching frequency.

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 NCP5269

PACKAGE DIMENSIONS

QFN20 3x3, 0.4P

CASE 485BC
ISSUE O

ÍÍÍ
D A B L
L NOTES:
1. DIMENSIONING AND TOLERANCING PER

ÍÍÍ
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
PIN ONE L1

ÍÍÍ
3. DIMENSION b APPLIES TO PLATED
REFERENCE TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
E DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED
ALTERNATE TERMINAL PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS MILLIMETERS
DIM MIN MAX
2X 0.10 C A 0.80 1.00
A3 A1 --- 0.05

ÉÉÉ ÇÇ
ÉÉ
EXPOSED Cu MOLD CMPD A3 0.20 REF
2X 0.10 C b 0.15 0.25

ÉÉÉ ÇÇ
TOP VIEW D 3.00 BSC
D2 1.70 1.90
E 3.00 BSC
0.05 C DETAIL B A3 A1 E2 1.70 1.90
e 0.40 BSC
DETAIL B
A ALTERNATE
K 0.30 REF
L 0.20 0.40
CONSTRUCTIONS L1 0.00 0.15
0.05 C
A1
NOTE 4
SIDE VIEW C SEATING
PLANE
SOLDERING FOOTPRINT*
20X
DETAIL A D2 0.52
6

1
11
20X K
E2
2X 3.30 2X 1.86
1

16
20X L e
20X b 20X
0.26
0.07 C A B 0.40
0.05 C NOTE 3 PITCH
BOTTOM VIEW DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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