NCP81151

MOSFET Driver, VR12.5

Compatible Synchronous
Buck
The NCP81151 is a high performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power www.onsemi.com
MOSFETs in a synchronous buck converter. It can drive up to 3 nF
load with a 25 ns propagation delay and 20 ns transition time. MARKING
Adaptive anti−cross−conduction and power saving operation circuit DIAGRAM
can provide a low switching loss and high efficiency solution for
1
notebook systems. 1
A3MG
The UVLO function guarantees the outputs are low when the supply DFN8 G
voltage is low. CASE 506AA

Features A3 = Specific Device Code

• Faster Rise and Fall Times M = Date Code
G = Pb−Free Package
• Adaptive Anti−Cross−Conduction Circuit (Note: Microdot may be in either location)
• Zero Cross Detection function
• Output Disable Control Turns Off Both MOSFETs
PINOUT DIAGRAM
• Undervoltage Lockout
• Power Saving Operation Under Light Load Conditions
BST 1 8 DRVH
• Direct Interface to NCP6131 and Other Compatible PWM
Controllers PWM 2 7 SW
FLAG
• Thermally Enhanced Package 9
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS EN 3 6 GND
Compliant
VCC 4 5 DRVL
Typical Applications
• Power Management Solutions for Notebook Systems
ORDERING INFORMATION
Device Package Shipping†
NCP81151MNTAG DFN8 3000 / Tape &
(Pb−Free) Reel

NCP81151MNTBG DFN8 3000 / Tape &

(Pb−Free) Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

April, 2015 − Rev. 4 NCP81151/D
 NCP81151

VCC BST

DRVH

PWM Logic
SW
Anti−Cross
Conduction
VCC

DRVL

EN
ZCD
Detection
UVLO

Figure 1. Block Diagram

PIN DESCRIPTIONS
Pin No. Symbol Description
1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and
the SW pin.

2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode
Emulation Enabled, High = High Side FET Enabled.

3 EN Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input:
EN = High to enable the gate driver;
EN = Low to disable the driver;
EN = Mid to go into diode mode (both high and low side gate drive signals are low)
4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.
5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET.
6 GND Bias and reference ground. All signals are referenced to this node.
7 SW Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.
8 DRVH High side gate drive output. Connect to the gate of high side MOSFET.
9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane.

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 NCP81151

APPLICATION CIRCUIT

5V_POWER VIN

TP1
R164 C4 +
0.027uF Q1 C1 C2 C3 CE9
R1
TP2 NTMFS4821N 4.7uF 4.7uF 4.7uF 390uF
1.02 0.0
NCP81151 TP3 R142
R143
0.0 VREG_SW1_HG 0.0
TP4 BST HG TP5
L VCCP
VREG_SW1_OUT
PWM PWM SW
235nH
DRON TP7
EN GND TP6 R3
VREG_SW1_LG Q9 Q10 2.2
VCC LG NTMFS4851N NTMFS4851N
JP13_ETCH CSN11
PAD
C5 TP8 C6
1uF 2700pF
JP14_ETCH CSP11

Figure 2. Application Circuit

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 NCP81151

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL INFORMATION
Symbol Pin Name VMAX VMIN
VCC Main Supply Voltage Input 6.5 V −0.3 V

BST Bootstrap Supply Voltage 35 V wrt/ GND −0.3 V wrt/SW

40 V v 50 ns wrt/ GND
6.5 V wrt/ SW
7.7 V < 50 ns wrt/ SW
SW Switching Node (Bootstrap Supply Return) 35 V −5 V
40 V v 50 ns −10 V (200 ns)

DRVH High Side Driver Output BST + 0.3 V −0.3 V wrt/SW

−2 V (< 200 ns) wrt/SW

DRVL Low Side Driver Output VCC + 0.3 V −0.3 V DC

−5 V (< 200 ns)

PWM DRVH and DRVL Control Input 6.5 V −0.3 V

EN Enable Pin 6.5 V −0.3 V
GND Ground 0V 0V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to AGND unless noted otherwise.

THERMAL INFORMATION
Symbol Parameter Value Unit
RqJA Thermal Characteristic QFN Package (Note 1) 119 °C/W

TJ Operating Junction Temperature Range (Note 2) −40 to 150 °C

TA Operating Ambient Temperature Range −40 to +100 °C
TSTG Maximum Storage Temperature Range −55 to +150 °C
MSL Moisture Sensitivity Level − QFN Package 1
*The maximum package power dissipation must be observed.
1. 1 in2 Cu, 1 oz. thickness.
2. JESD 51−7 (1S2P Direct−Attach Method) with 1 LFM.

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 NCP81151

NCP81151 ELECTRICAL CHARACTERISTICS (−40°C < TA < +100°C; 4.5 V < VCC < 5.5 V, 4.5 V < BST−SWN < 5.5 V,
4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)

Parameter Test Conditions Min Typ Max Unit

SUPPLY VOLTAGE

VCC Operation Voltage 4.5 5.5 V

UNDERVOLTAGE LOCKOUT
VCC Start Threshold 3.8 4.35 4.5 V
VCC UVLO Hysteresis 150 200 250 mV
SUPPLY CURRENT
Shutdown Mode ICC + IBST, EN = GND 11 20 mA
Normal Mode ICC + IBST, EN = 5 V, PWM = OSC 4.7 mA
Standby Current ICC + IBST, EN = HIGH, PWM = LOW, 0.9 mA
No loading on DRVH & DRVL

Standby Current ICC + IBST, EN = HIGH, PWM = HIGH, 1.1 mA

No loading on DRVH & DRVL

BOOTSTRAP DIODE
Forward Voltage VCC = 5 V, forward bias current = 2 mA 0.1 0.4 0.6 V
PWM INPUT
PWM Input High 3.4 V
PWM Mid−State 1.3 2.7 V
PWM Input Low 0.7 V
ZCD Blanking Timer 350 ns
HIGH SIDE DRIVER
Output Impedance, Sourcing Current VBST−VSW = 5 V 0.9 1.7 W
Output Impedance, Sinking Current VBST−VSW = 5 V 0.7 1.7 W
DRVH Rise Time trDRVH VCC = 5 V, 3 nF load, VBST−VSW = 5 V 16 25 ns
DRVH Fall Time tfDRVH VCC = 5 V, 3 nF load, VBST−VSW =5 V 11 18 ns

DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 10 30 ns

DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 10 40 ns

SW Pulldown Resistance SW to PGND 45 kW

DRVH Pulldown Resistance DRVH to SW, BST−SW = 0 V 45 kW
LOW SIDE DRIVER
Output Impedance, Sourcing Current 0.9 1.7 W
Output Impedance, Sinking Current 0.4 0.8 W
DRVL Rise Time trDRVL CLOAD = 3 nF 16 25 ns

DRVL Fall Time tfDRVL CLOAD = 3 nF 11 15 ns

DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 10 30 ns

DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 5.0 25 ns

DRVL Pulldown Resistance DRVL to PGND, VCC = PGND 45 kW

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 NCP81151

NCP81151 ELECTRICAL CHARACTERISTICS (−40°C < TA < +100°C; 4.5 V < VCC < 5.5 V, 4.5 V < BST−SWN < 5.5 V,
4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)

Parameter Test Conditions Min Typ Max Unit

EN INPUT
Input Voltage High 3.3 V
Input Voltage Mid 1.35 1.8 V
Input Voltage Low 0.6 V
Input bias current −1.0 1.0 mA
Propagation Delay Time 20 40 ns
SW NODE
SW Node Leakage Current 20 mA
Zero Cross Detection Threshold Voltage −6.0 mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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 NCP81151

Table 1. DECODER TRUTH TABLE

Input ZCD DRVL DRVH
PWM High (Enable High) ZCD Reset Low High

PWM Mid (Enable High) Positive Current Through the Inductor High Low
PWM Mid (Enable High) Zero Current Through the Inductor Low Low
PWM Low (Enable High) ZCD Reset High Low
Enable at Mid X Low Low

1V

1V

Figure 3.

PWM

DRVH−SW

DRVL

IL

Figure 4. Timing Diagram

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 NCP81151

APPLICATION INFORMATION

The NCP81151 gate driver is a single phase MOSFET high after the tpdhDRVH delay. When PWM is set low, the
driver designed for driving N−channel MOSFETs in a driver will monitor the gate voltage of the high side
synchronous buck converter topology. The NCP81151 is MOSFET. When the DRVH−SWN voltage falls below the
designed to work with ON Semiconductor’s NCP6131 top gate drive threshold, DRVL will be set to high after the
multi−phase controller. This gate driver is optimized for tpdhDRVL delay.
notebook applications.
Layout Guidelines
Undervoltage Lockout The layout for a DC−DC converter is very important. The
DRVH and DRVL are held low until VCC reaches 4.5 V bootstrap and VCC bypass capacitors should be placed close
during startup. The PWM signal will control the gate status to the driver IC.
when VCC threshold is exceeded. Connect the GND pin to a local ground plane. The ground
plane can provide a good return path for gate drives and
Three−State EN Signal reduce the ground noise. The thermal slug should be tied to
When EN is set to the mid state, both DRVH and DRVL the ground plane for good heat dissipation. To minimize the
are set low, to force diode mode operation. ground loop for the low side MOSFET, the driver GND pin
PWM Input and Zero Cross Detect (ZCD) should be close to the low−side MOSFET source pin. The
The PWM input, along with EN and ZCD, control the state gate drive trace should be routed to minimize its length. The
of DRVH and DRVL. minimum width is 20 mils.
When PWM is set high, DRVH will be set high after the Gate Driver Power Loss Calculation
adaptive non−overlap delay. When PWM is set low, DRVL The gate driver power loss consists of the gate drive loss
will be set high after the adaptive non−overlap delay. and quiescent power loss.
When PWM is set to the mid state, DRVH will be set low, The equation below can be used to calculate the power
and after the adaptive non−overlap delay, DRVL will be set dissipation of the gate driver. QGMF is the total gate charge
high. DRVL remains high during the ZCD blanking time. for each main MOSFET and QGSF is the total gate charge for
When the timer has expired, the SW pin will be monitored each synchronous MOSFET.
for zero cross detection. After the detection, DRVL will be
P DRV +
set low.

Adaptive Non−overlap
Adaptive dead time control is used to avoid shoot−through
ƪ f SW
2 n
ǒn MF Q GMF ) n SF Q GSFǓ ) I CCƫ V CC

(eq. 1)
damage of the power MOSFETs. When the PWM signal
pulls high, DRVL will be set low and the driver will monitor Also shown is the standby dissipation factor (ICC x VCC)
the gate voltage of the low side MOSFET. When the DRVL of the driver.
voltage falls below the gate threshold, DRVH will be set to

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 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

DFN8 2x2, 0.5P

CASE 506AA
ISSUE F
1 DATE 04 MAY 2016
SCALE 4:1
NOTES:
D A L L 1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
L1

ÇÇ
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
PIN ONE DETAIL A

ÇÇ
REFERENCE 4. COPLANARITY APPLIES TO THE EXPOSED
E OPTIONAL PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS

ÇÇ
MILLIMETERS
2X 0.10 C DIM MIN MAX

ÉÉ ÉÉ
A 0.80 1.00
A3 A1 0.00 0.05

ÇÇ
ÉÉ ÉÉ
ÇÇ
2X 0.10 C EXPOSED Cu MOLD CMPD A3 0.20 REF
TOP VIEW b 0.20 0.30

ÇÇ
D 2.00 BSC
D2 1.10 1.30
DETAIL B A E 2.00 BSC
0.10 C A1 E2 0.70 0.90
e 0.50 BSC
DETAIL B K 0.30 REF
ALTERNATE L 0.25 0.35
0.08 C CONSTRUCTIONS
L1 −−− 0.10
(A3)
NOTE 4 A1 SEATING
SIDE VIEW C PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
8X
D2 1.30 0.50
8X L
1 4 PACKAGE
OUTLINE

E2
0.90 2.30

K 8 5
8X b
e/2 1
0.10 C A B 8X
e 0.50
0.05 C NOTE 3 0.30
PITCH
BOTTOM VIEW DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the onsemi Soldering and Mounting
GENERIC Techniques Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
1
XXMG
G

XX = Specific Device Code

M = Date Code
G = Pb−Free Device
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON18658D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DFN8, 2.0X2.0, 0.5MM PITCH PAGE 1 OF 1

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