NCP1271

PWM Controller, Soft-Skip &

trade; Standby, with
Adjustable Skip Level and
External Latch
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The NCP1271 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The MARKING
controller allows for excellent stand by power consumption by use of DIAGRAMS
its adjustable Soft−Skip mode and integrated high voltage startup 8
FET. This proprietary Soft−Skip also dramatically reduces the risk of SOIC−7 1271x
acoustic noise. This allows the use of inexpensive transformers and D SUFFIX ALYWG
G
capacitors in the clamping network. Internal frequency jittering, ramp CASE 751U
1
compensation, timer−based fault detection and a latch input make
this controller an excellent candidate for converters where
ruggedness and component cost are the key constraints.
PDIP−7 VHVIC 1271Pxxx
Features P SUFFIX AWL
• Fixed−Frequency Current−Mode Operation with Ramp CASE 626B YYWWG
8
Compensation and Skip Cycle in Standby Condition 1
1
• Timer−Based Fault Protection for Improved Overload Detection
• “Soft−Skip Mode” Technique for Optimal Noise Control in Standby x = A or B
A= 65 kHz
• Internal High−Voltage Startup Current Source for Lossless Startup B= 100 kHz
• "5% Current Limit Accuracy over the Full Temperature Range xxx = Device Code: 65, 100
• Adjustable Skip Level A = Assembly Location
L, WL = Wafer Lot
• Internal Latch for Easy Implementation of Overvoltage and Y, YY = Year
Overtemperature Protection W, WW = Work Week
G or G = Pb−Free Package
• Frequency Jittering for Softened EMI Signature
(Note: Microdot may be in either location)
• +500 mA/−800 mA Peak Current Drive Capability
• Sub−100 mW Standby Power can be Achieved
• Pin−to−Pin Compatible with the Existing NCP120X Series
PIN CONNECTIONS
• This is a Pb−Free Device
1 8
Skip/latch HV
Typical Applications 2
FB
• AC−DC Adapters for Notebooks, LCD Monitors 3 6
CS VCC
• Offline Battery Chargers 4 5
Drv
GND
• Consumer Electronic Appliances STB, DVD, DVDR (Top View)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

September, 2009 − Rev. 6 NCP1271/D
 NCP1271

AC EMI Output
Input Filter Voltage

−
latch input*

skip/latch HV
FB
CS Vcc
*Optional Gnd Drv

NCP1271 R*ramp
Rskip

Figure 1. Typical Application Circuit

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 NCP1271

MAXIMUM RATINGS (Notes 1 and 2)

Rating Symbol Value Unit
VCC Pin (Pin 6)
Maximum Voltage Range Vmax −0.3 to +20 V
Maximum Current Imax 100 mA
Skip/Latch, FB, CS Pin (Pins 1−3)
Maximum Voltage Range Vmax −0.3 to +10 V
Maximum Current Imax 100 mA
Drv Pin (Pin 5)
Maximum Voltage Range Vmax −0.3 to +20 V
Maximum Current Imax −800 to +500 mA
HV Pin (Pin 8)
Maximum Voltage Range Vmax −0.3 to +500 V
Maximum Current Imax 100 mA
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction−to−Air, PDIP−7, Low Conductivity PCB (Note 3) RqJA 142 °C/W
Thermal Resistance, Junction−to−Lead, PDIP−7, Low Conductivity PCB RqJL 57 °C/W
Thermal Resistance, Junction−to−Air, PDIP−7, High Conductivity PCB (Note 4) RqJA 120 °C/W
Thermal Resistance, Junction−to−Lead, PDIP−7, High Conductivity PCB RqJL 56 °C/W
Thermal Resistance, Junction−to−Air, SO−7, Low Conductivity PCB (Note 3) RqJA 177 °C/W
Thermal Resistance, Junction−to−Lead, SO−7, Low Conductivity PCB RqJL 75 °C/W
Thermal Resistance, Junction−to−Air, SO−7, High Conductivity PCB (Note 4) RqJA 136 °C/W
Thermal Resistance, Junction−to−Lead, SO−7, High Conductivity PCB RqJL 69 °C/W
Operating Junction Temperature Range TJ −40 to +150 °C
Maximum Storage Temperature Range Tstg −60 to +150 °C
ESD Protection
Human Body Model ESD Pins 1−6 HBM 2000 V
Human Body Model ESD Pin 8 HBM 700 V
Machine Model ESD Pins 1−4, 8 MM 200 V
Machine Model ESD Pins 5, 6 MM 150 V
Charged Device Model ESD CDM 1000 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. ESD protection per JEDEC JESD22−A114−F for HBM, per JEDEC JESD22−A115−A for MM, and per JEDEC JESD22−C101D for CDM.
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
2. Guaranteed by design, not tested.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.

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 NCP1271

8V
I skip
Skip/ latch − latch−off, reset
13 us filter S when Vcc < 4V
1 + 8 HV
R Q
Rskip 10V V skip 4.1 mA when Vcc > 0.6 V
Vskip = Rskip * Iskip or 0.2 mA when Vcc < 0.6 V
Vskip = 1.2 V when pin 1 is opened skip
V FB + turn off
4.8 V −
2.85 V 12.6/
16.7k TLD disable
FB V FB soft−skip 5.8 V
− soft
2 + skip
−
S
Vss Soft start/ soft−skip +
75.3k (1V max) management Q R UVLO
1/3 4 ms/ 300 us soft
− start
10V + 130ms double
V FB / 3
delay & hiccup
0 1
short B2 9.1 V
circuit Counter
PWM − V CC
V PWM fault
CS V CS −
180 ns + 6
3 +
LEB &
10V 20V
R ramp 100uA
0 turn on internal bias
jittered ramp OR
R CS current source V CC
Drv
4 R Q 5
1 0 7.5% Jittering driver:
Gnd 65, 100 kHz S +500 mA
Oscillator Max duty / −800 mA
= 80%

Figure 2. Functional Block Diagram

PIN FUNCTION DESCRIPTION

Pin No. Symbol Function Description
1 Skip/latch Skip Adjust or A resistor to ground provides the adjustable standby skip level. Additionally, if this pin is
Latchoff pulled higher than 8.0 V (typical), the controller latches off the drive.

2 FB Feedback An optocoupler collector pulls this pin low during regulation. If this voltage is less than
the Skip pin voltage, then the driver is pulled low and Soft−Skip mode is activated. If this
pin is open (>3 V) for more than 130 ms, then the controller is placed in a fault mode.
3 CS Current Sense This pin senses the primary current for PWM regulation. The maximum primary current
is limited to 1.0 V / RCS where RCS is the current sense resistor. Additionally, a ramp
resistor Rramp between the current sense node and this pin sets the compensation ramp
for improved stability.
4 Gnd IC Ground −
5 Drv Driver Output The NCP1271’s powerful output is capable of driving the gates of large Qg MOSFETs.
6 VCC Supply Voltage This is the positive supply of the device. The operating range is between 10 V (min) and
20 V (max) with a UVLO start threshold 12.6 V (typ).

8 HV High Voltage This pin provides (1) Lossless startup sequence (2) Double hiccup fault mode (3)
Memory for latch−off shutdown and (4) Device protection if VCC is shorted to GND.

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 NCP1271

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C, VCC = 14 V,
HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit

OSCILLATOR
Oscillation Frequency (65 kHz Version, TJ = 25_C) 5 fosc 61.75 65 68.25 kHz
Oscillation Frequency (65 kHz Version, TJ = −40 to + 85_C) 58 65 69
Oscillation Frequency (65 kHz Version, TJ = −40 to + 125_C) 55 65 69
Oscillation Frequency (100 kHz Version, TJ = 25_C) 95 100 105
Oscillation Frequency (100 kHz Version, TJ = −40 to +85_C) 89 100 107
Oscillation Frequency (100 kHz Version, TJ = −40 to +125_C) 85 100 107
Oscillator Modulation Swing, in Percentage of fosc 5 − − "7.5 − %
Oscillator Modulation Swing Period 5 − − 6.0 − ms
Maximum Duty Cycle (VCS = 0 V, VFB = 2.0 V) 5 Dmax 75 80 85 %

GATE DRIVE
Gate Drive Resistance 5 W
Output High (VCC = 14 V, Drv = 300 W to Gnd) ROH 6.0 11 20
Output Low (VCC = 14 V, Drv = 1.0 V) ROL 2.0 6.0 12
Rise Time from 10% to 90% (Drv = 1.0 nF to Gnd) 5 tr − 30 − ns
Fall Time from 90% to 10% (Drv = 1.0 nF to Gnd) 5 tf − 20 − ns

CURRENT SENSE
Maximum Current Threshold 3 ILimit 0.95 1.0 1.05 V
Soft−Start Duration − tSS − 4.0 − ms
Soft−Skip Duration − tSK − 300 − ms
Leading Edge Blanking Duration 3 tLEB 100 180 330 ns
Propagation Delay (Drv =1.0 nF to Gnd) − − − 50 150 ns
Ramp Current Source Peak 3 Iramp(H) − 100 − mA
Ramp Current Source Valley 3 Iramp(L) − 0 − mA

SKIP
Default Standby Skip Threshold (Pin 1 = Open) 2 Vskip − 1.2 − V
Skip Current (Pin 1 = 0 V, TJ = 25_C) 1 Iskip 26 43 56 mA
Skip Level Reset (Note 5) 1 Vskip−reset 5.0 5.7 6.5 V
Transient Load Detection Level to Disable Soft−Skip Mode 2 VTLD 2.6 2.85 3.15 V

EXTERNAL LATCH
Latch Protection Threshold 1 Vlatch 7.1 8.0 8.7 V
Latch Threshold Margin (Vlatch−m = VCC(off) − Vlatch) 1 Vlatch−m 0.6 1.2 − V
Noise Filtering Duration 1 − − 13 − ms
Propagation Delay (Drv = 1.0 nF to Gnd) 1 Tlatch − 100 − ns

SHORT−CIRCUIT FAULT PROTECTION

Time for Validating Short−Circuit Fault Condition 2 tprotect − 130 − ms
5. Please refer to Figure 39 for detailed description.
6. Guaranteed by design.

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 NCP1271

ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C,
VCC = 14 V, HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit

STARTUP CURRENT SOURCE

High−Voltage Current Source
Inhibit Voltage (ICC = 200 mA, HV = 50 V) 6 Vinhibit 190 600 800 mV
Inhibit Current (VCC = 0 V, HV = 50 V) 6 Iinhibit 80 200 350 mA
Startup (VCC = VCC(on) − 0.2 V, HV = 50 V) 6 IHV 3.0 4.1 6.0 mA
Leakage (VCC = 14 V, HV = 500 V) 8 IHV−leak 10 25 50 mA

Minimum Startup Voltage (VCC = VCC(on) – 0.2 V, ICC = 0.5 mA) 8 VHV(min) − 20 28 V

SUPPLY SECTION
VCC Regulation 6
Startup Threshold, VCC Increasing VCC(on) 11.2 12.6 13.8 V
Minimum Operating Voltage After Turn−On VCC(off) 8.2 9.1 10 V
VCC Operating Hysteresis VCC(on) − VCC(off) 3.0 3.6 4.2 V
Undervoltage Lockout Threshold Voltage, VCC Decreasing VCC(latch) 5.0 5.8 6.5 V
Logic Reset Level (VCC(latch) –VCC(reset) > 1.0 V) (Note 7) VCC(reset) − 4.0 − V
VCC Supply Current 6
Operating (VCC = 14 V, 1.0 nF Load, VFB = 2.0 V, 65 kHz Version) ICC1 − 2.3 3.0 mA
Operating (VCC = 14 V, 1.0 nF Load, VFB = 2.0 V, 100 kHz Version) ICC1 − 3.1 3.5 mA
Output Stays Low (VCC = 14 V, VFB = 0 V) ICC2 − 1.3 2.0 mA
Latchoff Phase (VCC = 7.0 V, VFB = 2.0 V) ICC3 − 500 720 mA
7. Guaranteed by design.

TYPICAL CHARACTERISTICS

110 85
84
OSCILLATION FREQUENCY (kHz)

100 100 kHz

MAXIMUM DUTY CYCLE (%)

83
82
90
81
80 80
79
70 78
65 kHz
77
60
76
50 75
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 3. Oscillation Frequency vs. Figure 4. Maximum Duty Cycle vs.
Temperature Temperature

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 NCP1271

TYPICAL CHARACTERISTICS

16 1.04
OUTPUT GATE DRIVE RESISTANCE (W)

14
ROH 1.02
12

CURRENT LIMIT (V)

10 1.0
8
0.98
6
ROL
4
0.96
2

0 0.94
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 5. Output Gate Drive Resistance vs. Figure 6. Current Limit vs. Temperature
Temperature
8 350

7 LEADING EDGE BLANKING TIME (ns)

300
SOFT−START DURATION (ms)

6
250
5
200
4
150
3
100
2

1 50

0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 7. Soft−Start Duration vs. Temperature Figure 8. Leading Edge Blanking Time vs.
Temperature

1.40 45
44
43
DEFAULT SKIP LEVEL (V)

SKIP PIN CURRENT (mA)

1.30
42
41
1.20 40
39
38
1.10
37
36
1.00 35
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. Default Skip Level vs. Temperature Figure 10. Skip Pin Current vs. Temperature

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 NCP1271

TYPICAL CHARACTERISTICS

6.0 3.0

TRANSIENT LOAD DETECT LEVEL (V)

SKIP LEVEL RESET THRESHOLD (V)

5.9 2.9

5.8 2.8

5.7 2.7

5.6 2.6

5.5 2.5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Skip Level Reset Threshold vs. Figure 12. Transient Load Detection Level vs.
Temperature Temperature

8.5 150
8.4 145
LATCH PROTECTION LEVEL (V)

FAULT VALIDATION TIME (ms)

8.3 140
8.2 135
8.1 130
8.0 125
7.9 120
7.8 115
7.7 110
7.6 105
7.5 100
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 13. Latch Protection Level vs. Figure 14. Fault Validation Time vs.
Temperature Temperature

1.0 300
0.9 VCC = 0 V
STARTUP INHIBIT CURRENT (mA)
STARTUP INHIBIT VOLTAGE (V)

250
0.8
0.7
200
0.6
0.5 150
0.4
0.3 100

0.2
50
0.1
0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 15. Startup Inhibit Voltage vs. Figure 16. Startup Inhibit Current vs.
Temperature Temperature

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 NCP1271

TYPICAL CHARACTERISTICS

4.5 6
VCC = VCC(on) − 0.2 V
4.4
5
STARTUP CURRENT (mA)

4.3

STARTUP CURRENT (mA)

125°C
4.2
4
4.1 −40°C
25°C
4.0 3
3.9
2
3.8
3.7
1
3.6
3.5 0
−50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12
TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)
Figure 17. High Voltage Startup Current vs. Figure 18. Startup Current vs. VCC Voltage
Temperature

40 25
STARTUP LEAKAGE CURRENT (mA)

24
MINIMUM STARTUP VOLTAGE (V)
35
23
30
22
25
21
20 20
19
15
18
10
17
5
16
0 15
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 19. Startup Leakage Current vs. Figure 20. Minimum Startup Voltage vs.
Temperature Temperature

14 3.5
VCC(on)
SUPPLY VOLTAGE THRESHOLD (V)

ICC1 (100 kHz)

12 3.0
SUPPLY CURRENT (mA)

10 VCC(off) 2.5
ICC1 (65 kHz)
8 2.0
VCC(latch)
6 1.5 ICC2
VCC(reset)
4 1.0
ICC3
2 0.5

0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 21. Supply Voltage Thresholds vs. Figure 22. Supply Currents vs. Temperature
Temperature

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 NCP1271

OPERATING DESCRIPTION
Introduction • Current−Mode Operation: The NCP1271 uses
The NCP1271 represents a new generation of the current−mode control which provides better transient
fixed−frequency PWM current−mode flyback controllers response than voltage−mode control. Current−mode
from ON Semiconductor. The device features integrated control also inherently limits the cycle−by−cycle
high−voltage startup and excellent standby performance. primary current.
The proprietary Soft−Skip Mode achieves extremely • Compensation Ramp: A drawback of current−mode
low−standby power consumption while keeping power regulation is that the circuit may become unstable
supply acoustic noise to a minimum. The key features of
when the operating duty cycle is too high. The
the NCP1271 are as follows:
NCP1271 offers an adjustable compensation ramp to
• Timer−Based Fault Detection: In the event that an solve this instability.
abnormally large load is applied to the output for more • 80% Maximum Duty Cycle Protection: This feature
than 130 ms, the controller will safely shut the
limits the maximum on time of the drive to protect the
application down. This allows accurate overload (OL)
power MOSFET from being continuously on.
or short−circuit (SC) detection which is not dependent
on the auxiliary winding.
• Frequency Jittering: Frequency jittering softens the
EMI signature by spreading out peak energy within a
• Soft−Skip Mode: This proprietary feature of the band +/− 7.5% from the center frequency.
NCP1271 minimizes the standby low−frequency
acoustic noise by ramping the peak current envelope
• Switching Frequency Options: The NCP1271 is
whenever skip is activated. available in either 65 kHz or 100 kHz fixed frequency
options. Depending on the application, the designer
• Adjustable Skip Threshold: This feature allows the can pick the right device to help reduce magnetic
power level at which the application enters skip to be
switching loss or improve the EMI signature before
fully adjusted. Thus, the standby power for various
reaching the 150 kHz starting point for more
applications can be optimized. The default skip level
restrictive EMI test limits.
is 1.2 V (40% of the maximum peak current).
• 500 V High−Voltage Startup Capability: This NCP1271 Operating Conditions
AC−DC application friendly feature eliminates the There are 5 possible operating conditions for the NCP1271:
need for an external startup biasing circuit, minimizes 1. Normal Operation – When VCC is above VCC(off)
the standby power loss, and saves printed circuit board (9.1 V typical) and the feedback pin voltage (VFB)
(PCB) space. is within the normal operation range (i.e.,VFB < 3.0
• Dual High−Voltage Startup−Current Levels: The V), the NCP1271 operates as a fixed−frequency
NCP1271 uniquely provides the ability to reduce the current−mode PWM controller.
startup current supply when Vcc is low. This prevents 2. Standby Operation (or Skip−Cycle Operation)
damage if Vcc is ever shorted to ground. After Vcc When the load current drops, the compensation
rises above approximately 600 mV, the startup current network responds by reducing the primary peak
increases to its full value and rapidly charges the Vcc current. When the peak current reaches the skip
capacitor. peak current level, the NCP1271 enters Soft−Skip
operation to reduce the power consumption. This
• Latched Protection: The NCP1271 provides a pin,
Soft−Skip feature offers a modified peak current
which if pulled high, places the part in a latched off
envelope and hence also reduces the risk of audible
mode. Therefore, overvoltage (OVP) and
noise. In the event of a sudden load increase, the
overtemperature (OTP) protection can be easily
transient load detector (TLD) disables Soft−Skip
implemented. A noise filter is provided on this function
and applies maximum power to bring the output
to reduce the chances of falsely triggering the latch. The
into regulation as fast as possible.
latch is released when Vcc is cycled below 4 V.
3. Fault Operation – When no feedback signal is
• Non−Latched Protection/ Shutdown Option: By received for 130 ms or when VCC drops below
pulling the feedback pin below the skip threshold VCC(off) (9.1 V typical), the NCP1271 recognizes it
level, a non−latching shutdown mode can be easily as a fault condition. In this fault mode, the Vcc
implemented. voltage is forced to go through two cycles of slowly
• 4.0 ms Soft−Start: The soft start feature slowly ramps discharging and charging. This is known as a
up the drive duty cycle at startup. This forces the “double hiccup.” The double hiccup insures that
primary current to also ramp up slowly and ample time is allowed between restarts to prevent
dramatically reduces the stress on power components overheating of the power devices. If the fault is
during startup.

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 NCP1271

cleared after the double hiccup, then the application Startup current
restarts. If not, then the process is repeated.
4. Latched Shutdown – When the Skip/latch pin (Pin
4.1 mA
1) voltage is pulled above 8.0 V for more than
13 ms, the NCP1271 goes into latchoff shutdown.
The output is held low and VCC stays in hiccup
mode until the latch is reset. The reset can only
occur if Vcc is allowed to fall below VCC(reset)
(4.0 V typical). This is generally accomplished by 200 uA
unplugging the main input AC source.
0.6 V VCC(latch) VCC(on) VCC
5. Non−Latched Shutdown – If the FB pin is pulled
below the skip level, then the device will enter a Figure 23. Startup Current at Various VCC Levels
non−latched shutdown mode. This mode disables
the driver, but the controller automatically recovers VCC Double Hiccup Mode
when the pulldown on FB is released. Alternatively, Figure 24 illustrates the block diagram of the startup
Vcc can also be pulled low (below 190 mV) to circuit. An undervoltage lockout (UVLO) comparator
shutdown the controller. This has the added benefit monitors the VCC supply voltage. If VCC falls below
of placing the part into a low current consumption VCC(off), then the controller enters “double hiccup mode.”
mode for improved power savings.
Vbulk
Biasing the Controller
During startup, the Vcc bias voltage is supplied by the HV
HV Pin (Pin 8). This pin is capable of supporting up to 4.1 mA when Vcc > 0.6 V 8
500 V, so it can be connected directly to the bulk capacitor. 200 uA when Vcc < 0.6 V

10−to−20V biasing voltage

Internally, the pin connects to a current source which

(available after startup)

turn off
rapidly charges VCC to its VCC(on) threshold. After this
level is reached, the controller turns on and the transformer UVLO
auxiliary winding delivers the bias supply voltage to VCC. +
Q S −
The startup FET is then turned off, allowing the standby
R
power loss to be minimized. This in−chip startup circuit 12.6/
minimizes the number of external components and Printed 5.8 V
double
Circuit Board (PCB) area. It also provides much lower
hiccup
power dissipation and faster startup times when compared
B2 9.1 V
to using startup resistors to VCC. The auxiliary winding
Counter
needs to be designed to supply a voltage above the VCC(off) Vcc
−
level but below the maximum VCC level of 20 V. + 6
For added protection, the NCP1271 also include a dual &
startup mode. Initially, when VCC is below the inhibit 20V
voltage Vinhibit (600 mV typical), the startup current source
is small (200 uA typical). The current goes higher (4.1 mA turn on internal bias
typical) when VCC goes above Vinhibit. This behavior is Figure 24. VCC Management
illustrated in Figure 23. The dual startup feature protects During double hiccup operation, the Vcc level falls to
the device by limiting the maximum power dissipation VCC(latch) (5.8 V typical). At this point, the startup FET is
when the VCC pin (Pin 6) is accidentally grounded. This turned back on and charges VCC to VCC(on) (12.6 V typical).
slightly increases the total time to charge VCC, but it is VCC then slowly collapses back to the VCC(latch) level. This
generally not noticeable. cycle is repeated twice to minimize power dissipation in

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 NCP1271

external components during a fault event. After the second

cycle, the controller tries to restart the application. If the
Vout
restart is not successful, then the process is repeated.
During this mode, VCC never drops below the 4 V latch
12.6 V VCC
reset level. Therefore, latched faults will not be cleared
9.1 V
unless the application is unplugged from the AC line (i.e.,
Vbulk discharges). t startup
Figure 25 shows a timing diagram of the VCC double 0.6 V
hiccup operation. Note that at each restart attempt, a soft time
start is issued to minimize stress. Output waveforms with a large enough VCC capacitor

Desired level of Vout

Supply voltage, VCC

12.6 V 12.6 V VCC

9.1 V 9.1 V

5.8 V Vout
0.6 V
5.8 V time
time Output waveforms with too small of a VCC capacitor

Drain current, ID t startup Figure 26. Different Startup Scenarios of the

Circuits with Different VCC Capacitors
time
It is highly recommended that the VCC capacitor be as
Switching is missing in
close as possible to the VCC and ground pins of the product
every two VCC hiccup cycles to reduce switching noise. A small bypass capacitor on this
featuring a “double−hiccup” pin is also recommended. If the switching noise is large
Figure 25. VCC Double Hiccup Operation in a Fault enough, it could potentially cause VCC to go below VCC(off)
Condition and force a restart of the controller.
It is also recommended to have a margin between the
VCC Capacitor winding bias voltage and VCC(off) so that all possible
As stated earlier, the NCP1271 enters a fault condition transient swings of the auxiliary winding are allowed. In
when the feedback pin is open (i.e. FB is greater than 3 V) standby mode, the VCC voltage swing can be higher due to
for 130 ms or VCC drops below VCC(off) (9.1 V typical). the low−frequency skip−cycle operation. The VCC
Therefore, to take advantage of these features, the VCC capacitor also affects this swing. Figure 27 illustrates the
capacitor needs to be sized so that operation can be possible swings.
maintained in the absence of the auxiliary winding for at
least 130 ms. Supply voltage, VCC
The controller typically consumes 2.3 mA at a 65 kHz
frequency with a 1 nF switch gate capacitance. Therefore,
to ensure at least 130 ms of operation, equation 1 can be
9.1 V
used to calculate that at least an 85 mF capacitor would be
necessary. time
C DV 85 mF · (12.6 V−9.1 V)
tstartup + VCC + + 130 ms Feedback pin voltage, VFB
ICC1 2.3 mA
(eq. 1)
If the 130 ms timer feature will not be used, then the Vskip
capacitance value needs to at least be large enough for the
output to charge up to a point where the auxiliary winding
can supply VCC. Figure 26 describes different startup time
scenarios with different VCC capacitor values. If the VCC Drain current, ID
cap is too small, the application fails to start because the
bias supply voltage cannot be established before VCC is
reduced to the VCC(off) level. time

Figure 27. Timing Diagram of Standby Condition

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12
 NCP1271

Soft−Start Operation Current−Mode Pulse−Width Modulation

Figures 28 and 29 show how the soft−start feature is The NCP1271 uses a current−mode fixed−frequency
included in the pulse−width modulation (PWM) PWM with internal ramp compensation. A pair of current
comparator. When the NCP1271 starts up, a soft−start sense resistors RCS and Rramp sense the flyback drain
voltage VSS begins at 0 V. VSS increases gradually from 0 V current ID. As the drain current ramps up through the
to 1.0 V in 4.0 ms and stays at 1.0 V afterward. This voltage inductor and current sense resistor, a corresponding voltage
VSS is compared with the divided−by−3 feedback pin ramp is placed on the CS pin (pin 3). This voltage ranges
voltage (VFB/3). The lesser of VSS and (VFB/3) becomes the from very low to as high as the modulation voltage VPWM
modulation voltage VPWM in the PWM duty cycle (maximum of 1.0 V) before turning the drive off. If the
generation. Initially, (VFB/3) is above 1.0 V because the internal current ramp is ignored (i.e., Rramp ≈ 0) then the
output voltage is low. As a result, VPWM is limited by the maximum possible drain current ID(max) is shown in
soft start function and slowly ramps up the duty cycle (and Equation 2. This sets the primary current limit on a cycle
therefore the primary current) for the initial 4.0 ms. This by cycle basis.
provides a greatly reduced stress on the power devices 1V
during startup. ID(max) + (eq. 2)
RCS

V SS − Vbulk
VFB/ 3 +

0 1
I ramp

VPWM VCS
180ns
PWM
+
Figure 28. VPWM is the lesser of VSS and (VFB/3) Q R − LEB
Output S CS Rramp I D
80% VPWM
Soft−start voltage, VSS max duty 3
(1V max. signal)
Clock 1 0
RCS
1V

Figure 30. Current−Mode Implementation

time
4 ms
PWM
Feedback pin voltage divided−by−3, VFB/3 Output

1V VPWM

VCS
time must be less than130 ms time
to prevent fault condition

Pulse Width Modulation voltage, VPWM clock

1V Figure 31. Current−Mode Timing Diagram

The timing diagram of the PWM is in Figure 31. An
internal clock turns the Drive Output (Pin 5) high in each
time switching cycle. The Drive Output goes low when the CS
4 ms (Pin 3) voltage VCS intersects with the modulation voltage
Drain Current, ID VPWM. This generates the pulse width (or duty cycle). The
maximum duty cycle is limited to 80% (typically) in the
output RS latch.

time
4 ms

Figure 29. Soft−Start (Time = 0 at VCC = VCC(on))

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 NCP1271

Ramp Compensation 43 mVńms

Rramp + + 5.3 kW (eq. 4)
Ramp compensation is a known mean to cure 8.1 mAńms
subharmonic oscillations. These oscillations take place at It is recommended that the value of Rramp be limited to
half the switching frequency and occur only during less then 10 kW. Values larger than this will begin to limit
continuous conduction mode (CCM) with a duty−cycle the effective duty cycle of the controller and may result in
greater than 50%. To lower the current loop gain, one reduced transient response.
usually injects between 50 and 75% of the inductor down
slope. The NCP1271 generates an internal current ramp Frequency Jittering
that is synchronized with the clock. This current ramp is Frequency jittering is a method used to soften the EMI
then routed to the CS pin. Figures 32 and 33 depict how the signature by spreading the energy in the vicinity of the main
ramp is generated and utilized. Ramp compensation is switching component. The NCP1271 switching frequency
simply formed by placing a resistor, Rramp, between the CS ranges from +7.5% to −7.5% of the switching frequency in
pin and the sense resistor. a linear ramp with a typical period of 6 ms. Figure 34
demonstrates how the oscillation frequency changes.
Ramp current, Iramp
Oscillator Frequency
100uA

107.5 kHz

time 100 kHz

0
80% of period 92.5 kHz
100% of period 6 ms

Figure 32. Internal Ramp Current Source time

Figure 34. Frequency Jittering

(The values are for the 100 kHz frequency option)

DRIVE Fault Detection

Figure 35 details the timer−based fault detection
circuitry. When an overload (or short circuit) event occurs,
Clock 100 mA Peak the output voltage collapses and the optocoupler does not
Current
conduct current. This opens the FB pin (pin 2) and VFB is
CS Rramp internally pulled higher than 3.0 V. Since (VFB/3) is greater
Ramp
than 1 V, the controller activates an error flag and starts a
Oscillator
Rsense
130 ms timer. If the output recovers during this time, the
timer is reset and the device continues to operate normally.
However, if the fault lasts for more than 130 ms, then the
Figure 33. Inserting a Resistor in Series with the
driver turns off and the device enters the VCC Double
Current Sense Information brings Ramp Compensation Hiccup mode discussed earlier. At the end of the double
For the NCP1271, the current ramp features a swing of hiccup, the controller tries to restart the application.
100 mA. Over a 65 kHz frequency with an 80% max duty
4.8V
cycle, that corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance
(Lp) is 350 mH, the SMPS output is 19 V, the Vf of the V FB
output diode is 1 V and the Np:Ns ratio is 10:1. The OFF FB 2
time primary current slope is given by:
V FB
Np
(Vout ) Vf) @ Ns 3 Fault
+ 571 VńmH + 571 mAńms (eq. 3) + 130ms disable Drv
Lp V SS − delay &
When projected over an Rsense of 0.1 W (for example), Softstart
this becomes or 57 mV/ms. If we select 75% of the 1V max
downslope as the required amount of ramp compensation,
then we shall inject 43 mV/ms. Therefore, Rramp is simply Figure 35. Block Diagram of Timer−Based Fault
Detection
equal to:

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 NCP1271

Besides the timer−based fault detection, the NCP1271 Skip Duty Cycle
also enters fault condition when VCC drops below VCC(off) Skip peak current, %Icsskip, is the percentage of the
(9.1 V typical). The device will again enter a double hiccup maximum peak current at which the controller enters skip
mode and try to restart the application. mode. Icsskip can be any value from 0 to 100% as defined
by equation 5. However, the higher that %Icsskip is, the
Operation in Standby Condition greater the drain current when skip is entered. This
During standby operation, or when the output has a light increases the risk of acoustic noise. Conversely, the lower
load, the duty cycle on the controller can become very that %Icsskip is the larger the percentage of energy is
small. At this point, a significant portion of the power expended turning the switch on and off. Therefore it is
dissipation is related to the power MOSFET switching on important to adjust %Icsskip to the optimal level for a given
and off. To reduce this power dissipation, the NCP1271 application.
“skips” pulses when the FB level (i.e. duty cycle) drops too
Vskip
low. The level that this occurs at is completely adjustable % Icsskip + · 100% (eq. 5)
by setting a resistor on pin 1. 3V
By discontinuing pulses, the output voltage slowly drops
and the FB voltage rises. When the FB voltage rises above Skip Adjustment
the Vskip level, the drive is turned back on. However, to By default, when the Skip/latch Pin (Pin 1) is opened, the
minimize the risk of acoustic noise, when the drive turns skip level is 1.2 V (Vskip = 1.2 V). This corresponds to a
back on the duty cycle of its pulses are also ramped up. This 40% Icsskip (%Icsskip = 1.2 V / 3.0 V 100% = 40%).
Therefore, the controller will enter skip mode when the
is similar to the soft start function, except the period of the
Soft−Skip operation is only 300 ms instead of 4.0 ms for the peak current is less than 40% of the maximum peak current.
soft start function. This feature produces a timing diagram However, this level can be externally adjusted by placing
shown in Figure 36. a resistor Rskip between skip/latch pin (Pin 1) and Ground
(Pin 4). The level will change according to equation 6.
Vskip Vskip + Rskip Iskip (eq. 6)
To operate in skip cycle mode, Vskip must be between
FB Soft Skip 0 V and 3.0 V. Therefore, Rskip must be within the levels
given in Table 1.
ID

Figure 36. Soft−Skip Operation

Table 1. Skip Resistor Rskip Range for Dmax = 80% and Iskip = 43 mA
%Icsskip Vskip or Vpin1 Rskip Comment
0% 0V 0W Never skips.
12% 0.375 V 8.7 kW −
25% 0.75 V 17.4 kW −
40% 1.2 V 28 kW −
50% 1.5 V 34.8 kW −
100% 3.0 V 70 kW Always skips.

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 NCP1271

Recover from Standby to be opened. The skip level Vskip is restored to

In the event that a large load is encountered during skip the default 1.2 V.
cycle operation, the circuit automatically disables the 3. When the voltage is between about 3.0 V and
normal Soft−Skip procedure and delivers maximum power Vskip−reset, the Vskip level is above the normal
to the load (Figure 37). This feature, the Transient Load operating range of the feedback pin. Therefore,
Detector (TLD), is initiated anytime a skip event is exited the output does not switch.
and the FB pin is greater than 2.85 V, as would be the case 4. When the voltage is between 0 V and 3.0 V, the
for a sudden increase in output load. Vskip is within the operating range of the
feedback pin. Then the voltage on this pin sets
output voltage
the skip level as explained earlier.
300 ms max

V pin1

load current 10 V (max limit)

Output is latched off here.
V TLD 8V (Vlatch )
Maximum current available Pin 1 considered to be opened.
when TLD level is hit
Vskip Vskip is reset to default level 1.2 V.
V FB
5.7 V (Vskip−reset )

ID Output always low (skipped) here.

3.0 V (always skip)
Figure 37. Transient Response from Standby
Adjustable Vskip range.
External Latchoff Shutdown
When the Skip/Latch input (Pin 1) is pulled higher than 0 V (no skip)
Vlatch (8.0 V typical), the drive output is latched off until
VCC drops below VCC(reset) (4.0 Vtypical). If Vbulk stays Figure 39. NCP1271 Pin 1 Operating Regions
above approximately 30 Vdc, then the HV FET ensure that The external latch feature allows the circuit designers to
VCC remains above VCC(latch) (5.8 Vtypical). Therefore, the implement different kinds of latching protection. The
controller is reset by unplugging the power supply from the NCP1271 applications note (AND8242/D) details several
wall and allowing Vbulk to discharge. Figure 38 illustrates simple circuits to implement overtemperature protection
the timing diagram of VCC in the latchoff condition. (OTP) and overvoltage protection (OVP).
In order to prevent unexpected latchoff due to noise,
Startup current source is Startup current source is
charging the VCC capacitor off when VCC is 12.6 V it is very important to put a noise decoupling capacitor
near Pin 1 to increase the noise immunity. It is also
12.6 V
recommended to always have a resistor from pin 1 to GND.
This further reduces the risk of premature latchoff. Also
note that if the additional latch−off circuitry has leakage,
it will modify the skip adjust setup.

External Non−Latched Shutdown

Figure 40 illustrates the Feedback (pin 2) operation. An
5.8 V
external non−latched shutdown can be easily implemented
Startup current source turns by simply pulling FB below the skip level. This is an
on when VCC reaches 5.8 VCC
inherent feature from the standby skip operation. Hence, it
Figure 38. Latchoff VCC Timing Diagram allows the designer to implement additional non−latched
Figure 39 defines the different voltage regions of the shutdown protection.
Skip/latch Pin (Pin 1) operation. The device can also be shutdown by pulling the VCC pin
1. When the voltage is above Vlatch (7.1 V min, to GND (<190 mV). In addition to shutting off the output,
8.7 V max), the circuit is in latchoff and all drive this method also places the part into a low current
pulses are disabled until VCC cycles below 4.0 V consumption state.
(typical).
2. When the voltage is between Vskip−reset (5.0 V
min, 6.5 V max) and Vlatch, the pin is considered

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 NCP1271

V FB time of 30 ns and 20 ns with a 1.0 nF load. This allows the

NCP1271 to drive a high−current power MOSFET directly
Fault operation when staying
for medium−high power application.
in this region longer than 130 ms
3V Noise Decoupling Capacitors
There are three pins in the NCP1271 that may need
PWM operation
external decoupling capacitors.
V skip 1. Skip/Latch Pin (Pin 1) – If the voltage on
Non−latched shutdown
this pin is above 8.0 V, then the circuit enters
0V
latchoff. Hence, a decoupling capacitor on this
pin is essential for improved noise immunity.
Figure 40. NCP1271 Operation Threshold
Additionally, a resistor should always be placed
from this pin to GND to prevent noise from
1 8 causing the pin 1 level to exceed the latchoff
2 level.
3 6 2. Feedback Pin (Pin 2) – The FB pin is a high
OFF
4 5 impedance point and is very easily polluted in a
NCP1271 noisy environment. This could effect the circuit
opto operation.
coupler
3. VCC Pin (Pin 6) – The circuit maintains normal
operation when VCC is above VCC(off) (9.1 V
Figure 41. Non−Latchoff Shutdown
typical). But, if VCC drops below VCC(off) because
of switching noise, then the circuit can incorrectly
Output Drive recognize it as a fault condition. Hence, it is
The output stage of the device is designed to directly important to locate the VCC capacitor or an
drive a power MOSFET. It is capable of up to +500 mA and additional decoupling capacitor as close as possible
−800 mA peak drive currents and has a typical rise and fall to the device.

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 NCP1271

Fuse 2A D1 − D4
1N5406 x 4 C5 10 nF
+

Mode Choke

R1 100k / 2W
C3 82uF / 400V

D5 MMSZ914
C2 0.1 uF

C10 2200 uF
C1 0.1 uF

C9 2200 uF
Common
85 to 19 V / 3 A

D6 MRA4005T3
265 Vac
−
T1
E3506−A D8 MBR3100
D7 MURS160
IC1 NCP1271A

IC3 SFH615AA−X007
Q1 SPP06N80C3

R9 1.69k
R2 10

R11 15.8k
R6 10
C6 1.2 nF

R10 1.69k
R5 30.1k

C7 1.2 nF

C13 100uF
C4 100uF R7 511 C12
R8 0.15 uF
0.25 / 1W

R12 2.37k
D10 MZP4746A (18V)
IC4 TL431

Flyback transformer :
Cooper CTX22−17179
C11 1nF/ 1000V
Lp = 180uH, leakage 2.5uH max
np : ns : naux = 30 : 6 : 5
Hi−pot 3600Vac for 1 sec, primary to secondary
Hi−pot 8500Vac for 1 sec, winding to core

Figure 42. 57 W Example Circuit Using NCP1271

Figure 42 shows a typical application circuit using the circuit are described in application note AND8242/D. The
NCP1271. The standby power consumption of the circuit efficiency of the circuit at light load up to full load is shown
is 83 mW with 230 Vac input. The details of the application in Figure 43.

95

90 120 Vac

85
EFFICIENCY (%)

230 Vac
80

75

70

65

60
0 10 20 30 40 50 60
Pout (W)
Figure 43. Efficiency of the NCP1271 Demo
Board at Nominal Line Voltages

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18
 NCP1271

ORDERING INFORMATION
Device Frequency Package Shipping†
NCP1271D65R2G 65 kHz SOIC−7 2500 / Tape & Reel
(Pb−Free)
NCP1271D100R2G 100 kHz SOIC−7 2500 / Tape & Reel
(Pb−Free)
NCP1271P65G 65 kHz PDIP−7 50 Units / Rail
(Pb−Free)
NCP1271P100G 100 kHz PDIP−7 50 Units / Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).

The product described herein (NCP1271), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221, 6,633,193. There may
be other patents pending.

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19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−7 (PDIP−8 LESS PIN 7)

CASE 626B
ISSUE D
DATE 22 APR 2015
SCALE 1:1
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN XXXXXXXXX
4. AC IN
5. GROUND
AWL
6. OUTPUT YYWWG
7. NOT USED
8. VCC

XXXX = Specific Device Code

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON12198D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−7 (PDIP−8 LESS PIN 7) PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−7
CASE 751U−01
ISSUE E
SCALE 1:1 DATE 20 OCT 2009

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
8 5 3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
−B− S 0.25 (0.010) M B M 4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
1 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
4 PER SIDE.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C R X 45 _ C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
J H 0.10 0.25 0.004 0.010
−T− SEATING J 0.19 0.25 0.007 0.010
PLANE K 0.40 1.27 0.016 0.050
K M 0_ 8_ 0_ 8_
H M
D 7 PL N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M T B S A S

GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
XXXXX
1.52 ALYWX
0.060 G
1

XXX = Specific Device Code

7.0 4.0 A = Assembly Location
0.275 0.155 L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
0.6 1.270 Pb−Free indicator, “G” or microdot “ G”,
0.024 0.050 may or may not be present.

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON12199D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: 7−LEAD SOIC PAGE 1 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009

STYLE 1: STYLE 2: STYLE 3:

PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2
5. EMITTER 5. BASE, #2 5. GATE, #2
6. 6. EMITTER, #2 6. SOURCE, #2
7. NOT USED 7. NOT USED 7. NOT USED
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1

STYLE 4: STYLE 5: STYLE 6:

PIN 1. ANODE PIN 1. DRAIN PIN 1. SOURCE
2. ANODE 2. DRAIN 2. DRAIN
3. ANODE 3. DRAIN 3. DRAIN
4. ANODE 4. DRAIN 4. SOURCE
5. ANODE 5. 5. SOURCE
6. ANODE 6. 6.
7. NOT USED 7. NOT USED 7. NOT USED
8. COMMON CATHODE 8. SOURCE 8. SOURCE

STYLE 7: STYLE 8: STYLE 9:

PIN 1. INPUT PIN 1. COLLECTOR (DIE 1) PIN 1. EMITTER (COMMON)
2. EXTERNAL BYPASS 2. BASE (DIE 1) 2. COLLECTOR (DIE 1)
3. THIRD STAGE SOURCE 3. BASE (DIE 2) 3. COLLECTOR (DIE 2)
4. GROUND 4. COLLECTOR (DIE 2) 4. EMITTER (COMMON)
5. DRAIN 5. COLLECTOR (DIE 2) 5. EMITTER (COMMON)
6. GATE 3 6. EMITTER (DIE 2) 6. BASE (DIE 2)
7. NOT USED 7. NOT USED 7. NOT USED
8. FIRST STAGE Vd 8. COLLECTOR (DIE 1) 8. EMITTER (COMMON)

STYLE 10: STYLE 11:

PIN 1. GROUND PIN 1. SOURCE (DIE 1)
2. BIAS 1 2. GATE (DIE 1)
3. OUTPUT 3. SOURCE (DIE 2)
4. GROUND 4. GATE (DIE 2)
5. GROUND 5. DRAIN (DIE 2)
6. BIAS 2 6. DRAIN (DIE 2)
7. NOT USED 7. NOT USED
8. GROUND 8. DRAIN (DIE 1)

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON12199D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: 7−LEAD SOIC PAGE 2 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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