DATA SHEET

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Single Supply 3.0 V to 44 V SOIC−8

Operational Amplifiers 8 D SUFFIX
CASE 751
1

MC34071,2,4,A
MC33071,2,4,A, WQFN10
MT SUFFIX
NCV33072,4,A CASE 510AJ

Quality bipolar fabrication with innovative design concepts are

employed for the MC33071/72/74, MC34071/72/74, NCV33072/74A SOIC−14
series of monolithic operational amplifiers. This series of operational 14 D SUFFIX
CASE 751A
amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/ms slew rate 1
and fast settling time without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common TSSOP−14
mode input voltage range includes ground potential (VEE). With a 14 DTB SUFFIX
CASE 948G
Darlington input stage, this series exhibits high input resistance, low 1
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output ORDERING INFORMATION
voltage swing, provides high capacitance drive capability, excellent See detailed ordering and shipping information on page 18 of
this data sheet.
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74, NCV33072/74,A series of DEVICE MARKING INFORMATION
devices are available in standard or prime performance (A Suffix) See general marking information in the device marking
grades and are specified over the commercial, industrial/vehicular or section on page 19 of this data sheet.

military temperature ranges. The complete series of single, dual and

quad operational amplifiers are available in plastic SOIC, QFN and
TSSOP surface mount packages.

Features
• Wide Bandwidth: 4.5 MHz
• High Slew Rate: 13 V/ms
• Fast Settling Time: 1.1 ms to 0.1%
• Wide Single Supply Operation: 3.0 V to 44 V
• Wide Input Common Mode Voltage Range: Includes Ground (VEE)
• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
• Large Output Voltage Swing: −14.7 V to +14 V (with ±15 V
Supplies)
• Large Capacitance Drive Capability: 0 pF to 10,000 pF
• Low Total Harmonic Distortion: 0.02%
• Excellent Phase Margin: 60°
• Excellent Gain Margin: 12 dB
• Output Short Circuit Protection
• ESD Diodes/Clamps Provide Input Protection for Dual and Quad
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

October, 2021 − Rev. 24 MC34071/D
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

PIN CONNECTIONS

CASE 751 CASE 751A/CASE 948G CASE 510AJ

VCC
Offset Null 1 8 NC Output 1 1 14 Output 4 10
2 - 7 VCC 13
2 1 4 Output 1 1 9 Output 2
Inputs Inputs 1 - -
Inputs 4
3 + 6 Output + +
3 12
NC 2 8 NC
VEE 4 5 Offset Null
VCC 4 11 VEE
3 7 In ­ 2
(Single, Top View) In ­ 1
5 3
+ 2 + 10
Inputs 2 - - Inputs 3 In + 1 4
­

6 In + 2
Output 1 1 8 VCC 6 9
5
2 7 Output 2
- Output 2 7 8 Output 3
Inputs 1 3
+
6 VEE/GND
-
+ Inputs 2 (Quad, Top View)
VEE 4 5 (Top View)
(Dual, Top View)

VCC
Q3 Q4 Q5 Q6 Q7
Q1
Q17
Q2
R1 C1 R2
D2 Q18
Bias R6 R7
Q8 Q9 Q10 Q11
- Output
Inputs R8
+ C2 D3
Q19

Base Q13 Q14 Q15 Q16

Current
Cancellation Q12
Current
D1 Limit
R5

R3 R4

VEE/GND
Offset Null
(MC33071, MC34071 only)
Figure 1. Representative Schematic Diagram
(Each Amplifier)

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (from VEE to VCC) VS +44 V
Input Differential Voltage Range VIDR (Note 1) V
Input Voltage Range VIR (Note 1) V
Output Short Circuit Duration (Note 2) tSC Indefinite Sec
Operating Junction Temperature TJ +150 °C
Storage Temperature Range Tstg −60 to +150 °C
ESD Capability, Dual and Quad (Note 3) V
Human Body Model ESDHBM 2000
Machine Model ESDMM 200
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Either or both input voltages should not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115)

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground, unless otherwise noted. See Note 4 for
TA = Tlow to Thigh)
A Suffix Non−Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS = 100 W, VCM = 0 V, VO = 0 V) VIO mV
− −
VCC = +15 V, VEE = −15 V, TA = +25°C − 0.5 3.0 − 1.0 5.0
VCC = +5.0 V, VEE = 0 V, TA = +25°C − 0.5 3.0 − 1.5 5.0
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh − 5.0 − 7.0
Average Temperature Coefficient of Input Offset DVIO/DT − 10 − − 10 − mV/°C
Voltage
RS = 10 W, VCM = 0 V, VO = 0 V,
TA = Tlow to Thigh
Input Bias Current (VCM = 0 V, VO = 0 V) IIB nA
TA = +25°C − 100 500 − 100 500
TA = Tlow to Thigh − − 700 − − 700
Input Offset Current (VCM = 0 V, VO = 0V) IIO nA
TA = +25°C − 6.0 50 − 6.0 75
TA = Tlow to Thigh − − 300 − − 300
Input Common Mode Voltage Range VICR V
TA = +25°C VEE to (VCC −1.8) VEE to (VCC −1.8)
TA = Tlow to Thigh VEE to (VCC −2.2) VEE to (VCC −2.2)

Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kW) AVOL V/mV
TA = +25°C 50 100 − 25 100 −
TA = Tlow to Thigh 25 − − 20 − −
Output Voltage Swing (VID = ±1.0 V) VOH V
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kW, TA = +25°C 3.7 4.0 − 3.7 4.0 −
VCC = +15 V, VEE = −15 V, RL = 10 kW, TA = +25°C 13.6 14 − 13.6 14 −
VCC = +15 V, VEE = −15 V, RL = 2.0 kW, 13.4 − − 13.4 − −
TA = Tlow to Thigh
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kW, TA = +25°C VOL 0.1 0.3 − 0.1 0.3 V
−
VCC = +15 V, VEE = −15 V, RL = 10 kW, TA = +25°C −14.7 −14.3 − −14.7 −14.3
−
VCC = +15 V, VEE = −15 V, RL = 2.0 kW, − −13.5 − − −13.5
−
TA = Tlow to Thigh

Output Short Circuit Current (VID = 1.0 V, VO = 0 V, ISC mA

TA = 25°C)
Source 10 30 − 10 30 −
Sink 20 30 − 20 30 −
Common Mode Rejection CMR 80 97 − 70 97 − dB
RS ≤ 10 kW, VCM = VICR, TA = 25°C

Power Supply Rejection (RS = 100 W) PSR 80 97 − 70 97 − dB

VCC/VEE = +16.5 V/−16.5 V to +13.5 V/−13.5 V,
TA = 25°C
Power Supply Current (Per Amplifier, No Load) ID mA
VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°C − 1.6 2.0 − 1.6 2.0
VCC = +15 V, VEE = −15 V, VO = 0 V, TA = +25°C − 1.9 2.5 − 1.9 2.5
VCC = +15 V, VEE = −15 V, VO = 0 V, − − 2.8 − − 2.8
TA = Tlow to Thigh
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Tlow = −40°C for MC33071,2,4,/A, NCV33074/A Thigh = +85°C for MC33071,2,4,/A, NCV33074/A
= 0°C for MC34071,2,4,/A = +70°C for MC34071,2,4,/A
= −40°C for MC34072,4/V, NCV33072,4A = +125°C for MC34072,4/V, NCV33072,4A, NCV34074V
Case 510AJ Tlow/Thigh guaranteed by product characterization.

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.)
A Suffix Non−Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, CL = 500 pF) SR V/ms
AV = +1.0 8.0 10 − 8.0 10 −
AV = −1.0 − 13 − − 13 −
Setting Time (10 V Step, AV = −1.0) ts ms
To 0.1% (+1/2 LSB of 9−Bits) − 1.1 − − 1.1 −
To 0.01% (+1/2 LSB of 12−Bits) − 2.2 − − 2.2 −
Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 − 3.5 4.5 − MHz
Power Bandwidth BW − 160 − − 160 − kHz
AV = +1.0, RL = 2.0 kW, VO = 20 Vpp, THD = 5.0%
Phase margin fm Deg
RL = 2.0 kW − 60 − − 60 −
RL = 2.0 kW, CL = 300 pF − 40 − − 40 −
Gain Margin Am dB
RL = 2.0 kW − 12 − − 12 −
RL = 2.0 kW, CL = 300 pF − 4.0 − − 4.0 −
Equivalent Input Noise Voltage en − 32 − − 32 − nV/ √ Hz
RS = 100 W, f = 1.0 kHz
Equivalent Input Noise Current in − 0.22 − − 0.22 − pA/ √ Hz
f = 1.0 kHz

Differential Input Resistance Rin − 150 − − 150 − MW

VCM = 0 V

Differential Input Capacitance Cin − 2.5 − − 2.5 − pF

VCM = 0 V

Total Harmonic Distortion THD − 0.02 − − 0.02 − %

AV = +10, RL = 2.0 kW, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
Channel Separation (f = 10 kHz) − − 120 − − 120 − dB
Open Loop Output Impedance (f = 1.0 MHz) |ZO| − 30 − − 30 − W

Single Supply Split Supplies

3.0 V to 44 V VCC+|VEE|≤44 V VCC

VCC VCC
7
2
-
1 VCC 1 6
3 5
+
2 2 1
4

3 3
10 k

4 VEE 4 VEE

VEE VEE Offset nulling range is approximately ± 80 mV with a 10 k

potentiometer (MC33071, MC34071 only).

Figure 2. Power Supply Configurations Figure 3. Offset Null Circuit

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

2400
D MAXIMUM POWER DISSIPATION (mW) 4.0 VCC = +15 V

V IO INPUT OFFSET VOLTAGE (mV)

2000 VEE = -15 V
VCM = 0
2.0
1600
SOIC-14 Pkg 8 & 14 Pin Plastic Pkg
1200 0

800
-2.0
SOIC-8 Pkg
400

V,
-4.0
P,

0
-55 -40 -20 0 20 40 60 80 100 120 140 160 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Power Dissipation versus Figure 5. Input Offset Voltage versus
Temperature for Package Types Temperature for Representative Units

ICR INPUT COMMON MODE VOLTAGE RANGE (V)

VCC 1.3

IB INPUT BIAS CURRENT (NORMALIZED)

VCC VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V VCC = +15 V
1.2 VEE = -15 V
VCC -0.8
VCM = 0
1.1
VCC -1.6
1.0
VCC -2.4
0.9

VEE +0.01 0.8

VEE
I,
V,

VEE 0.7
-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 6. Input Common Mode Voltage Figure 7. Normalized Input Bias Current
Range versus Temperature versus Temperature
IB INPUT BIAS CURRENT (NORMALIZED)

1.4 50
VCC = +15 V RL Connected
VO, OUTPUT VOLTAGE SWING (Vpp )

VEE = -15 V to Ground TA = 25°C

40
1.2 TA = 25°C

30
RL = 10 k RL = 2.0 k
1.0
20

0.8
10
I,

0.6 0
-12 -8.0 -4.0 0 4.0 8.0 12 0 5.0 10 15 20 25
VIC, INPUT COMMON MODE VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V)

Figure 8. Normalized Input Bias Current versus Figure 9. Split Supply Output Voltage
Input Common Mode Voltage Swing versus Supply Voltage

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

VCC VCC
Vsat , OUTPUT SATURATION VOLTAGE (V)

Vsat , OUTPUT SATURATION VOLTAGE (V)

Source VCC/VEE = +4.5 V/ -4.5 V to +22 V/ -22 V VCC

VCC -1.0 VCC-2.0

−40 VCC = +15 V
25 RL = GND
VCC -2.0 VCC-4.0 TA = 25°C
125

VEE +2.0 Sink 0.2

25
VEE +1.0 0.1
85
GND
125
VEE 0
0 5.0 10 15 20 100 1.0 k 10 k 100 k
IL, LOAD CURRENT (± mA) RL, LOAD RESISTANCE TO GROUND (W)

Figure 10. Split Supply Output Saturation Figure 11. Single Supply Output Saturation
versus Load Current versus Load Resistance to Ground

0 60
Vsat , OUTPUT SATURATION VOLTAGE (V)

VCC
50

SC OUTPUT CURRENT (mA)

-0.4 Sink
40
-0.8
Source
30
2.0
VCC = +15 V 20
RL to VCC VCC = +15 V
TA = 25°C
I,

1.0 VEE = -15 V

10
GND RL ≤ 0.1 W
DVin = 1.0 V
0
100 1.0 k 10 k 100 k -55 -25 0 25 50 75 100 125
RL, LOAD RESISTANCE TO VCC (W) TA, AMBIENT TEMPERATURE (°C)

Figure 12. Single Supply Output Saturation Figure 13. Output Short Circuit Current
versus Load Resistance to VCC versus Temperature

50 28
VCC = +15 V
VCC = +15 V
VO, OUTPUT VOLTAGE SWING (Vpp )

VEE = -15 V 24
O OUTPUT IMPEDANCE ()

40 VCM = 0 VEE = -15 V

Ω

VO = 0 AV = +1.0
20
DIO = ±0.5 mA RL = 2.0 k
30 TA = 25°C THD ≤ 1.0%
16 TA = 25°C

20 12

AV = 1000 AV = 100 AV = 10 AV = 1.0 8.0

10
Z,

4.0

0 0
1.0 k 10 k 100 1.0 M 10 M 3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 14. Output Impedance Figure 15. Output Voltage Swing

versus Frequency versus Frequency

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

0.4 4.0
THD, TOTAL HARMONIC DISTORTION (%)

THD, TOTAL HARMONIC DISTORTION (%)

AV = 1000 VCC = +15 V
VEE = -15 V
0.3 3.0 AV = 1000 RL = 2.0 k
TA = 25°C
VCC = +15 V
VEE = -15 V
0.2 VO = 2.0 Vpp 2.0
RL = 2.0 k
TA = 25°C AV = 100
AV = 100
0.1 1.0 AV = 10
AV = 10
AV = 1.0
AV = 1.0
0 0
10 100 1.0 k 10 k 100 k 0 4.0 8.0 12 16 20
f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE SWING (Vpp)

Figure 16. Total Harmonic Distortion Figure 17. Total Harmonic Distortion
versus Frequency versus Output Voltage Swing

116 100
VOL OPEN LOOP VOLTAGE GAIN (dB)

VOL OPEN LOOP VOLTAGE GAIN (dB)

0
VCC = +15 V

φ, EXCESS PHASE (DEGREES)

112 80
VEE = -15 V Gain
VO= -10 V to +10 V Phase 45
108 RL = 10 k 60
f ≤ 10Hz Phase
Margin 90
104 40 = 60°
VCC = +15 V 135
VEE = -15 V
100 20 VO = 0 V
A,

A,

RL = 2.0 k
180
TA = 25°C
96 0
-55 -25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz)

Figure 18. Open Loop Voltage Gain Figure 19. Open Loop Voltage Gain and
versus Temperature Phase versus Frequency
GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)

20 1.15
VOL OPEN LOOP VOLTAGE GAIN (dB)

1 100
Phase VCC = +15 V
10 Margin = 60° 1.1 VEE = -15 V
φ, EXCESS PHASE (DEGREES)

Gain 120 RL = 2.0 k

0 Margin = 12 dB
1.05
140
-10 1.0
1. Phase RL = 2.0 k
160
2. Phase RL = 2.0 k, CL = 300 pF 3
-20 3. Gain RL = 2.0 k 0.95
4. Gain RL = 2.0 k, CL = 300 pF 180
4
-30 VCC = +15 V
A,

0.9
VEE = 15 V 2
VO = 0 VTA = 25°C
-40 0.85
1.0 2.0 3.0 5.0 7.0 10 20 30 -55 -25 0 25 50 75 100 125
f, FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (°C)

Figure 20. Open Loop Voltage Gain and Figure 21. Normalized Gain Bandwidth
Phase versus Frequency Product versus Temperature

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

100 70
VCC = +15 V

φ m , PHASE MARGIN (DEGREES)

60 VCC = +15 V
80 VEE = -15 V VEE = -15 V
PERCENT OVERSHOOT

RL = 2.0 k AV = +1.0
50
VO = -10 V to +10 V RL = 2.0 k to R
60 TA = 25°C VO = -10 V to +10 V
40
TA = 25°C
30
40
20
20
10

0 0
10 100 1.0 k 10 k 10 100 1.0 k 10 k
CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF)

Figure 22. Percent Overshoot versus Figure 23. Phase Margin versus
Load Capacitance Load Capacitance

14 80
VCC = +15 V
φ m , PHASE MARGIN (DEGREES)
12 CL = 10 pF
VEE = -15 V
m GAIN MARGIN (dB)

AV = +1.0 60 CL = 100 pF
10
RL = 2.0 k to ∞
VO = -10 V to +10 V
8.0 TA = 25°C VCC = +15 V
40 VEE = -15 V
6.0 AV = +1.0
RL = 2.0 k to ∞
A,

4.0 CL = 1,000 pF VO = -10 V to +10 V

20
2.0 CL = 10,000 pF

0 0
10 100 1.0 k 10 k -55 -25 0 25 50 75 100 125
CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE (°C)

Figure 24. Gain Margin versus Load Capacitance Figure 25. Phase Margin versus Temperature

16 12 70
VCC = +15 V
φ m , PHASE MARGIN (DEGREES)
10 60
CL = 10 pF Gain
m GAIN MARGIN (dB)

m GAIN MARGIN (dB)

12 VEE = -15 V 8.0 50

AV = +1.0 R1
VO
RL = 2.0 k to ∞ -
6.0 + 40
VO = -10 V to +10 V CL = 100 pF
8.0 R2
4.0 30
VCC = +15 V
VEE = -15 V
A,

CL = 10,000 pF
A,

2.0 RT = R1 + R2 20
4.0 CL = 1,000 pF Phase
AV = +100
0 VO = 0 V 10
TA = 25°C
0 0
-55 -25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k
TA, AMBIENT TEMPERATURE (°C) RT, DIFFERENTIAL SOURCE RESISTANCE (W)

Figure 26. Gain Margin versus Temperature Figure 27. Phase Margin and Gain Margin
versus Differential Source Resistance

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

1.15 10

O OUTPUT VOLTAGE SWING FROM 0 V (V)

VCC = +15 V VCC = +15 V
1.0 mV
SR, SLEW RATE (NORMALIZED)
1.1 VEE = -15 V 10 mV 1.0 mV VEE = -15 V
AV = +1.0 5.0 AV = -1.0
RL = 2.0 k TA = 25°C
1.05
CL = 500 pF
Compensated
1.0 0
Uncompensated
0.95
-5.0 1.0 mV
0.9 10 mV
1.0 mV

Δ V,
0.85 -10
-55 -25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TA, AMBIENT TEMPERATURE (°C) ts, SETTLING TIME (ms)

Figure 28. Normalized Slew Rate Figure 29. Output Settling Time
versus Temperature

VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
50 mV/DIV

5.0 V/DIV

0 0 TA = 25°C
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25°C

2.0 ms/DIV 1.0 ms/DIV

Figure 30. Small Signal Transient Response Figure 31. Large Signal Transient Response

100 100
CMR, COMMON MODE REJECTION (dB)

TA = 125°C VCC = +15 V VCC = +15 V

PSR, POWER SUPPLY REJECTION (dB)

TA = 25°C VEE = -15 V VEE = -15 V

80 VCM = 0 V 80 TA = 25°C
TA = -55°C DVCM = ±1.5 V DVCC
- (DVCC = +1.5 V)
60 60 ADM DVO
+

DVEE
40 - 40 DVO/ADM
+PSR
DVCM ADM DVO +PSR = 20 Log
+ DVCC
20 20
DVCM DVO/ADM
CMR = 20 Log x ADM -PSR = 20 Log -PSR
DVO DVEE (DVEE = +1.5 V)
0 0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 32. Common Mode Rejection Figure 33. Power Supply Rejection
versus Frequency versus Frequency

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

9.0 105

PSR, POWER SUPPLY REJECTION (dB)

-PSR (DVEE = +1.5 V) VCC = +15 V
TA = -55°C
CC , SUPPLY CURRENT (mA)

8.0 VEE = -15 V

95

7.0 +PSR (DVCC = +1.5 V)

TA = 25°C
85
6.0 DVCC
DVO/ADM
TA = 125°C +PSR = 20 Log -
DVCC ADM DVO
75
I

+
5.0 DVO/ADM
-PSR = 20 Log DVEE
Quad device DVEE
4.0 65
0 5.0 10 15 20 25 -55 -25 0 25 50 75 100 125
VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

Figure 34. Supply Current versus Figure 35. Power Supply Rejection
Supply Voltage versus Temperature

120 70 2.8

n INPUT NOICE VOLTAGE ( nV √ Hz)

n INPUT NOISE CURRENT (pA √ Hz )

VCC = +15 V
100 VCC = +15 V 60 VEE = -15 V 2.4
CHANNEL SEPARATION (dB)

VEE = -15 V VCM = 0

TA = 25°C 50 TA = 25°C 2.0
80
40 1.6
60 Voltage
30 1.2
40
20 Current 0.8
20 10 0.4
e,

i,
0 0 0
10 20 30 50 70 100 200 300 10 100 1.0 k 10 k 100 k
f, FREQUENCY (kHz) f, FREQUENCY (kHz)

Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency

APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the up to approximately 5.0 mA of current from VEE through
MC34071 amplifier series are similar to op amp products either inputs clamping diode without damage or latching,
utilizing JFET input devices, these amplifiers offer other although phase reversal may again occur.
additional distinct advantages as a result of the PNP If one or both inputs exceed the upper common mode
transistor differential input stage and an all NPN transistor voltage limit, the amplifier output is readily predictable and
output stage. may be in a low or high state depending on the existing input
Since the input common mode voltage range of this input bias conditions.
stage includes the VEE potential, single supply operation is Since the input capacitance associated with the small
feasible to as low as 3.0 V with the common mode input geometry input device is substantially lower (2.5 pF) than
voltage at ground potential. the typical JFET input gate capacitance (5.0 pF), better
The input stage also allows differential input voltages up frequency response for a given input source resistance can
to ±44 V, provided the maximum input voltage range is not be achieved using the MC34071 series of amplifiers. This
exceeded. Specifically, the input voltages must range performance feature becomes evident, for example, in fast
between VEE and VCC supply voltages as shown by the settling D−to−A current to voltage conversion applications
maximum rating table. In practice, although not where the feedback resistance can form an input pole with
recommended, the input voltages can exceed the VCC the input capacitance of the op amp. This input pole creates
voltage by approximately 3.0 V and decrease below the VEE a 2nd order system with the single pole op amp and is
voltage by 0.3 V without causing product damage, although therefore detrimental to its settling time. In this context,
output phase reversal may occur. It is also possible to source lower input capacitance is desirable especially for higher

www.onsemi.com
11
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

values of feedback resistances (lower current DACs). This Because the PNP output emitter−follower transistor has
input pole can be compensated for by creating a feedback been eliminated, the MC34071 series offers a 20 mA
zero with a capacitance across the feedback resistance, if minimum current sink capability, typically to an output
necessary, to reduce overshoot. For 2.0 kW of feedback voltage of (VEE +1.8 V). In single supply applications the
resistance, the MC34071 series can settle to within 1/2 LSB output can directly source or sink base current from a
of 8−bits in 1.0 ms, and within 1/2 LSB of 12−bits in 2.2 ms common emitter NPN transistor for fast high current
for a 10 V step. In a inverting unity gain fast settling switching applications.
configuration, the symmetrical slew rate is ±13 V/ms. In the In addition, the all NPN transistor output stage is
classic noninverting unity gain configuration, the output inherently fast, contributing to the bipolar amplifier’s high
positive slew rate is +10 V/ms, and the corresponding gain bandwidth product and fast settling capability. The
negative slew rate will exceed the positive slew rate as a associated high frequency low output impedance (30 W typ
function of the fall time of the input waveform. @ 1.0 MHz) allows capacitive drive capability from 0 pF to
Since the bipolar input device matching characteristics 10,000 pF without oscillation in the unity closed loop gain
are superior to that of JFETs, a low untrimmed maximum configuration. The 60° phase margin and 12 dB gain margin
offset voltage of 3.0 mV prime and 5.0 mV downgrade can as well as the general gain and phase characteristics are
be economically offered with high frequency performance virtually independent of the source/sink output swing
characteristics. This combination is ideal for low cost conditions. This allows easier system phase compensation,
precision, high speed quad op amp applications. since output swing will not be a phase consideration. The
The all NPN output stage, shown in its basic form on the high frequency characteristics of the MC34071 series also
equivalent circuit schematic, offers unique advantages over allow excellent high frequency active filter capability,
the more conventional NPN/PNP transistor Class AB output especially for low voltage single supply applications.
stage. A 10 kW load resistance can swing within 1.0 V of the Although the single supply specifications is defined at
positive rail (VCC), and within 0.3 V of the negative rail 5.0 V, these amplifiers are functional to 3.0 V @ 25°C
(VEE), providing a 28.7 Vpp swing from ±15 V supplies. although slight changes in parametrics such as bandwidth,
This large output swing becomes most noticeable at lower slew rate, and DC gain may occur.
supply voltages. If power to this integrated circuit is applied in reverse
The positive swing is limited by the saturation voltage of polarity or if the IC is installed backwards in a socket, large
the current source transistor Q7, and VBE of the NPN pull up unlimited current surges will occur through the device that
transistor Q17, and the voltage drop associated with the short may result in device destruction.
circuit resistance, R7. The negative swing is limited by the Special static precautions are not necessary for these
saturation voltage of the pull−down transistor Q16, the bipolar amplifiers since there are no MOS transistors on the
voltage drop ILR6, and the voltage drop associated with die.
resistance R7, where IL is the sink load current. For small As with most high frequency amplifiers, proper lead
valued sink currents, the above voltage drops are negligible, dress, component placement, and PC board layout should be
allowing the negative swing voltage to approach within exercised for optimum frequency performance. For
millivolts of VEE. For large valued sink currents (>5.0 mA), example, long unshielded input or output leads may result in
diode D3 clamps the voltage across R6, thus limiting the unwanted input−output coupling. In order to preserve the
negative swing to the saturation voltage of Q16, plus the relatively low input capacitance associated with these
forward diode drop of D3 (≈VEE +1.0 V). Thus for a given amplifiers, resistors connected to the inputs should be
supply voltage, unprecedented peak−to−peak output voltage immediately adjacent to the input pin to minimize additional
swing is possible as indicated by the output swing stray input capacitance. This not only minimizes the input
specifications. pole for optimum frequency response, but also minimizes
If the load resistance is referenced to VCC instead of extraneous “pick up” at this node. Supply decoupling with
ground for single supply applications, the maximum adequate capacitance immediately adjacent to the supply pin
possible output swing can be achieved for a given supply is also important, particularly over temperature, since many
voltage. For light load currents, the load resistance will pull types of decoupling capacitors exhibit great impedance
the output to VCC during the positive swing and the output changes over temperature.
will pull the load resistance near ground during the negative The output of any one amplifier is current limited and thus
swing. The load resistance value should be much less than protected from a direct short to ground. However, under
that of the feedback resistance to maximize pull up such conditions, it is important not to allow the device to
capability. exceed the maximum junction temperature rating. Typically
for ±15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.

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12
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

(Typical Single Supply Applications VCC = 5.0 V)

VCC

5.1 M VO
0 3.7 Vpp
VCC 0 3.7 Vpp

20 k 1.0 M 100 k
Cin
+ CO VO
MC34071
68 k
+
36.6 mVpp - Cin 10 k MC34071 VO
Vin 100 k - CO
10 k 10 k
RL 100 k RL
Vin 370 mVpp
1.0 k AV = 101
BW (-3.0 dB) = 45 kHz AV = 10 BW (-3.0 dB) = 450 kHz

Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier

VO
4.75 Vpp VCC
2.63 V
91 k
5.1 k
RL
5.1 k
+ 2.5 V

100 k
MC34071 VO
- 0 0 to 10,000 pF
Vin + MC54/74XX
1.0 M MC34071
- Cable TTL Gate
Vin AV = 10
BW (-3.0 dB) = 450 kHz

Figure 40. DC Coupled Inverting Amplifier Figure 41. Unity Gain Buffer TTL Driver
Maximum Output Swing

C R3
0.047 2.2 k
R1
Vin -
1.1 k C MC34071 VO
R2 0.047 +
VCC
Vin ≥ 0.2 Vdc 5.6 k fo = 30 kHz
- VO Ho = 10
MC34071
0.4 VCC Ho = 1.0
R R
Vin + Given fo = Center Frequency
16 k 16 k AO = Gain at Center Frequency
C Choose Value fo, Q, Ao, C
0.01
Then: Q R3 R1 R3
R3 =  R1 =  R2 =
fo = 1.0 kHz pfoC 2Ho 4Q2R1-R3
32 k 2.0 R
1 Qofo
fo = For less than 10% error from operational amplifier < 0.1
4pRC GBW
2.0 C 2.0 C where fo and GBW are expressed in Hz.
0.02 0.02 GBW = 4.5 MHz Typ.

Figure 42. Active High−Q Notch Filter Figure 43. Active Bandpass Filter

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13
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

CF Vin

2.0 V
RF Vin
+ VO
5.0 k 5.0 k 5.0 k MC34071 t
- VO -
MC34071 2.0 k VO
10 k 10 k 10 k + VCC RL
1.0 V 0.2 ms
4.0 V Delay
Bit 13 V/ms
Switches 25 V/ms
(R-2R) Ladder Network
0.1 t
Settling Time Delay
1.0 ms (8-Bits, 1/2 LSB) 1.0 ms

Figure 44. Low Voltage Fast D/A Converter Figure 45. High Speed Low Voltage Comparator

VCC
“ON"
Vin < Vref
VCC
VCC

Vin + RL
MC34071
- + +
Vref MC34071 MC34071
- -
“ON"
Vin > Vref RL

(A) PNP (B) NPN

Figure 46. LED Driver Figure 47. Transistor Driver

ILoad

RF
+
MC34071 VO
-
Ground Current RS -
Sense Resistor ICell
R1 MC34071 VO
+
R2 R1
VO = ILoad RS 1+
R2
For VO > 0.1V
VCell = 0 V
R2 VO = ICell RF
BW ( -3.0 dB) = GBW
R1+R2 VO > 0.1 V

Figure 48. AC/DC Ground Current Monitor Figure 49. Photovoltaic Cell Amplifier

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14
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

VO Hysteresis
R2

Vref R1 VOH
+ Iout
MC34071 VOL
- Vin
Vin +
Vin
VinL VinH MC34071
R1 Vref -
VinL = (VOL-Vref)+Vref
R1+R2
R1
VinH = (VOH-Vref)+Vref
R1+R2
R1 Vin±VIO R
VH = (VOH -VOL) Iout =
R1+R R

Figure 50. Low Input Voltage Comparator Figure 51. High Compliance Voltage to
with Hysteresis Sink Current Converter

R1 R2
R4 +Vref
RF
- 1/2 R3
- 1/2 VO R R
MC34072
+V1 + MC34072
- VO
+ MC34071
+V2 R +
R = DR
R2 R4
= (Critical to CMRR)
R1 R3
DR RF
R4 R4 VO = Vref
VO = 1 + V2-V1 RF 2R2
R3 R3 DR < < R
For (V2 ≥ V1), V > 0 RF > > R (VO ≥ 0.1 V)

Figure 52. High Input Impedance Figure 53. Bridge Current Amplifier
Differential Amplifier

fOSC ^ 0.85
RC + IB +
V
ISC
VP 0 t
Vin
+ VO = Vin (pk) t - Base Charge
MC34071
Removal
-
Iout

- 1/2 R + 1/2
+ MC34072 MC34072
RL VP 10,000 pF C + - ±IB

V+ 100 k
100 k VP Pulse Width
Vin 47 k Control Group
VP

OSC Comparator High Current

t Output

Figure 54. Low Voltage Peak Detector Figure 55. High Frequency Pulse
Width Modulation

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 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = ±15.0 V

C2 C2 R1
0.02 0.05 C1 46.1 k
1.0
R2 -
R1 R3 5.6 k C1 MC34071
560 510
- 1.0 R2 + fo = 100 Hz
1.1 k Ho = 20
MC34071
C1 fo = 1.0 kHz
0.44 +
Ho = 10 Ho+0.5
Choose: fo, Ho, C1 Then: R1 =
Choose: fo, Ho, C2 pfoC1 Ǹ2
Ǹ2
Then: C1 = 2C2 (Ho+1) R2 =
2pfoC1 (1/Ho+2)
Ǹ2 R2 R2 C
R2 = R3 = R1 = C2 =
4pfoC2 Ho+1 Ho Ho

Figure 56. Second Order Low−Pass Active Filter Figure 57. Second Order High−Pass Active Filter

CF *

VO = 10 V
RF Step

2.0 k

+
-
MC34071 VO
MC34071 VO R1
- RL
+
I Vin R2
ts = 1.0 ms
Uncompensated
to 1/2 LSB (8-Bits)
ts = 2.2 ms VO
High Speed Compensated R2 R1
DAC to 1/2 LSB (12-Bits) = BW (-3.0 dB) = GBW
Vin R1 R1 +R2

*Optional Compensation SR = 13 V/ms SR = 13 V/ms

Figure 58. Fast Settling Inverter Figure 59. Basic Inverting Amplifier

+
MC34071 VO
-
Vin
R2 Vin +
MC34071 VO
RL
-
R1
VO R2
= 1+
Vin R1
BWp = 200 kHz
R1 VO = 20 Vpp
BW (-3.0 dB) = GBW
R1 +R2 SR = 10 V/ms

Figure 60. Basic Noninverting Amplifier Figure 61. Unity Gain Buffer (AV = +1.0)

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16
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

+ R
R
MC34074
-
R
-

RE MC34074 VO

R +

-
R Example:
MC34074
Let: R = RE = 12 k R
+ Then: AV = 3.0 AV = 1 +2
R BW = 1.5 MHz RE

Figure 62. High Impedance Differential Amplifier

+VO

+
+ +
MC34074
100 k - RL
10 10
+10

-
MC34074
220 pF +
100 k
-10
+
+ RL
+ 10
MC34074
RL +VO -VO 100 k - 10
∞ 18.93 -18.78
10 k 18 -18
-VO
5.0 k 15.4 -15.4

Figure 63. Dual Voltage Doubler

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17
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

ORDERING INFORMATION
Op Amp Operating
Shipping†
Function Device Temperature Range Package
MC34071DR2G SOIC−8
TA = 0° to +70°C 2500 / Tape & Reel
(Pb−Free)
MC33071DR2G SOIC−8
Single 2500 / Tape & Reel
(Pb−Free)
TA = −40° to +85°C
MC33071ADR2G SOIC−8
2500 / Tape & Reel
(Pb−Free)
MC34072DR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC34072ADR2G SOIC−8
TA = 0° to +70°C
(Pb−Free)
MC34072AMTTBG WQFN10
3000 Units / Tape & Reel
(Pb−Free)
MC33072DR2G SOIC−8
Dual
(Pb−Free)
TA = −40° to +85°C 2500 / Tape & Reel
MC33072ADR2G SOIC−8
(Pb−Free)
MC34072VDR2G SOIC−8
2500 / Tape & Reel
(Pb−Free)
TA = −40° to +125°C
NCV33072DR2G* SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC34074ADR2G SOIC−14
(Pb−Free)
TA = 0° to +70°C 2500 Units / Tape & Reel
MC34074DR2G SOIC−14
(Pb−Free)
MC33074DR2G SOIC−14
(Pb−Free)
2500 / Tape & Reel
NCV33074DR2G* SOIC−14
(Pb−Free)
MC33074ADR2G SOIC−14
(Pb−Free)
2500 / Tape & Reel
NCV33074ADR2G* SOIC−14
Quad TA = −40° to +85°C
(Pb−Free)
MC33074DTBR2G TSSOP−14
2500 / Tape & Reel
(Pb−Free)
MC33074ADTBR2G TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NCV33074ADTBR2G* TSSOP−14
(Pb−Free)
MC34074VDR2G SOIC−14
(Pb−Free)
TA = −40° to +125°C 2500 / Tape & Reel
NCV34074VDR2G* SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAP
capable.

www.onsemi.com
18
 MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A

MARKING DIAGRAMS

SOIC−8
D SUFFIX
CASE 751

8 8 8 8 8
3x071 3x071 3x072 3x072 34072
ALYW ALYWA ALYW ALYWA ALYWV
    
1 1 1 1 1
*applies to NCV33072DR2G

SOIC−14 TSSOP−14
D SUFFIX DTB SUFFIX
CASE 751A CASE 948G

14 14 14 14 14 14

MC3x074DG MC3x074ADG MC34074VDG MC33 MC33 NCV3

AWLYWW AWLYWW AWLYWW 074 074A 074A
ALYW ALYW ALYW
1 1 1   
*applies to NCV34074VDR2G
1 1 1
WQFN10
MT SUFFIX
CASE 510AJ

4072
AAYW


x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or  = Pb−Free Package
(Note: Microdot may be in either location)

www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

WQFN10 2.6x2.6, 0.5P

CASE 510AJ−01
ISSUE A
SCALE 2:1 DATE 27 MAR 2009

L L

ÍÍÍ
D A B NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

ÍÍÍ
2. CONTROLLING DIMENSION: MILLIMETERS.
PIN ONE L1 3. DIMENSION b APPLIES TO PLATED

ÍÍÍ
REFERENCE TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
E DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED
ALTERNATE TERMINAL PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS MILLIMETERS
DIM MIN MAX
0.15 C

ÉÉ
A 0.70 0.80
A1 0.00 0.05
0.15 C EXPOSED Cu MOLD CMPD

ÉÉ
A3 0.20 REF
TOP VIEW b 0.20 0.30
D 2.60 BSC
E 2.60 BSC
0.10 C DETAIL B A3 e 0.50 BSC
DETAIL B L 0.45 0.55
ALTERNATE
A CONSTRUCTIONS
L1 0.00 0.15
L2 0.55 0.65
0.08 C
A1
NOTE 4 GENERIC
SIDE VIEW C SEATING
PLANE MARKING DIAGRAM*
DETAIL A
9X L 5 XXXX
AAYW
4 6 G

XXXX = Specific Device Code

AA = Assembly Location
1 9
e Y = Year
10 W = Work Week
L2
G = Pb−Free Package
10X b
0.10 C A B *This information is generic. Please refer to
device data sheet for actual part marking.
0.05 C NOTE 3
BOTTOM VIEW Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
2.90

1
0.50
PITCH
2.90

10X 0.30
10X 0.73
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON38696E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: WQFN10 2.6X2.6, 0.5P PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011

NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S

GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
ALYWX ALYWX AYWW AYWW
1.52
G G
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week G = Pb−Free Package
G = Pb−Free Package

0.6 1.270 *This information is generic. Please refer to

0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
SCALE 6:1 ǒinches
mm Ǔ or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
STYLE 5: STYLE 6: STYLE 7: STYLE 8:
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1
STYLE 9: STYLE 10: STYLE 11: STYLE 12:
PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE
3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE
4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE
5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN
6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN
7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN
8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN

STYLE 13: STYLE 14: STYLE 15: STYLE 16:

PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1

STYLE 17: STYLE 18: STYLE 19: STYLE 20:

PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N)
3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
4. TXE 4. GATE 4. GATE 2 4. GATE (P)
5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN
6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN
7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN
8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN
STYLE 21: STYLE 22: STYLE 23: STYLE 24:
PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER
3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE
4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE
5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE
6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE
7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE
8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE

STYLE 25: STYLE 26: STYLE 27: STYLE 28:

PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND
2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF
3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET
4. GND 4. ILIMIT 4. INPUT+ 4. GND
5. IOUT 5. SOURCE 5. SOURCE 5. V_MON
6. IOUT 6. SOURCE 6. SOURCE 6. VBULK
7. IOUT 7. SOURCE 7. SOURCE 7. VBULK
8. IOUT 8. VCC 8. DRAIN 8. VIN
STYLE 29: STYLE 30:
PIN 1. BASE, DIE #1 PIN 1. DRAIN 1
2. EMITTER, #1 2. DRAIN 1
3. BASE, #2 3. GATE 2
4. EMITTER, #2 4. SOURCE 2
5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2
6. COLLECTOR, #2 6. SOURCE 1/DRAIN 2
7. COLLECTOR, #1 7. SOURCE 1/DRAIN 2
8. COLLECTOR, #1 8. GATE 1

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 2 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE

GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW

XXXXX = Specific Device Code

A = Assembly Location
1.27
WL = Wafer Lot
PITCH
Y = Year
WW = Work Week
G = Pb−Free Package
14X
*This information is generic. Please refer to
0.58
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−14 NB PAGE 1 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COMMON CATHODE CANCELLED PIN 1. NO CONNECTION PIN 1. NO CONNECTION
2. ANODE/CATHODE 2. ANODE 2. CATHODE
3. ANODE/CATHODE 3. ANODE 3. CATHODE
4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
5. ANODE/CATHODE 5. ANODE 5. CATHODE
6. NO CONNECTION 6. NO CONNECTION 6. NO CONNECTION
7. ANODE/CATHODE 7. ANODE 7. CATHODE
8. ANODE/CATHODE 8. ANODE 8. CATHODE
9. ANODE/CATHODE 9. ANODE 9. CATHODE
10. NO CONNECTION 10. NO CONNECTION 10. NO CONNECTION
11. ANODE/CATHODE 11. ANODE 11. CATHODE
12. ANODE/CATHODE 12. ANODE 12. CATHODE
13. NO CONNECTION 13. NO CONNECTION 13. NO CONNECTION
14. COMMON ANODE 14. COMMON CATHODE 14. COMMON ANODE

STYLE 5: STYLE 6: STYLE 7: STYLE 8:

PIN 1. COMMON CATHODE PIN 1. CATHODE PIN 1. ANODE/CATHODE PIN 1. COMMON CATHODE
2. ANODE/CATHODE 2. CATHODE 2. COMMON ANODE 2. ANODE/CATHODE
3. ANODE/CATHODE 3. CATHODE 3. COMMON CATHODE 3. ANODE/CATHODE
4. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE 4. NO CONNECTION
5. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE 5. ANODE/CATHODE
6. NO CONNECTION 6. CATHODE 6. ANODE/CATHODE 6. ANODE/CATHODE
7. COMMON ANODE 7. CATHODE 7. ANODE/CATHODE 7. COMMON ANODE
8. COMMON CATHODE 8. ANODE 8. ANODE/CATHODE 8. COMMON ANODE
9. ANODE/CATHODE 9. ANODE 9. ANODE/CATHODE 9. ANODE/CATHODE
10. ANODE/CATHODE 10. ANODE 10. ANODE/CATHODE 10. ANODE/CATHODE
11. ANODE/CATHODE 11. ANODE 11. COMMON CATHODE 11. NO CONNECTION
12. ANODE/CATHODE 12. ANODE 12. COMMON ANODE 12. ANODE/CATHODE
13. NO CONNECTION 13. ANODE 13. ANODE/CATHODE 13. ANODE/CATHODE
14. COMMON ANODE 14. ANODE 14. ANODE/CATHODE 14. COMMON CATHODE

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−14 NB PAGE 2 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1

ÉÉÉ
ÇÇÇ
−V− DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT XXXX
XXXX
7.06
ALYWG
G
1 1

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
0.65 G = Pb−Free Package
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
14X device data sheet for actual part marking.
14X
0.36 Pb−Free indicator, “G” or microdot “ G”,
1.26 may or may not be present.
DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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MC34072DR2 MC34072DR2G MC34072P MC34072PG MC34072VD MC34072VDG MC34072VDR2
MC34072VDR2G MC34072VP MC34072VPG MC34074AD MC34074ADG MC34074ADR2 MC34074ADR2G
MC34074AP MC34074APG MC34074D MC34074DG MC34074DR2 MC34074DR2G MC34074P MC34074PG
MC34074VD MC34074VDG MC34074VDR2 MC34074VDR2G MC34074VP MC34074VPG NCV33074DR2G
NCV33072DR2G NCV33074ADTBR2G NCV33074ADR2G NCV33072ADR2G NCV34074VDR2G
SCV33074ADTBR2G