DATASHEET

EL9115 FN7441
Triple Analog Video Delay Line Rev 7.00
January 12, 2012

The EL9115 is a triple analog delay line that allows skew Features
compensation between any three signals. This part is perfect
for compensating for the skew introduced by a typical CAT-5 • 62ns total delay
cable with differing electrical lengths on each pair. • 2ns delay step increments
The EL9115 can be programmed in steps of 2ns up to 62ns • Operates from ±5V supply
total delay on each channel.
• Up to 122MHz bandwidth
Ordering Information • Low power consumption

PART • 20 Ld QFN (5mmx5mm) package

NUMBER PART PACKAGE PKG.
(Notes 1, 2, 3) MARKING (Pb-free) DWG. #
• Pb-free (RoHS compliant)

EL9115ILZ 9115ILZ 20 Ld 5mmx5mm QFN L20.5x5C Applications

NOTES: • Skew control for RGB
1. Add “-T*” suffix for tape and reel. Please refer to Tech Brief TB347
for details on reel specifications. • Analog beamforming
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, Pinout
and 100% matte tin plate plus anneal (e3 termination finish, EL9115
which is RoHS compliant and compatible with both SnPb and (20 LD 5X5 QFN)
Pb-free soldering operations). Intersil Pb-free products are MSL TOP VIEW
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.

18 TESTG
19 TESTR

17 TESTB

16 VSPO
3. For Moisture Sensitivity Level (MSL), please see device

20 X2
information page for EL9115. For more information on MSL,
please see Tech Brief TB363.
VSP 1 15 ROUT

RIN 2 14 GNDO
THERMAL
GND 3 PAD
13 GOUT

GIN 4 12 VSMO

VSM 5 SCLOCK 10 11 BOUT

BIN 6

CENABLE 7

NSENABLE 8

SDATA 9

EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V

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January 12, 2012
EL9115

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Thermal Resistance (Typical) JA (°C/W)
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA 20 Ld QFN Package (Note 4). . . . . . . . . . . . . . . . . . 32
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation . . See “Typical Performance Curves” on page 4.
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
Operating Conditions http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTE:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

DC Electrical Specifications VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.

MIN MAX
PARAMETER DESCRIPTION CONDITIONS (Note 5) TYP (Note 5) UNIT

V+ Positive Supply Range +4.5 +5.5 V

V- Negative Supply Range -4.5 -5.5 V

G_0 Gain Zero Delay X2 = 5V, 150 load 1.81 1.9 2.04

G_m Gain Mid Delay 1.64 1.8 1.97

G_f Gain Full Delay 1.46 1.7 1.97

DG_m0 Difference in Gain, 0 to Mid -10 -4 2.3 %

DG_f0 Difference in Gain, 0 to Full -17.5 -9 0.3 %

DG_fm Difference in Gain, Mid to Full -15 -5 4 %

VIN Input Voltage Range Gain falls to 90% of nominal -0.7 1.2 V

IB Input Bias Current 1 5 µA

RIN Input Resistance 10 M

VOS_0 Output Offset 0 Delay X2 = +5V, 75 + 75 load -90 0 90 mV

VOS_M Output Offset Mid Delay -90 0 90 mV

VOS_F Output Offset Full Delay -90 0 90 mV

ZOUT Output Impedance Chip enable = +5V 4.5 5 6.3 

Chip enable = 0V 1 M
+PSRR Rejection of Positive Supply X2 = +5V into 75 + 75 load -38 dB

-PSRR Rejection of Negative Supply X2 = +5V into 75 + 75 load -53 dB

ISP Supply Current (Note 5) Chip enable = +5V current on VSP 75 87 115 mA

ISM Supply Current (Note 5) Chip enable = +5V current in VSM -15.25 -12.5 -9.75 mA

ISMO Supply Current (Note 5) Chip enable = +5V current in VSMO -15.25 -13 -11 mA

ISPO Supply Current (Note 5) Chip enable = +5V current in VSPO 10 11.8 15.5 mA

ISP Supply Current (Note 5) Increase in ISP per unit step in delay 0.9 mA

ISP OFF Supply Current (Note 5) Chip enable = 0V current in VSP 1.6 mA

IOUT Output Drive Current 10 load, 0.5V drive, X2 = 5V 40 mA

LHI Logic High Switch high threshold 1.25 1.6 V

LLO Logic Low Switch low threshold 0.8 1.15 V

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January 12, 2012
EL9115

AC Electrical Specifications VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.

MIN MAX
PARAMETER DESCRIPTION CONDITIONS (Note 5) TYP (Note 5) UNIT
BW -3dB 3dB Bandwidth 0ns Delay Time 122 MHz
BW 0.1dB 0.1dB Bandwidth 0ns Delay Time 60 MHz
SR Slew Rate 0ns Delay Time 400 V/µs
tR - t F Transient Response Time 20% to 80%, for all delays, 1V step 2.5 ns
VOVER Voltage Overshoot For any delay, response to 1V step input 5 %
Glitch Switching Glitch Time for o/p to settle after last s_clock edge 100 ns
THD Total Harmonic Distortion 1VP-P 10MHz sinewave, offset by +0.2V at -50 -40 dB
mid delay setting
Xt Hostile Crosstalk Stimulate G, measure R/B at 1MHz -80 dB
VN Output Noise Gain X2, measured at 75 load 2.5 mVRMS
dt Nominal Delay Increment Note 7 1.75 2 2.25 ns
tMAX Maximum Delay 55 62 70 ns
DELDT Delay Diff Between Channels 1.6 %
tPD Propagation Delay Measured input to output 9.8 ns
tMAX Max s_clock Frequency Maximum programming clock speed 10 MHz
t_en_ck Minimum Separation Between Serial Check enable low edge can occur after 10 ns
Enable and Clock t_en_ck of previous (ignored) clock and up
to before t_en_ck of next (wanted) clock.
Clock edges occurring within t_en_ck of the
enable edge will have uncertain effect.
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
7. Delay increment limits are derived by taking Maximum Delay limits and dividing by the number of steps for the device (e.g., the number of steps
for the EL9115 is 31).

Pin Descriptions
PIN NUMBER PIN NAME PIN DESCRIPTION
1 VSP +5V for delay circuitry and input amp
2 RIN Red channel input, ref GND
3 GND 0V for delay circuitry supply
4 GIN Green channel input, ref GND
5 VSM -5V for input amp
6 BIN Blue channel input, ref GND
7 CENABLE Chip enable logical +5V enables chip
8 NSENABLE ENABLE for serial input; enable on low
9 SDATA Data into registers; logic threshold 1.2V
10 SCLOCK Clock to enter data; logical; data written on negative edge
11 BOUT Blue channel output, ref GNDO
12 VSMO -5V for output buffers
13 GOUT Green channel output, ref GNDO
14 GNDO 0V reference for input and output buffers
15 ROUT Red channel output, ref GNDO
16 VSPO +5V for output buffers

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January 12, 2012
EL9115

Pin Descriptions (Continued)

PIN NUMBER PIN NAME PIN DESCRIPTION
17 TESTB Blue channel phase detector output
18 TESTG Green channel phase detector output
19 TESTR Red channel phase detector output
20 X2 Sets gain to 2X if input high; X1 otherwise
Thermal Pad Must be connected to -5V

Typical Performance Curves

Delay = 0ns
-3dB@122MHz
Delay = 0ns

Delay = 62ns
Delay = 62ns
-3dB@80MHz

Delay 10, 20, 30, 40 and 50ns Delay 10, 20, 30, 40 and 50ns

FIGURE 1. GAIN vs FREQUENCY FIGURE 2. GAIN vs FREQUENCY

20 20

0 10

-20 0
DC OFFSET (mV)

DC OFFSET (mV)

-10
-40
-20
-60
-30
-80
-40
-100
-50
-120 -60
-140 -70
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 0 10 20 30 40 50 60 70
PROGRAMMED DELAY (ns) PROGRAMMED DELAY (ns)

FIGURE 3. DC OFFSET vs DELAY TIME (GAIN = 2X) FIGURE 4. DC OFFSET vs DELAY TIME (GAIN = 1X)

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January 12, 2012
EL9115

Typical Performance Curves (Continued)

DELAY TIME (ns) DELAY TIME (ns)

FIGURE 5. RISE TIME vs DELAY TIME FIGURE 6. FALL TIME vs DELAY TIME

Vout = 1Vptp 3 Channels

DELAY TIME (ns)

FIGURE 7. DISTORTION vs FREQUENCY FIGURE 8. POSITIVE SUPPLY CURRENT vs DELAY TIME

X2 Hi_62ns Delay

X2 Hi_62ns Delay X2 Hi_0ns Delay

X2 Low_62ns Delay
X2 Hi_0ns Delay

X2 Low_62ns Delay

X2 Low_0ns Delay

X2 Low_0ns Delay

FIGURE 9. ISUPPLY+ vs VSUPPLY+ FIGURE 10. ISUPPLY- vs VSUPPLY-

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January 12, 2012
EL9115

Typical Performance Curves (Continued)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD CONDUCTIVITY TEST BOARD - QFN EXPOSED
1.2 DIEPAD SOLDERED TO PCB PER JESD51-5
4.0
1.0 3.5
POWER DISSIPATION (W)

833mW

POWER DISSIPATION (W)

QF
0.8 3.0 J N2
A= 0
QF 32
J N2 2.5 °C
/W
A=
0.6 15 0
0° 2.0
C/
W
0.4 1.5

0.2 1.0

0.5
0
0 25 50 75 85 100 125 150 0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE TEMPERATURE

1 19 17 18 16
TESTR

TESTB

TESTG
VSP

VSPO
CENABLE 7

2 R_IN
+ DELAY LINE
R_OUT 15
+

4 G_IN
+ DELAY LINE
G_OUT 13
+

6 B_IN
+ DELAY LINE
B_OUT 11
+
9 SDATA X2 20
10 SCLOCK CONTROL LOGIC
8 NSENABLE
VSMO

GND
GND

VSM

[BOTTOM PLATE]
3 5 C 12 14

FIGURE 13. EL9115 BLOCK DIAGRAM

FN7441 Rev 7.00 Page 6 of 10

January 12, 2012
EL9115

Applications Information TABLE 1. SERIAL BUS DATA

EL9115 is a triple analog delay line receiver that allows skew vwxyz DELAY
compensation between any three high frequency signals. This 00000 0
part compensates for time skew introduced by a typical CAT-5
00001 2
cable with differing electrical lengths on each pair. The EL9115
can be independently programmed via SPI interface in steps of 00010 4
2ns up to 62ns total delay on each channel while achieving 00011 6
over 80MHz bandwidth.
00100 8
Figure 13 shows the EL9115 block diagram. The three analog 00101 10
inputs are ground reference single-ended signals. After the
00110 12
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass filter 00111 14
introducing 2ns delay. In addition to time delay, each filter block 01000 16
also introduces some low pass filtering. As a result, the
01001 18
bandwidth of the signal path decreases from 120MHz at 0ns
delay setting to 80MHz at the maximum delay setting, as 01010 20
shown in Figure 1 of the “Typical Performance Curves” on 01011 22
page 4. 01100 24
In addition to delay, the extra amplifiers in the signal path also 01101 26
introduce offset voltage. The output offset voltage can shift by
01110 28
100mV for X2 high setting and 50mV for X2 low.
01111 30
In operation, it is best to allocate the most delayed signal 0ns
10000 32
delay and then increase the delay on the other channels to
bring them into line. This will result in the lowest power and 10001 34
distortion solution to balancing delays. 10010 36

Power Dissipation 10011 38

As the delay setting increases, additional filter blocks turn on 10100 40

and insert into the signal path. For each 2ns of delay per 10101 42
channel, VSP current increases by 0.9mA while VSM does not
10110 44
change significantly. Under the extreme settings, the positive
supply current reaches 140mA and the negative supply current 10111 46
can be 35mA. Operating at ±5V power supply, the total power 11000 48
dissipation is as shown in Equation 1: 11001 50
PD = 5  140mA + 5  35mA = 875mW (EQ. 1)
11010 52
JA required for long term reliable operation can be calculated. 11011 54
This is done using Equation 2: 11100 56
 JA =  T J – T A   PD = 57 C  W (EQ. 2)
11101 58

where: 11110 60

TJ is the maximum junction temperature (+135°C) 11111 62

NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
TA is the maximum ambient temperature (+85°C) Green register - ab = 10; Blue register - ab = 11; vwxyz selects delay.
For a 20 Ld package in a proper layout PCB heat-sinking
copper area, 40°C/W JA thermal resistance can be achieved. Serial Bus Operation
To disperse the heat, the bottom heat-spreader must be On the first negative clock edge after NSEnable goes low, read
soldered to the PCB. Heat flows through the heat-spreader to the input from DATA (Figure 14). This DATA level should be 0
the circuit board copper then spreads and convects to air. (write into registers); READ is not supported. Read the next
Thus, the PCB copper plane becomes the heatsink (see two data bits on subsequent negative edges and interpret them
TB389). This has proven to be a very effective technique. A as the register to be filled. Reg 01 = R, 02 = G, 03 = B, 00 test
separate application note, which details the 20 Ld QFN PCB use. Read the next five bits of data and send them to register.
design considerations, is available. At the end of each block of 8 bits, any further data is treated as
being a new word. Data entered is shifted directly to the final

FN7441 Rev 7.00 Page 7 of 10

January 12, 2012
EL9115

registers as it is clocked in. Initial value of all registers on For the logic to work correctly, A and B must have a period of
power-up is 0. It is the user's responsibility to send complete overlap while they are high (a delay longer than the pulse width
patterns of 8 clock cycles, even if the first bit is set to 1. If less cannot be measured).
than 8 bits are sent, data will only be partially shifted through
Signals A and B are derived from the video input by comparing
the registers. The pattern of 8 starts with NSEnable going low,
the video signal with a slicing level, which is set by an internal
so it is good practice to frame each word within an NS enable
DAC. This enables the delay to be measured either from the
burst.
rising edges of sync-like signals encoded on top of the video or
from a dedicated set-up signal. The outputs can be used to set
Test Pins
the correct delays for the signals received.
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a The DAC level is set through the serial input by bits 1 through 4
duration of the overlap between the inputs, as shown in Figure directed to the test register (00). Table 2 shows the settings for
15: the DAC slice level bits.

Test_R pulse = Red out (A) wrt Green out (B) Test Mode
Bit zero of the test register is set to 0 for normal operation. If it
Test_G pulse = Green out wrt Blue out
is set to 1 then the device is in Test Mode. In Test Mode, the
Test_B pulse = Blue out wrt Red out DAC voltage is directed to the Green channel output, while for
the Red and Blue channels, the test outputs are now pulses of
Averaging the current gives a direct measure of the delay
current which are generated by looking at the delay between
between the two edges. When A precedes B the current pulse
the input and output of the channel. They thus enable the delay
is +50µA, and the output voltage goes up. When B precedes A,
to be measured.
the pulse is -50µA.

NSENABLE

SCLOCK

0 A1 A0 D4 D3 D2 D1 D0 SDATA

a b v w x y z

FIGURE 14. SERIAL DATA TIMING

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EL9115

TABLE 2. DAC SLICE LEVEL SETTINGS

1 D
SET
Q
X
ENABLES +50µA DELAY
A CURRENT wxyz DAC/mV
CLR Q
1000 -400
1001 -350
R
1010 -300

1 SET Y 1011 -250

D Q
B ENABLES -50µA DELAY
CURRENT
1100 -200
CLR Q
1101 -150
1110 -100
A 1111 -50
0000 0
B
0001 50
0010 100
R
0011 150
0100 200
X
0101 250
0110 300
Y
0111 350
A AND B REPRESENT THE VIDEO INPUTS BEING COMPARED. THE THREE
COMBINATIONS FOR A-B ARE RED-GREEN, RED-BLUE, OR GREEN-BLUE.
NOTE: Test Register word = 000wxyzt. If t = 1 test mode else
normal. wxyz fed to DAC. z is LSB
FIGURE 15. DELAY DETECTOR

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modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com

FN7441 Rev 7.00 Page 9 of 10

January 12, 2012
EL9115

Quad Flat No-Lead Plastic Package (QFN) L20.5x5C

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
A D B (COMPLIANT TO JEDEC MO-220)

(N-1)
(N-2)
MILLIMETERS

N
SYMBOL MIN NOMINAL MAX NOTES
1 A 0.80 0.90 1.00 -
2 PIN #1 A1 0.00 0.02 0.05 -
3 I.D. MARK E
b 0.28 0.30 0.32 -
c 0.20 REF -
(2X) D 5.00 BASIC -
0.075 C
(N/2)
D2 3.70 REF 8
E 5.00 BASIC -
(2X)
0.075 C

E2 3.70 REF 8
TOP VIEW
e 0.65 BASIC -
L 0.35 0.40 0.45 -
N 20 4
e 0.10 C
C ND 5 REF 6
NE 5 REF 5
SEATING
PLANE Rev. 0 6/06
0.08 C NOTES:
SEE DETAIL “X”
N LEADS AND
EXPOSED PAD
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
0.01 M C A B
5. NE is the number of terminals on the “E” side of the package
(N-2)
(N-1)

b PIN #1 I.D.
L (or Y-direction).
N

N LEADS 3 6. ND is the number of terminals on the “D” side of the package

1
(or X-direction). ND = (N/2)-NE.
2
3 7. Inward end of terminal may be square or circular in shape with
(E2) radius (b/2) as shown.
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
NE 5
9. One of 10 packages in MDP0046
(N/2)

(D2) 7

BOTTOM VIEW

C (c) 2
A

(L)
A1
N LEADS
DETAIL “X”

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January 12, 2012