Introduction to VLSI Design 113-2
Introduction to VLSI Design
113-2
Devices and the Characterizations
Chung-An Shen(沈中安)
Universidad Politécnica Taiwán Paraguay
National Taiwan University of Science and Technology
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Introduction to VLSI Design 113-2
Introduction
The physical structure of an nMOS transistor.
Gate, source, drain, substrate, channel.
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Introduction to VLSI Design 113-2
Introduction
MOS junction operating modes.
Accumulation mode
• A negative voltage is applied
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Introduction to VLSI Design 113-2
Introduction
MOS junction operating modes.
Depletion mode
• A small positive voltage is applied
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Introduction to VLSI Design 113-2
Introduction
MOS junction operating modes.
Inversion mode
• A higher positive potential exceeding a threshold value Vt
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Introduction to VLSI Design 113-2
Introduction
Vg
Mode of operation depends on Vg, Vd, Vs + +
Vgs Vgd
• Vgs = Vg – Vs
- -
• Vgd = Vg – Vd Vs Vd
- +
• Vds = Vd – Vs = Vgs - Vgd Vds
Source and drain are symmetric diffusion terminals
• By convention, source is terminal at lower voltage
• Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
• Cutoff
• Linear
• Saturation
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Introduction to VLSI Design 113-2
Introduction
MOS operating regions
Cutoff region
• Vgs < 𝑉𝑡
• Ids = 0
• No channel
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Introduction to VLSI Design 113-2
Introduction
MOS operating regions
Linear region
• Channel formed, current flows by drift of electrons (majority carriers)
• Ids increases with Vds
• Similar to linear resistors
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Introduction to VLSI Design 113-2
Introduction
MOS operating regions
Saturation region
• Channel pinches off
• Ids is independent of Vds
• Similar to current source
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Introduction to VLSI Design 113-2
I-V Characteristics
In linear region, MOS transistor has channel inversion and
majority carriers conduct current in the form of drifting by
electric field.
In linear region, the current Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?
Speed of carriers depends on
• Electric field
• Effective mass
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Introduction to VLSI Design 113-2
I-V Characteristics
Channel charge.
MOS structure looks like parallel plate capacitor while operating in
inversions
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Introduction to VLSI Design 113-2
I-V Characteristics
nMOS I-V summary.
Cutoff region, 𝑉 𝑉
Linear region, 𝑉 𝑉
Saturation region, 𝑉 𝑉
β is a coefficient related to the device characteristics. 16
Introduction to VLSI Design 113-2
I-V Characteristics
An example. 2.5
Vgs = 5
assume a 0.6 m process 2
tox = 100 Å 1.5 Vgs = 4
Ids (mA)
μ = 350 cm2/V*s
1
Vt = 0.7 V Vgs = 3
Plot Ids vs. Vds 0.5
Vgs = 2
Vgs = 0, 1, 2, 3, 4, 5 0
Vgs = 1
0 1 2 3 4 5
Use W/L = 4/2
Vds
W 3.9 8.85 1014 W W
Cox 350 8 120 μA/V 2
L 100 10 L L
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Introduction to VLSI Design 113-2
I-V Characteristics
All dopings and voltages are inverted for pMOS
• Source is the more positive terminal
Mobility p is determined by holes
Typically 2-3x lower than that of electrons mn
Provide less current than nMOS transistors
2-3 times larger (W/L) needed for pMOS to achieve the same level of current
Thus pMOS must be wider to provide same current
0
V g s = -1
V g s = -2
-0 .2
V g s = -3
Ids (mA)
-0 .4
V g s = -4
-0 .6
V g s = -5
-0 .8
-5 -4 -3 -2 -1 0
V ds
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Introduction to VLSI Design 113-2
CMOS circuit example
Determine 𝑉 and 𝑉 for the E-MOSFET circuit in figure.
Assume this particular MOSFET has β = 100 and 𝑉 2𝑉.
𝑉 𝑉 24𝑉 3.13𝑉
.
β/2 50
𝐼 𝑉 𝑉 50 3.13 2 63.8𝑚𝐴
𝑉 𝑉 𝐼 𝑅 24𝑉 63.8𝑚𝐴 200Ω 11.2𝑉
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Ideal vs. Simulated nMOS I-V Curves
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Electric Fields Effects
Vertical electric field:
• Attracts carriers into channel
• Long channel:
Lateral electric field:
• Accelerates carriers from drain to source
• Long channel:
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Mobility Degradation
High Evert effectively reduces mobility
Mobility decreases as 𝑣 𝜇𝐸
• Temperature or doping concentration increases
• The vertical electric field increases (Collision with oxide interface)
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Velocity Saturation
At high lateral electric field, carrier velocity will cease to scale linearly
• Carriers scatter off atoms in silicon lattice
• Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
• Better model
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Velocity Saturation
As the technology advances and the channel gets shorter, velocity
saturates at even smaller 𝑉
Revision on the 𝐼 formula (𝛼-power law model)
• 𝛼: velocity saturation index
• 𝛼 2 is the non-saturation case
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion 𝐿 region grows with reverse bias
Higher 𝑉 shortens the length of the channel
𝐿 𝐿 𝐿
Shorter Leff gives more current
Ids increases with Vds
Even in saturation
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
In the saturation region, as 𝑉 ↑
𝐿 ↓
𝐸↑
𝐼 ↑
The drain current is thus affected
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Threshold Voltage Effects
Ideal models assume 𝑉 is constant
In fact, 𝑉 weakly depends on
• Body voltage: body effect
• Drain voltage (drain-induced barrier lowering, DIBL)
𝑉 decreases with 𝑉
𝐼 increases with 𝑉
• Channel length (short channel effect)
𝑉 increases with the channel length
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Leakage
Even when transistors are nominally OFF, they leak small amount of
current
Subthreshold conduction
• Conduction between source and drain
Gate leakage
• Leakage from the gate to body
Junction leakage
• Leakage from source/drain to body
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Introduction to VLSI Design 113-2
Non-ideal I-V Effects
Temperature Dependence
As 𝑇 ↑
Mobility ↓
Threshold voltage ↓
Junction leakage ↑
Subthreshold leakage ↑
OFF current ↑
ON current ↓
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Introduction to VLSI Design 113-2
DC Transfer Characteristics
Beta Ratio Effects
Inverter with different beta ratio 𝑟 is known as the skewed inverter.
The gate threshold voltage (input threshold) 𝑉 𝑉 𝑉 is
controlled by the ratio
1: unskewed, the inverter has the same current sourcing and sinking capability,
i.e., the nMOS is as strong as the pMOS
1: HI-skewed, stronger
pMOS, higher switching threshold
1: LO-skewed, weaker
pMOS, lower switching threshold
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Introduction to VLSI Design 113-2
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