VE24P23 – ANALOG AND DIGITAL CMOS VLSI DESIGN

LABORATORY

M.Tech. VLSI DESIGN AND EMBEDDED SYSTEMS

Department

Of

ELECTRONICS AND COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNICAL TEACHERS

TRAINING AND RESEARCH

Deemed to be university,

(Ministry of Education, Government of India) Taramani, Chennai.

SEPTEMBER 2025
 NATIONAL INSTITUTE OF TECHNICAL TEACHERS TRAINING
AND RESEARCH

Deemed to be university,

(Ministry of Education, Government of India)

Taramani, Chennai.

BONAFIDE CERTIFICATE

Certified that this is a bonafide record of the work done by

Mr/Ms__ Register Number _
studying 03 semester M.Tech degree programme in the
department of Electronics and Communication Engineering for
the subject Embedded Automation Laboratory.

SIGNATURE SIGNATURE
Dr. P. Sivashankar Ph.D. Dr. P. Sivashankar Ph.D.
HEAD OF THE DEPARTMENT SUPERVISOR
Department of Electronics and Department of Electronics and
Communication Engineering, Communication Engineering,
National Institute of Technical National Institute of Technical
Teachers Training and Teachers Training and
Research (Ministry of Research (Ministry of
Education, Government of Education, Government of
India) India)
Taramani, Chennai. Taramani, Chennai

Submitted for the viva-voce held at National Institute of Technical

Teachers Training and Research оn _ _ _ _ _ _ _ _ _ _.

INTERNAL EXAMINER EXTERNAL E X AM IN E R

 LIST OF EXPERIMENTS

Expt. Page
Date Title of the Experiment Signature
No. No.
Part I: Module Design and Simulation using SPICE simulator
Design of Common Source
1. 11
Amplifier
Design of Cascade and Cascode
2. 15
amplifiers
3. Design of current Mirrors 23
Design of differential pair amplifier
4. 27
with active load
Design of telescopic amplifier
5. 31
circuit
Design of two-stage amplifier
6. 35
circuit
Part II: Module Design using FPGA Implementation (Verilog/VHDL)
1. Adders and Subtractors 43
2. Multiplier (8-bit) 49
3. ALU circuit 53
4. Flip-flops 59
5. Universal Shift Registers 69
Asynchronous and synchronous
6. 77
Counters
Finite State Machine
7. 87
(Moore/Mealy) and its applications
8. Memories1: Any microcontroller 93

5
6
 Part I: Module Design and
Simulation using SPICE simulator

7
8
9
Experiment 1: Common Source Amplifier

Circuit Diagram

10
Date:
Common Source Amplifier
Exp No: 01

Aim:

To design and simulate a common-source JFET amplifier using

SPICE, obtain the midband voltage gain, verify the 180° phase inversion,
and observe the effect of coupling/bypass capacitors on the frequency
response.

Software Tools Required:

1. SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

2. JFET Model (2N5458/2N3458)
3. Virtual oscilloscope/AC analysis plots

Theory:

The common-source amplifier is one of the basic JFET amplifier

configurations. The input signal is applied at the gate, and the output is
taken from the drain, with the source connected to ground (AC-wise). It
provides voltage amplification with a 180° phase shift. Biasing is
achieved using a resistor divider network to fix the gate voltage. The
source resistor provides stability, and the bypass capacitor increases AC
gain. Coupling capacitors (C1, C2) block DC and limit low-frequency
response.

Circuit Used :

1. Supply: VCC = 30 V
2. JFET: 2N5458/2N3458
3. Drain Resistor: R1 = 2.2 kΩ
4. Source Resistor: R2 = 10 kΩ (bypassed by C3 = 10 µF)
5. Gate Bias Divider: R3 = 2 MΩ, R4 = 1 MΩ
6. Input Coupling Capacitor: C2 = 10 µF, Vin = 120 mVrms, 60 Hz
7. Output Coupling Capacitor: C1 = 10 µF

11
Output Waveform

12
Procedure:

1. Draw the circuit schematic in the SPICE simulator with the given
values.
2. Run DC operating point (.op) analysis to obtain ID, VD, VS, and VG.
3. Run transient simulation with sinusoidal input and observe the
outputwaveform.
4. Measure input and output amplitudes and calculate voltage gain.
5. Run AC sweep analysis to obtain frequency response and identify
midband gain, low-frequency cutoff (fL), and high-frequency roll-off.
6. Repeat the experiment with and without the bypass capacitor (C3) and
compare gains.

Result :

The common-source amplifier was successfully simulated. The output

waveform is amplified and phase-shifted by 180° relative to the input.

13
Experiment 2: Cascade Amplifier

Circuit Diagram

14
Date:
Cascade Amplifier
Exp No: 02(a)

Aim:

To design and simulate a two-stage cascade JFET amplifier using

SPICE, to observe the increase in voltage gain compared to a single stage,
and verify the overall phase inversion and frequency response.

Software Tools Required:

1. SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

2. JFET Model (2N5458/2N3458)
3. Virtual oscilloscope/AC analysis plots.

Theory:

A cascade amplifier consists of two or more amplifier stages connected in

series. Here, two common-source JFET amplifiers are connected so that
the output of the first stage is coupled to the input of the second stage.
The main advantages are:
1. Overall voltage gain is the product of individual stage gains.
2. Increased amplification with relatively low input signal.
3. Each stage provides 180° phase shift; hence, two stages result in an
overall 360° phase shift (in-phase with input).
Coupling capacitors (C1, C4, C5) block DC and allow AC signals, while
bypass capacitors (C2, C3) increase gain by reducing source
degeneration.

Circuit Used:

1. Supply: VCC = 30 V
2. Transistors: 2N5458/2N3458 JFETs (Q1, Q2)
Stage 1:
- Drain Resistor R1 = 2.2 kΩ
- Source Resistor R4 = 10 kΩ (bypassed by C3 = 10 µF)
- Gate Bias: R5 = 100 kΩ, R6 = 10 kΩ
- Coupling Capacitors: C1 = 10 µF, C4 = 10 µF

15
Output Waveform

16
Stage 2:
- Drain Resistor R2 = 2.2 kΩ, Load Resistor R9 = 2.2 kΩ
- Source Resistor R3 = 10 kΩ (bypassed by C2 = 10 µF)
- Gate Bias: R7 = 100 kΩ, R8 = 10 kΩ
- Output Coupling Capacitor: C5 = 10 µF
3. Input: Vin = 5 mVrms, 60 Hz sinusoidal

Procedure:

1. Draw the cascade amplifier circuit in the SPICE simulator with given
component values.
2. Run DC operating point analysis to ensure both stages are properly
biased.
3. Apply a sinusoidal input (5 mVrms, 60 Hz) and perform transient
simulation.
4. Measure the input and final output waveforms using the oscilloscope.
5. Calculate the overall voltage gain (Av = Vout/Vin).
6. Run AC sweep analysis to plot frequency response and compare it with
single-stage amplifier.
7. Observe the phase shift: two stages result in ~360° (in-phase with
input).
8. Note the effect of bypass capacitors (C2, C3) on gain improvement.

Result:

The cascade amplifier was successfully simulated, and the output gain
was higher than a single stage, in-phase with the input.

17
Experiment 2: Cascode Amplifier

Circuit Diagram

18
Date:
Cascode Amplifier
Exp No: 02(b)

Aim:

To design and simulate a cascode amplifier using SPICE, to observe its

high voltage gain, improved bandwidth, and higher output resistance
compared to a single common-source amplifier.

Software Tools Required:

SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

JFET Model (2N5458/2N3458)
Virtual oscilloscope/AC analysis plots.

Theory:

A cascode amplifier combines a common-source (or common-emitter)

stage with a common-gate (or common-base) stage. The first transistor
provides transconductance, while the second transistor increases output
resistance, thus improving overall voltage gain and bandwidth.

Advantages:
• High voltage gain (product of gm and high Rout).
• Higher bandwidth due to reduced Miller effect.
• Better input-output isolation.

In this circuit, Q4 (common-source) drives Q3 (common-gate). Coupling

capacitors (C1, C2) block DC, and resistors provide proper biasing.

Circuit Used:

1. Supply: VCC = 30 V
2. Transistors: BFW11 (Q3, Q4)
3. Drain Load: R2 = 3.9 kΩ
4. Source Resistor: R1 = 330 Ω (bypassed by C2 = 1 µF)
5. Bias Network: R3 = 30 kΩ, R4 = 10 kΩ, R5 = 10 MΩ
6. Coupling Capacitors: C1 = 1 µF, C2 = 1 µF
7. Input: Small AC signal source (few mV amplitude, sinusoidal)
8. Output: Taken at drain of Q3 through oscilloscope

19
Output Waveform

20
Procedure:

1. Draw the cascode amplifier circuit in the SPICE simulator using given
values.
2. Run DC operating point analysis to verify bias voltages of Q3 and Q4.
3. Apply a small sinusoidal input and run transient simulation.
4. Observe input and output waveforms using the oscilloscope.
5. Measure input and output amplitudes; calculate voltage gain Av =
Vout/Vin.
6. Perform AC sweep analysis to determine midband gain and bandwidth
improvement.
7. Compare results with single common-source amplifier to highlight
advantages of cascode configuration.

Result:

The cascode amplifier was successfully simulated, and it showed higher

gain with improved bandwidth

21
Experiment 3: Current Mirrors

Circuit Diagram

22
Date:
Current Mirrors
Exp No: 03

Aim:

To design and simulate a MOSFET-based current mirror using SPICE

and verify that the output currents are equal to the reference current,
demonstrating current replication and biasing applications.

Software Tools Required:

• SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

• MOSFET Model (e.g., 100 µm/100 µm W/L ratio)
• Multimeters/virtual instruments to measure current values

Theory:

A current mirror is a circuit designed to copy (mirror) current from one

active device to another, maintaining constant current independent of
load resistance. It is widely used in analog circuits for biasing and as an
active load.

Working principle:

• Q2 is diode-connected to set a reference current Iref.

• This current is mirrored to Q1 and Q3, providing nearly equal output
currents.
• The accuracy depends on matching of transistors and output
resistance.

Key Features:

• Provides biasing without large resistors.

• Ensures equal currents in multiple branches.
• Variants include Wilson current mirror, Cascode current mirror for
higher accuracy.

Circuit Used:

Supply: VCC = 12 V
Transistors: MOSFETs with W/L = 100 µm/100 µm (Q1, Q2, Q3)
Resistors: R1 = 2 kΩ (reference branch), R2 = 500 Ω (output branch), R3
= 1 kΩ (output branch)

23
Output Waveform

24
Connections:
• Q2 is diode-connected to generate reference current (Iref).
• Q1 and Q3 replicate the reference current to their drains.
Measurement: Multimeters connected to measure Iref and mirrored
currents.

Procedure:

1. Construct the current mirror circuit in the SPICE simulator.

2. Connect Q2 in diode configuration (gate and drain shorted).
3. Apply VCC = 12 V and run DC operating point analysis.
4. Measure reference current through R1.
5. Observe and record output currents through R2 and R3.
6. Compare measured currents to verify current mirroring action.
7. Analyze variation in output current with different load resistances.
8. Repeat with different W/L ratios for improved accuracy.

Result:

The current mirror was successfully simulated, and the output currents
matched the reference current

25
Experiment 5: Differential Amplifier with Active Load

Circuit Diagram

26
Date:
Differential Amplifier with Active Load
Exp No: 04

Aim:

To design and simulate a BJT-MOSFET based differential amplifier with

active load using SPICE, and to study its differential-mode gain,
common-mode gain, and Common-Mode Rejection Ratio (CMRR).

Software Tools Required:

• SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

• BJT Models (2N2222A, 2N3702)
• MOSFET Models (W/L = 100 µm/100 µm)
• Virtual oscilloscope and function generators.

Theory:

A differential amplifier amplifies the difference between two input signals

while rejecting any signal common to both inputs. It forms the input
stage of operational amplifiers.

With active load (current mirror), the differential amplifier achieves:

• Higher gain compared to resistive load.
• Better output swing and linearity.
• High CMRR (ability to reject common-mode signals).

Key Parameters:

• Differential Gain (Ad) = Vo_diff / (V1 - V2)

• Common-Mode Gain (Acm) = Vo_common / Vcm
• CMRR = Ad / Acm (ideally very high).

Circuit Used:
Supply: VCC = +15 V, VSS = -15 V
Transistors:
• Input Pair: Q1 (2N3702), Q2 (2N2222A)
• Current Mirror Load: Q7, Q8 (2N3702, 2N2222A)
• Current Source: Q3, Q4, Q5, Q6 (MOSFETs, W/L = 100 µm/100 µm)
Inputs: V1 = 50 mVrms, 60 Hz; V2 = 50 mVrms, 180° phase shifted
Load Resistor: R1 = 500 Ω
Output: Taken at collector of Q2 through oscilloscope.

27
Output Waveform

28
Procedure:

1. Construct the differential amplifier with active load in SPICE.

2. Apply two input signals: V1 (0°) and V2 (180° phase difference).
3. Run DC operating point analysis to verify bias currents of BJTs and
MOSFETs.
4. Run transient simulation with AC inputs and observe output
waveform.
5. Measure differential gain (Ad) from output amplitude versus input
difference.
6. Apply identical common-mode signals and measure common-mode
gain (Acm).
7. Calculate CMRR = Ad / Acm.
8. Compare gain performance with resistive-load differential amplifier.

Result:

The differential amplifier was successfully simulated, and it amplified

differential signals while rejecting common-mode signals.
29
Experiment 5: Telescopic Amplifier Circuit

Circuit Diagram

30
Date:
Telescopic Amplifier Circuit
Exp No: 05

Aim:

To design and simulate a CMOS telescopic amplifier using SPICE and

analyze its voltage gain, output swing, and frequency response.

Software Tools Required:

• SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

• CMOS Transistor Models (e.g., BST100, 2N7000)
• Virtual oscilloscope and signal sources

Theory:

The telescopic amplifier is a high-gain single-stage CMOS operational

amplifier topology. It uses a differential input pair with cascode
transistors to increase output resistance, thereby achieving higher
voltage gain compared to a simple differential amplifier.

Advantages:
• High DC gain due to large output resistance.
• Low noise compared to multi-stage op-amps.
• Better linearity and improved CMRR.

Limitations:
• Limited output voltage swing due to stacked transistors.
• Requires higher supply voltage for proper operation.

Circuit Used:

Supply: VDD = +12 V, VSS = 0 V, bias voltages V3 = V4 = 2.5 V, V5 = 12

V
Transistors: MOSFETs (BST100, 2N7000)
Input Pair: Q1, Q3 with differential inputs V1 = 120 Vrms (0°), V2 = 120
Vrms (180°)
Cascode Transistors: Q2, Q4, Q6, Q8
Current Source: Q7, Q9, Q10
Load Capacitor: C1 = 100 µF
Output: Taken from drain of cascode transistor via oscilloscope.

31
Output Waveform

32
Procedure:

1. Construct the telescopic amplifier circuit in the SPICE simulator with

the given parameters.
2. Apply a differential input signal: V1 (0°) and V2 (180°).
3. Run DC operating point analysis to verify transistor biasing.
4. Perform transient analysis with sinusoidal input and observe the
amplified output waveform.
5. Measure input and output voltages and calculate gain.
6. Run AC sweep analysis to determine frequency response, midband
gain, and bandwidth.
7. Compare results with a simple differential amplifier to highlight
improvements in gain.

Result:

The telescopic amplifier was successfully simulated, and it provided high

gain but limited output swing.

33
Experiment 6: Two-Stage Amplifier

Circuit Diagram:

34
Date:
Two-Stage Amplifier Circuit
Exp No: 06

Aim:

To design and simulate a two-stage amplifier using SPICE and study its
overall gain, phase response, and frequency response compared to a
single-stage amplifier.

Software Tools Required:

• SPICE Simulator (LTspice / Multisim / OrCAD PSpice)

• JFET Models (2N3458)
• Virtual oscilloscope and AC analysis tools.

Theory:

A two-stage amplifier is built by cascading two common-source amplifier

stages. The overall voltage gain is approximately the product of individual
stage gains:
Av_total ≈ Av1 × Av2

Advantages:
• Higher overall gain than a single stage.
• Better signal amplification for low-level inputs.

Coupling capacitors connect stages while blocking DC. Bypass capacitors

improve gain by reducing source degeneration. Stability can be ensured
with proper biasing and coupling design.

Phase: Each CS stage provides ~180° phase inversion, so overall two

stages give ~360° phase shift, meaning output is in-phase with input.

Circuit Used:

Supply: VCC = 30 V
Transistors: Q1, Q2 = 2N3458 (JFET)
Stage 1:
- Drain Resistor: R1 = 2.2 kΩ
- Source Resistor: R4 = 10 kΩ (bypassed by C3 = 10 µF)
- Gate Bias: R5 = 100 kΩ, R6 = 10 kΩ
- Input Coupling Capacitor: C4 = 10 µF

35
Output Waveform:

36
Stage 2:
- Drain Resistor: R2 = 2.2 kΩ, Load Resistor R9 = 2.2 kΩ
- Source Resistor: R3 = 10 kΩ (bypassed by C2 = 10 µF)
- Gate Bias: R7 = 100 kΩ, R8 = 10 kΩ
- Interstage & Output Coupling Capacitors: C1 = 10 µF, C5 = 10 µF
Input: Vin = 5 mVrms, 60 Hz sinusoidal
Output: Taken across load resistor R9 through oscilloscope

Procedure:

1. Construct the two-stage amplifier circuit in the SPICE simulator with

the given parameters.
2. Perform DC operating point analysis to confirm correct biasing of Q1
and Q2.
3. Apply an AC input (5 mVrms, 60 Hz) and run transient simulation.
4. Measure input and output amplitudes and calculate overall gain.
5. Run AC sweep analysis to determine midband gain, low and high
frequency cutoffs.
6. Compare results with single-stage amplifier in terms of gain and
bandwidth.
7. Verify that the overall phase shift is ~360° (output in-phase with
input).

Result:

The two-stage amplifier was successfully simulated, and it gave higher

gain than a single stage, with the output in-phase with the input.
37
38
Part II: Module Design using FPGA
Implementation (Verilog/VHDL)

39
40
41
Experiment 1:

Verilog Code: Adder/Subtractor

module AdderSubtractor (
input [3:0] A, // First operand
input [3:0] B, // Second operand
input op, // Operation: 0 = Add, 1 = Subtract
output reg [4:0] Result // 5-bit result (to include carry/borrow)
);

always @(*) begin

if (op == 0) begin
Result = A + B; // Addition
end else begin
Result = A - B; // Subtraction
end
end

endmodule

42
Date:
Adders and Subtractors
Exp No: 01

Aim:

To design and simulate a 4-bit Adder/Subtractor using Verilog HDL and

verify its functionality through simulation.

Software Tools Required:

 Xilinx ISE Project Navigator

 ModelSim

Theory:

1. Adders and subtractors are the fundamental arithmetic building

blocks in digital systems.
2. A half-adder adds two 1-bit numbers and gives Sum and Carry
outputs.
3. A full-adder extends this by including a carry input.
4. A subtractor can be designed similarly, with a borrow logic.
5. In Verilog, addition and subtraction are performed using the + and
- operators.
6. This experiment combines both operations into one module, with a
control signal (op) deciding whether the operation is Addition (op
= 0) or Subtraction (op = 1).

Procedure:

1. Write the Verilog code for the Adder/Subtractor module.

2. Develop the testbench to apply different input cases.
3. Compile and simulate the design in Xilinx ISE or ModelSim.
4. Observe the output waveforms for addition and subtraction.
5. Verify correctness by comparing with manual calculations.

43
Verilog Testbench: Adder/Subtractor

module test_add_sub_v;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg op;

// Outputs
wire [4:0] Result;

// Instantiate the Unit Under Test (UUT)

AdderSubtractor uut (
.A(A),
.B(B),
.op(op),
.Result(Result)
);

initial begin
// Initialize Inputs
A = 0; B = 0; op = 0;

#100; A = 4; B = 10; op = 0; // Addition: 4 + 10

#100; A = 8; B = 6; op = 0; // Addition: 8 + 6
#100; A = 10; B = 10; op = 1; // Subtraction: 10 - 10
#100; A = 11; B = 7; op = 1; // Subtraction: 11 - 7
#100; A = 8; B = 12; op = 1; // Subtraction: 8 - 12
#100; // End of simulation
end

endmodule

44
45
Simulation output: Adder/Subtractor

46
Result

The 4-bit Adder/Subtractor design was successfully simulated and

verified using Verilog HDL.

47
Experiment 2:

Verilog Code: Multiplier

module Multiplier8bit (
input [7:0] A, // First 8-bit operand
input [7:0] B, // Second 8-bit operand
output reg [15:0] OUT // 16-bit product
);
always @(*) begin
OUT = A * B; // Multiply A and B
end
endmodule

Verilog Testbench:

module test_multiplier_v;
// Inputs
reg [7:0] A;
reg [7:0] B;

// Outputs
wire [15:0] OUT;

// UUT
Multiplier8bit uut (
.A(A),
.B(B),
.OUT(OUT)
);

initial begin
// Initialize inputs
A = 0; B = 0;

#100; A = 5; B = 10; // Expected = 50

#100; A = 16; B = 45; // Expected = 720
#100; A = 128; B = 128; // Expected = 16384
#100; A = 100; B = 100; // Expected = 10000
#100; A = 100; B = 0; // Expected = 0
#100; A = 89; B = 100; // Expected = 8900
#100; $finish;
end
endmodule

48
Date:
Multiplier (8-bit)
Exp No: 02
Aim

Design and simulate an 8-bit unsigned multiplier using Verilog HDL

and verify the 16-bit product in simulation.

Software Tools Required:

 Xilinx ISE Project Navigator

 ModelSim

Theory

1. A multiplier performs the arithmetic operation of multiplication.

2. Two 8-bit numbers when multiplied produce a 16-bit product.
3. In Verilog, the * operator is used to implement multiplication.
4. The design is combinational; output changes immediately
whenever inputs change.

Procedure

1. Write the Verilog code for the 8-bit multiplier module.

2. Develop the testbench to apply different input values.
3. Compile and simulate the design in Xilinx ISE or ModelSim.
4. Observe the 16-bit product output in the waveform window.
5. Verify correctness by comparing with manual multiplication
results

49
Simulation output: Multiplier

50
Result

The 8-bit multiplier design was successfully simulated and verified

using Verilog HDL.

51
Experiment 3:

Verilog Code: ALU circuit

module ALU8bit (
input [7:0] A, B, // 8-bit inputs
input [3:0] control, // 4-bit control signal
output reg [7:0] result, // 8-bit output
output reg ov // carry/borrow/overflow flag for ADD/SUB
);
always @(*) begin
// Safe defaults to avoid inferred latches
result = 8'b0;
ov = 1'b0;

case (control)
4'b0000: begin // ADD (unsigned)
{ov, result} = {1'b0, A} + {1'b0, B}; // ov = carry-out
end
4'b0001: begin // SUB (unsigned)
{ov, result} = {1'b0, A} - {1'b0, B}; // ov = borrow-out
end
4'b0010: result = A & B; // AND
4'b0011: result = A | B; // OR
4'b0100: result = A << 1; // Shift left A by 1
4'b0101: result = A >> 1; // Shift right A by 1
default: result = 8'b00000000;
endcase
end
endmodule

52
Date:
ALU circuit
Exp No: 03
Aim:

To design and simulate an 8-bit ALU using Verilog HDL and verify its
arithmetic, logic, and shift operations.

Software Tools Required

 Xilinx ISE Project Navigator

 ModelSim

Theory:

1. An Arithmetic Logic Unit (ALU) is a digital circuit that performs

arithmetic and logical operations.
2. Operations are selected using a control signal.
3. Common operations:
 Addition and Subtraction
 Bitwise AND and Bitwise OR
 Shift Left and Shift Right
4. In Verilog, these are implemented using operators (+, -, &, |, <<,
>>).
5. The ALU is a combinational circuit; the output changes
immediately when inputs or control change.

Procedure:

1. Write the Verilog code for the 8-bit ALU module.

2. Write a testbench to apply different input values and control
signals.
3. Compile and simulate the design using Xilinx ISE or ModelSim.
4. Observe the output waveforms for each operation.
5. Verify correctness of results by comparing with expected manual
calculations.

53
Verilog Tesbench: ALU circuit

module tb_ALU8bit;
reg [7:0] A, B;
reg [3:0] control;
wire [7:0] result;
wire ov;

// Instantiate the UUT

ALU8bit uut (
.A(A),
.B(B),
.control(control),
.result(result),
.ov(ov)
);

initial begin
$display("time A B ctrl result ov");
$monitor("%4t %3d %3d %b %3d %b",
$time, A, B, control, result, ov);

// Addition
A = 8'd10; B = 8'd5; control = 4'b0000; #10; // result=15, ov=0
A = 8'd250;B = 8'd10; control = 4'b0000; #10; // result=4, ov=1
(carry)

// Subtraction
A = 8'd10; B = 8'd5; control = 4'b0001; #10; // result=5, ov=0 (no
borrow)
A = 8'd5; B = 8'd10; control = 4'b0001; #10; // result=251, ov=1
(borrow)

// Logic ops
A = 8'b10101010; B = 8'b11001100; control = 4'b0010; #10; //
AND
control = 4'b0011; #10; // OR

// Shifts
A = 8'b00010110; control = 4'b0100; #10; // A<<1
control = 4'b0101; #10; // A>>1

$finish;
end
endmodule

54
55
Simulation output: ALU circuit

56
Result

The 8-bit ALU design was successfully simulated and verified using
Verilog HDL.

57
Experiment 4: Flip flops

i) JK Flip-Flop

Verilog Code:

module jk_ff (
input clk,
input reset,
input J,
input K,
output reg Q
);
always @(posedge clk or posedge reset) begin
if (reset)
Q <= 0;
else begin
case ({J, K})
2'b00: Q <= Q; // Hold
2'b01: Q <= 0; // Reset
2'b10: Q <= 1; // Set
2'b11: Q <= ~Q; // Toggle
endcase
end
end
endmodule

58
Date:
Flip-flops
Exp No: 04

Aim

To design and simulate JK, D, and T Flip-Flops using Verilog HDL and
verify their operation through simulation.

Software Tools Required

 Xilinx ISE Project Navigator

 ModelSim

Theory

 Flip-Flops are basic sequential circuits used to store 1-bit of

data.
 They operate on the clock edge and may include asynchronous
reset.
 JK Flip-Flop:
o J=0, K=0 → Hold
o J=0, K=1 → Reset
o J=1, K=0 → Set
o J=1, K=1 → Toggle
 D Flip-Flop: On clock edge, output Q follows D.
 T Flip-Flop: When T=1, Q toggles; when T=0, Q holds.
 All are widely used in counters, registers, and sequential
systems.

Procedure

1. Write Verilog code for JK, D, and T Flip-Flops.

2. Write corresponding testbenches to apply clock, reset, and input
signals.
3. Compile and simulate the designs using Xilinx ISE or ModelSim.
4. Observe the waveforms and verify operation for all input
conditions.

59
i) JK Flip-Flop

Verilog Tesbench:

`timescale 1ns/1ps
module tb_jk_ff;
reg clk, reset, J, K;
wire Q;

// UUT
jk_ff uut (.clk(clk), .reset(reset), .J(J), .K(K), .Q(Q));

// Clock
initial begin clk = 0; forever #5 clk = ~clk; end

// Stimulus
initial begin
reset = 1; J = 0; K = 0; #12; reset = 0;

#10 J=0; K=0; // Hold

#10 J=0; K=1; // Reset
#10 J=1; K=0; // Set
#10 J=1; K=1; // Toggle
#10 J=0; K=1; // Reset
#10 J=1; K=1; // Toggle
#10 $stop;
end
endmodule

60
61
ii) D Flip-Flop

Verilog Code:

module d_ff (
input clk,
input reset,
input D,
output reg Q
);
always @(posedge clk or posedge reset) begin
if (reset)
Q <= 0;
else
Q <= D;
end
endmodule

Verilog Teshbench:

`timescale 1ns/1ps
module tb_d_ff;
reg clk, reset, D;
wire Q;

// UUT
d_ff uut (.clk(clk), .reset(reset), .D(D), .Q(Q));

// Clock
initial begin clk = 0; forever #5 clk = ~clk; end

// Stimulus
initial begin
reset = 1; D = 0; #12; reset = 0;

#10 D=0;
#10 D=1;
#10 D=0;
#10 D=1;
#10 D=1;
#10 D=0;
#10 $stop;
end
endmodule

62
63
iii) T Flip-Flop

Verilog Code:

module t_ff (
input clk,
input reset,
input T,
output reg Q
);
always @(posedge clk or posedge reset) begin
if (reset)
Q <= 0;
else if (T)
Q <= ~Q; // Toggle
else
Q <= Q; // Hold
end
endmodule

Verilog Testbench:

`timescale 1ns/1ps
module tb_t_ff;
reg clk, reset, T;
wire Q;

// UUT
t_ff uut (.clk(clk), .reset(reset), .T(T), .Q(Q));

// Clock
initial begin clk = 0; forever #5 clk = ~clk; end

// Stimulus
initial begin
reset = 1; T = 0; #12; reset = 0;
#10 T=0; // Hold
#10 T=1; // Toggle
#10 T=1; // Toggle
#10 T=0; // Hold
#10 T=1; // Toggle
#10 $stop;
end
endmodule

64
65
Simulated Output:

i) JK-Flipflop

ii) D Flip-Flop

iii) T-Flipflop:

66
Result

The JK, D, and T Flip-Flops were successfully simulated and verified

using Verilog HDL.

67
Experiment 5: Universal Shift Registers

Verilog Code:

module universal_shift_reg (
input wire clk, // Clock signal
input wire rst, // Active-high reset
input wire [1:0] sel, // 00-Hold, 01-Shift right, 10-Shift left, 11-
Parallel load
input wire [3:0] parallel_in, // Data for parallel load
input wire serial_in_left, // Serial data entering from left (for shift
right)
input wire serial_in_right, // Serial data entering from right (for
shift left)
output reg [3:0] q // Register value
);

always @(posedge clk or posedge rst) begin

if (rst)
q <= 4'b0000; // Reset clears register
else begin
case (sel)
2'b00: q <= q; // Hold
2'b01: q <= {serial_in_left, q[3:1]}; // Shift right
2'b10: q <= {q[2:0], serial_in_right}; // Shift left
2'b11: q <= parallel_in; // Parallel load
default: q <= q;
endcase
end
end

endmodule

68
Date:
Universal Shift Registers
Exp No: 05
Aim

To design and simulate a 4-bit Universal Shift Register using Verilog

HDL and verify its different modes of operation.

Software Tools Required

 Xilinx ISE Project Navigator – for design entry, syntax check, and
simulation
 ModelSim – for functional simulation and waveform verification

Theory

 A universal shift register can perform multiple operations

depending on the mode select (sel) inputs:
o 00 → Hold (no change)
o 01 → Shift Right (serial input enters from left)
o 10 → Shift Left (serial input enters from right)
o 11 → Parallel Load (all 4 bits loaded at once)
 It is widely used in data transfer, storage, and manipulation
circuits.
 Implementation uses D flip-flops with multiplexed inputs.

Procedure

1. Write the Verilog code for the 4-bit universal shift register.
2. Write a testbench to apply different sel values for Hold, Shift Right,
Shift Left, and Parallel Load.
3. Compile and simulate the design in Xilinx ISE or ModelSim.
4. Observe the waveform of output q under each mode of operation.
5. Verify correctness with expected results.

69
Verilog Testbench: Universal Shift Registers

`timescale 1ns/1ps
module tb_universal_shift_reg;

reg clk;
reg rst;
reg [1:0] sel;
reg [3:0] parallel_in;
reg serial_in_left;
reg serial_in_right;
wire [3:0] q;

// DUT
universal_shift_reg dut (
.clk(clk),
.rst(rst),
.sel(sel),
.parallel_in(parallel_in),
.serial_in_left(serial_in_left),
.serial_in_right(serial_in_right),
.q(q)
);

// Clock: 10ns period

always #5 clk = ~clk;

initial begin
// Initialize
clk = 0;
rst = 1; sel = 2'b00; parallel_in = 4'b0000;
serial_in_left = 0; serial_in_right = 0;

// Release reset
#10 rst = 0;

// Parallel load: 1010

sel = 2'b11; parallel_in = 4'b1010; #10;

// Hold
sel = 2'b00; #10;

// Shift right (serial_in_left = 1)

sel = 2'b01; serial_in_left = 1; #10;

// Shift right (serial_in_left = 0)

70
71
 sel = 2'b01; serial_in_left = 0; #10;

// Shift left (serial_in_right = 1)

sel = 2'b10; serial_in_right = 1; #10;

// Shift left (serial_in_right = 0)

sel = 2'b10; serial_in_right = 0; #10;

// Parallel load: 1100

sel = 2'b11; parallel_in = 4'b1100; #10;

// End
$stop;
end

endmodule

72
73
Simulated Output: Universal Shift Registers

74
Result

The 4-bit Universal Shift Register was successfully simulated and

verified using Verilog HDL.

75
Experiment: 6 Part A: 4-bit Synchronous Counter

Verilog Code:

module sync(clk, rst, count);

input clk;
input rst;
output reg [3:0] count;

always @(posedge clk) begin

if (rst)
count <= 4'b0000;
else
count <= count + 1'b1;
end
endmodule

Verilog Testbench:

module test_sync_v;
reg clk, rst;
wire [3:0] count;

// UUT
sync uut (.clk(clk), .rst(rst), .count(count));

always #50 clk = ~clk; // 100ns clock period

initial begin
clk = 0; rst = 1; #80; rst = 0; // Reset release
#1000;
rst = 1; #80; rst = 0;
end
endmodule

76
Date:
Asynchronous & Synchronous Counters
Exp No: 06(A)
Part A: 4-bit Synchronous Counter

Aim

To design and simulate a 4-bit synchronous counter using Verilog HDL

and verify its counting sequence.

Software Tools Required

 Xilinx ISE Project Navigator

 ModelSim

Theory

 In a synchronous counter, all flip-flops are triggered by the same

clock.
 Counting happens simultaneously at each flip-flop → fast and
reliable.
 Reset input initializes counter to zero.

Procedure

1. Write Verilog module for synchronous counter.

2. Write testbench to provide clock and reset.
3. Simulate and observe binary counting sequence.

77
Simulated Output: 4-bit Synchronous Counter

78
Result

The 4-bit synchronous counter was successfully simulated and verified.

79
Part B:

Verilog Code: 4-bit Asynchronous Counter

module asy(clk, rst, count);

input clk, rst;
output reg [3:0] count;

always @(posedge clk or posedge rst) begin

if (rst)
count[0] <= 1'b0;
else
count[0] <= ~count[0];
end

always @(posedge count[0] or posedge rst) begin

if (rst)
count[1] <= 1'b0;
else
count[1] <= ~count[1];
end

always @(posedge count[1] or posedge rst) begin

if (rst)
count[2] <= 1'b0;
else
count[2] <= ~count[2];
end

always @(posedge count[2] or posedge rst) begin

if (rst)
count[3] <= 1'b0;
else
count[3] <= ~count[3];
end
endmodule

80
Date:
Asynchronous & Synchronous Counters
Exp No: 06(B)
Part B: 4-bit Asynchronous Counter

Aim

To design and simulate a 4-bit asynchronous (ripple) counter using

Verilog HDL and verify its counting sequence.

Software Tools Required

 Xilinx ISE Project Navigator

 ModelSim

Theory

 In an asynchronous counter, the first flip-flop is triggered by the

main clock, while subsequent flip-flops are triggered by the output
of the previous stage.
 Results in propagation delay (ripple effect).
 Reset input initializes the counter.

Procedure

1. Write Verilog module for asynchronous counter.

2. Write testbench with clock and reset stimulus.
3. Simulate and observe ripple count sequence.

81
Verilog Testbench: 4-bit Asynchronous Counter

module asynn_v;
reg clk, rst;
wire [3:0] count;

// UUT
asy uut (.clk(clk), .rst(rst), .count(count));

always #50 clk = ~clk;

initial begin
clk = 0; rst = 1; #80; rst = 0;
#1000;
rst = 1; #80; rst = 0;
end
endmodule

82
83
Simulated Output: 4-bit Asynchronous Counter

84
Result

The 4-bit asynchronous counter was successfully simulated and

verified.

85
Experiment: 7

Verilog Code: Finite State Machine (Moore/Mealy) and its

applications

`timescale 1ns/1ps
module mealy_10_detector (
input clk,
input reset,
input in,
output reg out
);

parameter S0 = 1'b0; // Start

parameter S1 = 1'b1; // Got '1'

reg state, next_state;

// State register
always @(posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
state <= next_state;
end

// Next-state and output logic

always @(*) begin
next_state = state;
out = 0;
case (state)
S0: if (in) next_state = S1;
S1: if (~in) begin
next_state = S0;
out = 1; // Sequence "10" detected
end
endcase
end
endmodule

86
Date: Finite State Machine (Moore/Mealy)
Exp No: 07 and its applications

Aim

To design and simulate a Mealy FSM sequence detector that detects

the sequence “10”.

Software Tools Required

 Xilinx ISE Project Navigator

 ModelSim

Theory

 A Finite State Machine (FSM) has states, transitions, inputs, and

outputs.
 In a Mealy machine, output depends on present state + input.
 Here, FSM outputs 1 whenever the sequence “10” appears in the
input stream.

Procedure

1. Write Verilog code for FSM (Mealy sequence detector).

2. Write testbench to apply input bit sequence.
3. Simulate and observe output waveform.
4. Verify that output = 1 when sequence “10” occurs.

87
Verilog Testbench: Finite State Machine (Moore/Mealy) and its
applications

`timescale 1ns/1ps
module mealy_10_detector_tb;
reg clk, reset, in;
wire out;

// UUT
mealy_10_detector uut (.clk(clk), .reset(reset), .in(in), .out(out));

// Clock generation
initial begin clk = 0; forever #5 clk = ~clk; end

// Test sequence
initial begin
$monitor("Time=%0d | in=%b | out=%b", $time, in, out);

// Reset
reset = 1; in = 0; #10; reset = 0;

// Input sequence
in = 1; #10; // got '1'
in = 0; #10; // detected "10"
in = 1; #10;
in = 0; #10; // detected "10"
in = 0; #10;
in = 1; #10;
in = 1; #10;
in = 0; #10; // detected "10"

$finish;
end
endmodule

88
89
Simulated Output: Finite State Machine (Moore/Mealy) and its
applications

90
Result:

The Mealy FSM sequence detector was successfully simulated and

verified.

91
Experiment: 8

Verilog Code: Memories1: Any microcontroller

module memory_8x64K (
input clk, // Clock
input we, // Write Enable (1 = write, 0 = read)
input [2:0] addr, // 3-bit address (0 to 7)
input [7:0] din, // Data input
output reg [7:0] dout // Data output
);
// Declare memory (8 locations x 8 bits)
reg [7:0] mem [0:7];

always @(posedge clk) begin

if (we) begin
// Write operation
mem[addr] <= din;
end else begin
// Read operation
dout <= mem[addr];
end
end
endmodule

92
Date:
Memories1: Any microcontroller
Exp No: 08

Aim

To design and simulate an 8x64K memory module (RAM) using Verilog

HDL and verify read/write operations.

Software Tools Required

 Xilinx ISE Project Navigator

 ModelSim

Theory

 A memory stores binary data at specific addresses.

 RAM (Random Access Memory): allows both read and write
operations.
 Control signals:
o we = 1 → Write Enable (store din at address addr)
o we = 0 → Read (output data from memory at addr)
 In Verilog, memory is modeled using a reg array.
 Here, we implement 8 locations × 8-bit data width.

Procedure

1. Write the Verilog code for the 8x64K memory module.

2. Write the testbench to apply read and write operations.
3. Compile and simulate using Xilinx ISE/ModelSim.
4. Perform write operations by setting we=1.
5. Perform read operations by setting we=0 and check dout.
6. Verify that the data read matches the data written.

93
Verilog Testbench: Memories1: Any microcontroller

module test;
// Inputs
reg clk;
reg we;
reg [2:0] addr;
reg [7:0] din;

// Outputs
wire [7:0] dout;

// UUT
memory_8x64K uut (
.clk(clk),
.we(we),
.addr(addr),
.din(din),
.dout(dout)
);

// Clock generation
always #5 clk = ~clk;

initial begin
// Initialize
clk = 0; we = 0; addr = 0; din = 0;

// Write values into memory

#10 we = 1; addr = 3'b000; din = 8'hAA; // Write 0xAA at address 0
#10 we = 1; addr = 3'b001; din = 8'h55; // Write 0x55 at address 1
#10 we = 1; addr = 3'b010; din = 8'hF0; // Write 0xF0 at address 2

// Read values back

#10 we = 0; addr = 3'b000; // Read from address 0
#10 addr = 3'b001; // Read from address 1
#10 addr = 3'b010; // Read from address 2

// End simulation
#20 $stop;
end
endmodule

94
Simulated Output: Memories1: Any microcontroller

95
Result:

The 8x64K memory module was successfully simulated and verified

using Verilog HDL.

96