Madan Mohan Malaviya Univ.

of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-6)

Presented By:
Prof. R. K. Chauhan
Department of Electronics and Communication Engineering
16-07-2020 Side 1
Introduction
• The SPICE software that was distributed by UC
Berkeley beginning in the late 1970s had three
built-in MOSFET models
– LEVEL1(MOS1) is a described y a square-law
current-voltage characteristics
– LEVEL2 (MOS2) is a detailed analytical MOSFET
model
– LEVEL 3 (MOS3) is a semi-empirical model
• Both MOS2 and MOS3 include second-order effects
– The short channel threshold voltage, subthreshold conduction,
scattering-limited velocity saturation, and charge-controlled
capacitances
– The BSIM3 version
• More accurate characterization sub-micron MOSFET
characteristics
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Basic concept

• The equivalent circuit structure of the

NMOS LEVEL 1 model

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 The LEVEL 1 model equation
• K’=27.6μA/V2 KP=27.6U
Linear region
• VT0=1.0V VTO=1
k' W • γ=0.53V1/2 GAMMA=0.53
ID = ⋅ ⋅ 2 ⋅ VGS − VT VDS − VDS
2
⋅ 1 + λ ⋅ VDS for VGS ≥ VT
2 Leff • 2φF=-0.58 PHI=0.58
and VDS < VGS -VT • λ=0 LAMBDA=0
Saturation region • μn=800cm2/Vs UO=800
• tox=100nm TOX=100E-9
k' W 2
ID = ⋅ ⋅ VGS − VT ⋅ 1 + λ ⋅VDS for VGS ≥ VT • NA=1015cm-3 NSUB=1E15
2 Leff
• LD=0.8μm LD=0.8E-6
and VDS ≥ VGS -VT
The threshold voltage
VT = VT 0 + ⋅ 2 F + VSB − 2 F

Leff = L − 2 ⋅ LD
εox
k' = ⋅ Cox where Cox =
tox
2⋅ ⋅q⋅ NA
= Si

Cox
kT ⎛ ni ⎞
2 F =2 ⋅ ln⎜⎜ ⎟⎟
q ⎝ NA ⎠

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Variation of the drain current with model parameter

5
The LEVEL 2 model equation
k' W ⎧⎛ VDS ⎞ 2 3/ 2 3/ 2 ⎫
ID = ⋅ ⋅ ⎨⎜VGS − VFB − 2 F − ⎟ ⋅VDS − ⋅ ⋅ VDS − VBS + 2 F − − VBS + 2 F ⎬
1 − ⋅ VDS Leff ⎩⎝ 2 ⎠ 3 ⎭
The saturation voltage
⎛ 2 ⎞
VDSAT = VGS − VFB − 2 F + 2
⋅ ⎜⎜1 − 1 + 2 ⋅ VGS − VFB ⎟
⎟
⎝ ⎠
The saturation mode current
1
I D = I Dsat ⋅
1-λ ⋅ VDS
The zero bias threshold voltage
q ⋅ N ss
VT 0 = Φ GC − +2 F + 2 F
Cox
• In the current equation above, the surface carrier mobility has been assumed
constant, and its variation with applied terminal voltages has been neglected
• In reality, the surface mobility decreases with the increasing gate voltage
– Due to the scattering of carriers in the channel
– Ue
⎛ toc ⋅ U c ⎞
k(' new) = k ' ⋅ ⎜⎜ Si ⋅ ⎟⎟
⎝ ox VGS − VT − U t ⋅VDS ⎠
U c is the gate - to - channel critical field
U t is the contribution of the drain voltage to the gate - to - channel field
U e is the exponential fitting parameter 6
variation of channel length in saturation mode

L'eff = Leff − ΔL

2 ⋅ Si ⎡VDS − VDSAT
2⎤
⎛ V − V DSAT ⎞ ⎥
ΔL = ⋅⎢ + 1 + ⎜ DS ⎟
q⋅ NA ⎢ 4 ⎝ 4 ⎠ ⎥⎦
⎣
The empirical channel length shortening coefficient
ΔL
=
Leff ⋅ VDS
The slope of the I D -VDS vurve is saturation can be adjusted and
fitted to experimental data by changing the substrate doping parameter N A
In this case, however, other N A - dependent electrical parameters such
as 2 F and must be specified separately in the .MODEL statement

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Saturation of carrier velocity
• The calculation of the saturation voltage VDSAT is based
on the assumption
– The channel charge near the drain becomes equal to zero when
the device enters saturation
– This hypothesis is actually incorrect
• Since a minimum charge concentration greater than zero must exist
in the channel, due to the carriers that sustain the saturation current
• The minimum concentration depends on the speed of the carriers
• The inversion layer charge at the channel-end is found as
– I Dsat
Qinv =
W ⋅ vmax
2
⎛ X D ⋅ vmax ⎞ X D2 ⋅ vmax
ΔL = X D ⋅ ⎜⎜ ⎟⎟ + VDS − VDSAT −
⎝ 2⋅ ⎠ 2⋅
2 ⋅ Si
XD =
q ⋅ N A ⋅ N eff

– The parameter Neff is used as a fitting parameter

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Subthreshold conduction
• For VGS<VT, there is a channel current even
when the surface is not in strong inversion
• This subthreshold current
– Due mainly to diffusion between and the
channel
– Becoming an increasing concern for deep-
sub-micron designs
• The model implemented in SPICE
introduces an exponential, semi-empirical
dependence of the drain current on VGS in
the weak inversion region
– ⎛ q ⎞
(VGS −Von )⋅⎜ ⎟
I D ( weak inversion ) = I on ⋅ e ⎝ nkT ⎠

I on is the current in strong inversion for VGS = Von

the voltage Von is found as
nkT q ⋅ N FS Cd
Von = VT + where n = 1 + +
q Cox Cox
The parameter N FS is defined as the number of fast superficial states
and is used as a fitting parameter that determines the slope of the subthreshold
current - voltage characteristics
Cd : is the depletion capacitance
This model introduces a discontinuity for VGS = Von , therefore, the simulation
of the transition region between weak and strong inversion is not very precise
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The LEVEL 3 model equations
• The LEVEL 3 model has been developed for simulation of short channel
MOS transistor
– Quite precisely for channel lengths down to 2μm
– The current-voltage equation in the linear region has been simplified with a
Taylor series expansion
– The majority of the LEVEL 3 model equations are empirical
• To improve the accuracy of the model
• To limit the complexity of the calculation
W ⎛ 1 + FB ⎞
ID = s ⋅ Cox ⋅ ⋅ ⎜VGS − VT − ⋅ VDS ⎟ ⋅ VDS
Leff ⎝ 2 ⎠
⋅ Fs
where FB = + Fn
4⋅ 2 F + VSB
The empirical parameter FB express the dependence of the bulk depletion charge
The VT . Fs , and μs are influenced by the short - channel effects
The Fn is influenced by the narrow - channel effects
μ
μs =
1 + θ ⋅ VGS -VT
The decrease in the effective mobility with the average lateral electrical field
μs
μeff =
VDS
1 + μs ⋅
vmax ⋅ Leff
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State-of-art MOSFET models
• BSIM-Berkeley short-channel IGFET model
– The model is analytically simple and is based on a small number
of parameters, which are normally extracted from experimental
data
– Accuracy and d\efficiency
– Widely used by many companies and silicon foundries
• EKV (Enz-Krummenacher-Vittoz) transistor model
– Previous models considering
• The strong-inversion region of operation separately from the weak-
inversion region
• Causing serous problems in the modeling of transistors at very low
voltages as in many cases involving deep sub-micron CMOS
technology
– Attempting to solve this problem by
• Using a unified view of the transistor operating regions
• Avoiding the use of disjoint equations in strong and weak inversion

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Gate oxide capacitance
• SPICE uses a simple gate oxide capacitance model that represents the charge
storage effect by three nonlinear two-terminal capacitor: CGB, CGS and CGD
• The geometry information required for the calculation of gate oxide capacitance are:
– Gate oxide thickness TOX
– Channel width W
– Channel length L
– Lateral diffusion LD
• The capacitances CGBO, CGSO, and CGDO, which are specified in the .MODEL
statement, are the overlap capacitances between the gate and the other terminals
outside the channel region
• If the parameter XQC is specified in the .MODEL statement
– SPICE uses a simplified version of the charge-controlled capacitance model proposed by
Ward

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Junction capacitance

C j ⋅ AS C jsw ⋅ PS
CSB = Mj
+ M jsw
⎛ VBS ⎞ ⎛ VBS ⎞
⎜⎜1 − ⎟⎟ ⎜⎜1 − ⎟⎟
⎝ 0 ⎠ ⎝ 0 ⎠

C j ⋅ AD C jsw ⋅ PD
C DB = Mj
+ M jsw
⎛ VBD ⎞ ⎛ VBD ⎞
⎜⎜1 − ⎟⎟ ⎜⎜1 − ⎟⎟
⎝ 0 ⎠ ⎝ 0 ⎠

C j : the zero - bias depletion capacitance per unit area at the bottom of the junction
C jsw : the zero - bias depletion capzcitance per unit length at the sidewall junctions
C jsw ≅ 10 ⋅ C j ⋅ x j
AS and AD are the source and the drain areas
PS and PD are the source and the drain perimeters
M j and M jsw denote the junction grading coefficients for the bottom and the sidewalls junctions
Default values are M j = 0.5 and M jsw = 0.33

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Comparison of the SPICE MOSFET models
• The LEVEL 1 model
– Not very precise
– Quick and rough estimate of the circuit performance
without much accuracy
• THE LEVEL 2 model
– Require a larger time
– May occasionally cause convergence problems in the
Newton-Raphson algorithm used in SPICE
• THE LEVEL 3 model
– The CPU time needed for model evaluation is less
and the number of iterations are significantly fewer for
the LEVEL three model
– Disadvantage
• The complexity of calculating some of its parameters

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