CSE 520210

Microprocessor and Assembly

Language

Internal Architecture of Intel

8086
FEATURES OF 8086
 It is a 16-bit μp.
 8086 has a 20 bit address bus

can access up to 220 memory

locations (1 MB).
 It can support up to 64K I/O ports.

 It provides 14, 16 -bit registers.

 Word size 16 bit.

 It has multiplexed address

and data bus AD0- AD15 and A16 – A19.

FEATURES OF 8086
 8086 is designed to operate in two
 modes, Minimum and Maximum.
 It can pre-fetch up to 6 instruction
 bytes from memory and queues them
 in order to speed up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package
 Address ranges from 00000H to FFFFFH.
 BIU

EU
 Internal Architecture of 8086
 8086 has two blocks –
 Bus Interface Unit(BIU) and Execution unit(EU).
• Dividing the work between these two units speed up
processing.
 The BIU sends out addresses, fetches instruction
from memory, reads data from ports and memory, and
writes data to ports and memory.
The BIU handles all transfer of data and addresses
on the buses for the execution unit.
The execution unit of 8086 tells the BIU where to fetch
instruction or data from, decode instructions and executes
instructions.
 THE BUS INTERFACE UNIT(BIU)
6-byte instruction Queue (Q)
The segment registers (CS, DS, ES, SS).
The instruction Pointer (IP).
The Address summing block(∑)
• The function of BIU is that it fetches instructions, read data from memory
or I/O ports and writers data to memory of I/O ports and buffers them
into the queue.
• While the execution units decode or executes an instruction that does not
involve uses of the bus, the BIU fetches up to 6-byte instruction byte for
preceding instruction.
• The BIU stores this pre-fetched instruction byte in FIFO register called
instruction queue.
• Fetching the next instruction while executing the current instruction is
referred as the instruction pipeline.
• The BIU has a dedicated Adder; the main function of the adder is to
produce 20 bit physical address.
 BUS INTERFACE UNIT(BIU)
• The bus control logic of the BIU generates all bus control signals such as read and
writes for memory I/O ports.
• BIU sends out 20-bit addresses, so it can address any of 220 bytes in memory.
• Four segment registers in the BIU are used to hold the upper 16-bits of the starting
addresses of four memory segments that the 8086 is working with at particular
time.
• The four segment registers are the Code segment (CS), Stack segment (SS), Extra
Segment (ES) and Data Segment (DS).

In short the Bus Interface unit is responsible for performing all following external bus
operations.
– It sends the address of the memory or I/O.
– It fetches instruction from memory.
– It read data from port/memory.
– It writes data into port/memory.
– It supports instruction queuing.
– It provides the address relocation facility.
 Segment Register
In 8086 processor has 4 segments registers
•Code Segment register (CS)
•Data Segment register(DS)
•Extra Segment register(ES)
•Stack Segment (SS)register.
All are16 bit registers.
Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.
Memory Segments of 8086
 Segment Register
• Code Segment (CS): The CS register is used for
addressing a memory location in the Code Segment of
the memory, where the executable program is stored.
• Data Segment (DS): The DS contains most data used by
program. Data are accessed in the Data Segment by an
offset address or the content of other register that
holds the offset address.
• Stack Segment (SS): SS defined the area of memory
used for the stack.
• Extra Segment (ES): ES is additional data segment that
is used by some of the string to hold the destination
data.
 Segmented Memory
The memory in an 8086 based system is organized as segmented memory.
The CPU 8086 is able to address 1Mbyte of memory.
The Complete physically available memory may be divided into
a number of logical segments.
The 4 segments are Code, Data, Extra and Stack segments.
A Segment is a 64kbyte block of memory.
The16 bit contents of the segment registers in the BIU actually
Point to the starting location of a particular segment.
Segments may be overlapped or non-overlapped
 Instruction Pointer (IP) and the
Address Summing Block
• The IP register hold the 16 bit offset address or the offset, of the next
code byte within the Code segment.
• An offset is the distance (in terms of address) from the beginning of a
segment to a particular instruction or variable.
• The IP always references the Code segment register (CS).
• The physical address of the next instruction is formed by combining the
CS and IP.
• To form a 20bit address of the next instruction, the 16 bit address of the
IP is added (by the address summing block) to the address contained in
the CS , which has been shifted four bits to the left.
• The following examples shows the CS:IP scheme of address formation
 16-bit word fetch from even valued
physical address
Consider the following instruction:
MOV BX, [XXXX] where DS:XXXX points to an even
physical address say 01234H Address Word
Then the BX will loaded in One 01230 12
01231 34
memory access operation in 01232 56
01233 78
following way:
01234 9A
High byte of the word in BH Low byte of the word BL 01235 BC
BCH 9AH 01236 DE
From address 01235H From address 01234H
 16-bit word fetch from odd valued
physical address
Consider the following instruction:
MOV BX, [XXXX] where DS:XXXX points to an odd
physical address say 01233H Address Word
Then the BX will loaded in Two 01230 12
01231 34
memory access operation in 01232 56
01233 78
following way:
01234 9A
High byte of the word in BH Low byte of the word BL 01235 BC
9AH 78H 01236 DE
From address 01234H From address 01233H
 16-bit word fetch from odd valued
physical address
In first operation, the processor will fetch from physical
address 01232H and 01233H and will discard the contents
of 01232H
And in next fetch operation, contents Address Word
01230 12
from 01234H and 01235H will be 01231 34
fetched but contents from 01235H 01232 56
01233 78
will be discarded
01234 9A
High byte of the word in BH Low byte of the word BL 01235 BC
9AH 78H 01236 DE
From address 01234H From address 01233H
 8-bit word fetch from even valued
physical address
Consider the following instruction:
MOV BH, [XXXX] where DS:XXXX points to an even
physical address say 01234H
Address Word
Then only BH part will be loaded in 01230 12
One memory access operation. Words 01231 34
01232 56
from both 01234H and 01235H will 01233 78
be fetched but contents from 01235H 01234 9A
01235 BC
will be discarded. And…… 01236 DE
BH = 9AH
 8-bit word fetch from odd valued
physical address
Consider the following instruction:
MOV BL, [XXXX] where DS:XXXX points to an odd
physical address say 01235H
Address Word
Then only BL part will be loaded in 01230 12
One memory access operation. Words 01231 34
01232 56
from both 01234H and 01235H will 01233 78
be fetched but contents from 01234H 01234 9A
01235 BC
will be discarded. And…… 01236 DE
BL = BCH
 Difference between the physical and
the logical address
• The physical address is 20 bits long and corresponds to the
actual binary code output by the BIU on the address bus
lines. The logical address is an offset from location 0 of a
given segment.
• When two segments overlap it is certainly possible for two
different logical addresses to map to the same physical
address. This can have disastrous results when the data
begins to overwrite the subroutine stack area, or vice versa.
For this reason you must be very careful when segments
are allowed to overlap.
• You should also be careful when writing addresses on paper
to do so clearly. To specify the logical address XXXX in the
stack segment, use the convention SS:XXXX, which is equal
to [SS] * 10H + XXXX.
 Advantages of Segmented memory
Scheme
• Allows the memory capacity to be 1Mb although
the actual addresses to be handled are of 16 bit size.
• Allows the placing of code, data and stack portions
of the same program in different parts(segments)of
the memory, for data and code protection.
• Permits a program and/or its data to be put into
different areas of memory each time program is
executed, i.e. provision for relocation may be done .
 ADDRESSING MODES
The CPU can access operands (data) in various ways,
called addressing modes. The number of addressing
modes is determined when microprocessor is
designed and cannot be changed. The 80x86 provides
a total of seven distinct addressing modes:
1. Register
2. Immediate
3. Direct
4. Register indirect
5. Based relative
6. Indexed relative
7. Based indexed relative
size of source and destination
must match
;move contents of DS:2400H into DL
 Example of Direct addressing mode
Find the physical address of the memory location and its contents after the
execution of the following, assuming that DS = 1512H.
MOV AL, 99H
MOV [3518H], AL
Solution: First AL is initialized to 99H, then in line two, the contents of
AL are moved to logical address DS:3518Hwhich is 1512:3518. Shifting
DS left and adding it to the offset gives the physical address of 18638H
(15120H + 3518H = 18638H).
That means after the execution of the second instruction, the memory
location with address 18638H will contain the value 99H
;move contents of DS:SI into CL

;move contents of AH into DS:DI

;moves contents of AX into memory

;locations DS:SI and DS:SI +1
 Example of Register indirect addressing mode

Assume that DS = 1120, SI = 2498, and AX = 17FE. Show the contents of

memory locations after the execution of
MOV [SI], AX

Solution: The contents of AX are moved into memory locations with

logical address DS:SI and DS:SI+1. Low address 13698H contain FE, and
high address 13699H contains 17H.
;move DS:BX+10 & DS:BX+10+1
;into CX. PA= DS(sl) +BX+10

;PA = SS (sl) + BP + 5
 Based relative addressing mode
• In the based relative addressing mode, base registers are BX
and BP. The default segments are DS for BX and SS for BP. For
example:
MOV CX, [BX]+10 ;move DS:BX+10 and DS:BX+10+1
into CX
;PA = DS (shifted left) + BX + 10
Alternative codings are
MOV CX, [BX+10] or MOV CX, 10[BX]
• In the case of the BP register,
MOV AL, [BP]+5 ;PA = SS(shifted left) + BP + 5
alternative codings are
MOV AL, [BP+5] or MOV AL, 5[BP]
;PA = DS (sl) + SI + 5

;PA = DS (sl) + DI + 20
 Example of Indexed relative addressing mode
Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486,
DI = 8500, BP = 7814, and AX = 2512. Show the exact
physical memory location where AX is stored in each of the
following. All values are in hex.
(a) MOV [BX]+20, AX (b) MOV [SI]+10, AX
(c) MOV [DI]+4, AX (d) MOV [BP]+12, AX
Solution:
(a) DS:BX+20 location 47120 = (12) and 47121 = (25)
(b) DS:SI+10 location 46496 = (12) and 46497 = (25)
(c) DS:DI+4 location 4D504 = (12) and 4D505 = (25)
(d)SS:BP+12 location 27826 = (12) and 27827 = (25)
;PA=DS(sl)+BX+DI +8

;PA=SS(sl)+BP+SI +29
 Summary of 8086 addressing modes
Addressing Mode Operand Default

Register reg None

Immediate Data None

Direct [offset] DS

Register indirect [BX], [SI], [DI] DS, DS, DS

Based relative [BX]+disp, [BP]+disp DS, SS

Indexed relative [DI]+disp, [SI]+disp DS, DS

Based indexed relative [BX][SI]+disp, [BX][DI]+disp DS, DS

[BP][SI]+disp, [BP][DI]+disp SS, SS
EXCECUTION UNIT
 EXCECUTION UNIT

• The execution unit includes the ALU, eight 16-bit

general purpose register, a 16-bit flag register and a
control unit.
• EU contains control circuitry which directs internal
operations.
• A decoder in the EU translates instructions fetched
from memory into a series of actions which the EU
carries out.
• The EU has a 16-bit arithmetic logic unit which can
add, subtract, AND, OR, increment, decrement,
complement, Binary numbers.
 EXECUTION UNIT(EU)
• The EU contains eight 16-bit general purpose registers-
AX, BX, CX, DX, SP, BP, SI and DI.
 Among these registers AX, BX, CX, DX can be further into
two 8-bit registers AH&AL, BH&BL, CH&CL and
DH&DL.
 The general purpose registers can be used to store or 16-
bit data during program execution.
• A 16-bit flag register in the EU contains nine active
flags.
 Six of the nine flags are used to indicate some condition
produced by an instruction.
 The three remaining flags in the flag registers are used to
control certain operations of the processors.
EXCECUTION UNIT-GENERAL PURPOSE REGISTERS
 EXCECUTION UNIT-General Purpose Registers

Register------Purpose
AX ---------Word multiply, word divide, word I /O
AL ---------Byte multiply, byte divide, byte I/O,
decimal arithmetic
AH --------Byte multiply, byte divide
BX --------Store address information
CX --------String operation, loops
CL --------Variable shift and rotate
DX --------Word multiply, word divide, indirect I/O
 EU--Pointer and Index
Registers(SP,BP,SI,DI)

• Used to keep offset addresses.

• Used in various forms of memory addressing.

• In the case of SP and BP the default reference

to form a physical address is the Stack
Segment(SS-is discussed under the BIU)
 Pointer and Index Registers
• The index registers (SI & DI) and the BX
generally default to the Data segment
register(DS).
• SP: Stack pointer
– Used with SS to access the stack segment
• BP: Base Pointer
• – Primarily used to access data on the stack
• – Can be used to access data in other segments
 Pointer And Index Registers
• SI: Source Index register
• It performs to point to memory locations in the
data segment. by incrementing the contents of SI
consecutive memory locations can be accessed.
– is required for some string operations.
– When string operations are performed, the SI
register points to memory locations in the data
segment which is addressed by the DS register. Thus,
SI is associated with the DS in string operations.
 Pointer and Index Registers
DI: Destination Index register
• DI is used to point to memory locations.
– is also required for some string operations.
– When string operations are performed, the DI
register points to memory locations in the data
segment which is addressed by the ES register.
Thus, DI is associated with the ES in string
operations.
The SI and the DI registers may also be used to
access data stored in arrays.
 EXCECUTION UNIT-Flag register
• Flags Register determines the current state of the
processor. They are modified automatically by CPU
after mathematical operations, this allows to
determine the type of the result, and to determine
conditions to transfer control to other parts of the
program.
• In 8086 The EU contains a 16 bit flag register. 9 of the
16 are active flags and remaining 7 are undefined.
• 8086 has 9 flags and they are divided into two
categories:
Conditional Flags
Control Flags
 EXCECUTION UNIT-Flag register

U U U U OF DF IF TF SF ZF U AF U PF U CF

Overflow Direction Interrupt Trap sign Zero Auxiliary Parity Carry

 Conditional Flags
Conditional flags represent result of last arithmetic or logical
instruction executed. Conditional flags are as follows:
• Carry Flag (CF): This flag indicates an overflow condition for
unsigned integer arithmetic. It is also used in multiple-
precision arithmetic.
• Auxiliary Flag (AF): If an operation performed in ALU
generates a carry/barrow from lower nibble (i.e. D0 – D3) to
upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by
D3 bit to D4 is AF flag. This is not a general-purpose flag, it is
used internally by the processor to perform Binary to BCD
conversion.
• Parity Flag (PF): This flag is used to indicate the parity of
result. If lower order 8-bits of the result contains even
number of 1’s, the Parity Flag is set and for odd number of 1’s,
the Parity Flag is reset.
 Conditional Flags
• Zero Flag (ZF): It is set; if the result of arithmetic or logical
operation is zero else it is reset.
• Sign Flag (SF): In sign magnitude format the sign of number is
indicated by MSB bit. If the result of operation is negative,
sign flag is set.
• Overflow Flag (OF): It occurs when signed numbers are added
or subtracted. An OF indicates that the result has exceeded
the capacity of machine.
 Control Flags
Control flags are set or reset deliberately to control the operations of
the execution unit. Control flags are as follows:
• Trap Flag (TP):
– It is used for single step control and allows user to execute one
instruction of a program at a time for debugging.
– When trap flag is set, program can be run in single step mode.
• Interrupt Flag (IF):
– It is an interrupt enable/disable flag.
– If it is set, the maskable interrupt of 8086 is enabled and if it is
reset, the interrupt is disabled.
– It can be set by executing instruction sit and can be cleared by
executing CLI instruction.
 Control Flags
• Direction Flag (DF):
– It is used in string operation.
– If it is set, string bytes are accessed from higher memory
address to lower memory address.
– When it is reset, the string bytes are accessed from lower
memory address to higher memory address.