International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056

Volume: 02 Issue: 02 | May-2015 www.irjet.net p-ISSN: 2395-0072

DESIGN OF HIGHER ORDER PHASE LOCKED LOOP

Sreelekshmi K. R.1, Subhalekshmi K. R.2, Jacob Thomas3

1 M. Tech Scholar, Department of ECE, Believers Church Caarmel Engg. College, Kerala, India
2 M. Tech Scholar, Department of ECE, Believers Church Caarmel Engg. College, Kerala, India
3 Assistant Professor, Department of ECE, Believers Church Caarmel Engg. College, Kerala, India

---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - A phase-locked loop (PLL) is a closed-loop is that they are un- conditionally stable. They typically
feedback control system, which synchronizes its output yield a satisfactory performance in terms of the phase or
frequency detection accuracy when the grid frequency is
signal in frequency as well as in phase with an input
at, or close to, its nominal value; however, their
signal. The phase detector, the loop filter, and the performance tends to worsen when the input frequency
voltage controlled oscillator are the key parts of almost deviates from its nominal value. To overcome this
all PLLs. The phase-locked loops (PLLs) are probably problem, incorporating frequency estimation or control
the most widely used synchronization technique in grid- algorithms into the open-loop schemes have been
connected applications. A basic approach to improve proposed. The main challenge that is associated with the
PLLs is how to precisely and fast estimate the phase and
the performance of phase-locked loop (PLL) under
frequency, when the grid voltage is unbalanced and/or
adverse grid condition is to incorporate a first-order distorted. To overcome this challenge, incorporating
low-pass filter (LPF) into its control loop. The first- moving average filter(s) (MAF) into the PLL structure has
order LPF, however, has a limited ability to suppress been proposed in some recent literature. An MAF is a
grid disturbances. Normally the loop filter is designed linear-phase finite-impulse-response filter, which can act
to match the characteristics required by the application as an ideal low-pass filter, if certain conditions hold. The
of the PLL. If the PLL is to acquire and track a signal the main aim of this paper is to present the control design
guidelines for a typical MAF-based PLL.
bandwidth of the loop filter will be greater than if it
expects a fixed input frequency. The pure digital phase
locked loop is attractive because it is less sensitive to
noise and operating conditions than its analog
counterpart. A PLL is a nonlinear feedback control
system that tracks the phase and frequency of the input
signal fundamental component and is able to re track Fig -1: Basic PLL Structure
the phase, with no steady-state error, following a
transient event such as phase and frequency jumps. Fig- 1 shows the basic structure of PLL. Among the
various synchronization techniques, PLLs have found
much attention, mainly due to their simplicity, robustness,
Key Words: Phase-locked loop, Low pass filter, and effectiveness. A PLL is a closed-loop feedback control
Synchronization. system, which synchronizes its output signal in frequency,
as well as in phase, with an input signal. With the
advanced technology of microcontrollers and digital signal
1. Phase Locked Loop processors (DSPs), all of the functions of the classical PLL
Phase-locked loops (PLLs) are a widely needed and used have been implemented by software. The components are:
circuitry in today’s semiconductor chips. They are mainly
used for three different tasks: Generation of high 1.1 Phase and Frequency Detector
frequency on-chip clocks by frequency multiplication, The first component in PLL is the phase and frequency
Reduction of clock skew and Jitter attenuation. A PLL is detector. The output of the PFD depends on both the phase
characterized by the frequency range, jitter, jitter and frequency of the inputs. This type of phase detector is
attenuation and lock time. PLLs are only used for also termed a sequential phase detector. It compares the
generation of high frequency stable clocks and are leading edges of data and data1 (data is the input signal to
normally feed by quartz controlled oscillators so that PFD, data1 is considered as the feedback signal from the
there is no need for a jitter attenuation. The phase-locked output of VCO to PFD). A data1 rising edge cannot be
Loops (PLLs) are probably the most widely used present without a data rising edge. If the rising edge of the
synchronization technique in grid-connected applications. data leads the data1 rising edge, the up output of the
The key feature of open-loop synchronization techniques phase detector goes high while the down output remains

© 2015, IRJET.NET- All Rights Reserved Page 1001

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 02 | May-2015 www.irjet.net p-ISSN: 2395-0072

low. This causes the data1 frequency to increase and to VCO is low, the frequency of output signal in VCO
makes the edges move closer. If the data1 signal leads the becomes smaller and smaller. This is reasonable. For
Data up remains low while the down goes high. And we example, if the voltage of the input signal to VCO becomes
can find the phase difference between data1 and data. high, that means the rising edge of data leads that of data1.
That is the reason why we need to make the frequency of
1.2 Loop Filter the output signal of VCO larger to catch up with the
The second component in PLL is the loop filter. The loop reference (input) signal.
filter consists of two parts, the charge pump and the RC-
filter. The output of the PFD should be combined into a 2. Model Order Reduction
single output to drive the loop filter. In charge pump, two According to the small signal model in fig- 3. The PLL
NMOS and two PMOS are connected serially. The under study is of order n + 2 (n is the LPF order). In what
uppermost PMOS and lowermost NMOS are considered as follows it is shown that regardless of the LPF order, the
the current source and the other PMOS and NMOS in the PLL Department of model can be approximated by a third-
middle are connected to the up and down of the output of order model. This model order reduction simplifies the
PFD. When the PFD up signal goes high, the PMOS will turn analysis and design of PLL. The key to determine the
on. This will connect the current source to the loop filter. It reduced-order model lies in the fact that the in-loop LPF
is in the similar way when the PFD down signal goes high. causes phase delay in the PLL control loop, so to ensure
The loop filter is a simple RC filter. However, it plays a the PLL stability its crossover frequency must be
very important role in the PLL. Unless the loop filter sufficiently lower than the LPF cutoff frequency.
values are correctly chosen, it would take the loop too long
to lock or once locked it is still unstable small variations in
the input data may cause the loop unlock again. If the
rising edge of data leads that of data1l, the PFD up goes
high. And it will cause the voltage of the output signal of
the loop filter become higher. If the rising edge of data lags Fig -3: Reduced Order Small Signal Model
that of data1, the PFD down goes high. It would cause
output signal of the loop filter become lower. The higher the LPF order, the greater the low frequency
phase delay is, and therefore the smaller the PLL
crossover frequency (compared to the LPF cutoff
1.3 Voltage Controlled Oscillator
frequency) should be. According to this fact, the reduced-
In the voltage controlled oscillator (VCO), the main part is order model can be obtained by neglecting the high
the multiple stage oscillator which is similar to the ring frequency dynamics of LPF and approximating its transfer
oscillator. In each stage, there are two PMOS and two function with a first-order transfer function in Fig- 3. This
NMOS. The upper most PMOS and lower most NMOS model is accurate at low frequency range. Therefore, it can
operate as current source and the PMOS and NMOS in the only be used to study the stability and dynamic behavior
middle operate as inverter. The current sources limit the of PLL.
current available to the inverter. Compared with the
resistance and capacitance present in the loop filter, the
3. PLL Structure and Small Signal Modeling
resistance of the VCO should bed resigned infinite and the
capacitance of the VCO should be designed smaller. Fig- 2 Fig- 4 shows the schematic diagram of PLL under study,
shows the standard structure of PLL. which is a standard three phase PLL with an in-loop LPF.
In this structure, the PI controller acts as the main filter of
Control loop as it is responsible to provide a zero steady-
state average phase-error for the PLL. The LPF, on the
other hand, supports the PI controller as it is responsible
to improve the disturbance rejection capability of control
loop under adverse grid condition. The performance of
PLL under distorted grid condition is to include a simple
first order low pass filter (LPF) inside its control loop.

Fig -2: Standard PLL Structure

The input to the VCO is the output signal of loop filter.

When the voltage of the input signal to VCO is high, the
frequency of output signal in VCO becomes larger and
larger. The output of loop filter is given to the input of
VCO. On the contrary, when the voltage of the input signal Fig -4: Structure of PLL under Study

© 2015, IRJET.NET- All Rights Reserved Page 1002

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 02 | May-2015 www.irjet.net p-ISSN: 2395-0072

A first-order LPF, however, has a limited ability to and frequency mismatch of the reference clock and
suppress the grid disturbances. To further improve the divided DCO clock. The PLL is locked when the PFD
disturbance rejection capability of PLL, using higher order detects that the phase and frequency of the two clock
LPFs are sometimes recommended. For example, using a inputs match. The output of the PFD drives the time to
fourth order LPF in the PLL control loop is suggested in. digital converter. The PFD produces up and down enable
Application of these high order LPFs, however, results in signals that are interfaced to the digital converter. The
high order PLLs. digital converter takes these inputs and increases or
decreases the control word which is fed to the
4. All Digital Phase Locked Loop thermometric decoder. This decoder is essential for
An all digital phase locked loop was implemented, in 0.25 controlling the DCO. The DCO clock is divided by a specific
micron CMOS technology, by understanding the analog multiplication factor, in our case it is four, and sent back to
phase locked loop concepts and the digital conversion the PFD for phase and frequency comparison.
required to maintain the same functionality. The all digital
phase locked loop achieves locking within about 100 5. Linear Phase Locked Loop
reference clock cycles. The pure digital phase locked loop Linear PLL is also in s domain. The phase error is small in
is attractive because it is less sensitive to noise and linear PLL. A PLL can be accurately described by a linear
operating conditions than its analog counterpart. Many model. So it is known as linear PLL. Fig- 6 shows the linear
circuits currently face the problem of clock skew, and PLL model.
registers and flip-flops are not receiving the clock at the
exact same time. The clocks are generated by oscillators,
but the clocks that reach the registers and flip-flops are
distorted and require a phase locked loop to address this
problem.

Fig -6: Linear PLL Model

The phase of the input signal, the phase of the feedback

signal is shown in fig- 6. Since the system is described in
the continuous-time domain. So far, all the modeling
shown is in the continuous-time domain. This model can
be applied directly to an analog PLL. One mandatory
requirement for designing linear PLLs is that the linear
PLL system must be stable. Basically, the stable condition
of a discrete-time system occurs when the roots of the
Fig -5: ADPLL Block Diagram characteristic equation are inside the unit circle in the Z-
plane. Normally, after a system is implemented, numerical
A phase locked loop ensures that the clock frequencies Coefficient can be substituted into the characteristic
seen at the clock inputs of various registers and flip-flops equation. By solving the characteristic equation
match the frequency generated by the oscillator. The numerically, the positions of the poles can be found to
phase locked loop (PLL) is a very important and common determine if the system is stable; however, this method is
part of high performance microprocessors. Traditionally, a technically difficult to use when implementing a linear PLL
PLL is made to function as an analog building block, but since numerical coefficients will not be available at the
integrating an analog PLL on a digital chip is difficult. beginning of the process.
Analog PLLs are also more susceptible to noise and
process variations. Digital PLLs allow a faster lock time to 6. CONCLUSIONS
be achieved and are attractive for clock generation on high PLL is a closed-loop feedback control system that
performance microprocessors. The all digital phase locked synchronizes its output signal in frequency as well as in
loop was designed such that it is composed of four main phase with an input signal. Phase Locked Loops (PLL)
components. The components are analogous to the analog circuits are used for frequency control. They can be
PLL, but the implementation consists of digital configured as frequency multipliers, demodulators,
components. A digitally controlled oscillator (DCO) was tracking generators or clock recovery circuits. Each of
utilized instead of a voltage controlled oscillator. A high these applications demands different characteristics but
level block diagram of the implementation is shown in Fig- they all use the same basic circuit concept. The phase
5. The phase frequency detector (PFD) detects the phase locked loop (PLL) is a very important and common part of

© 2015, IRJET.NET- All Rights Reserved Page 1003

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 02 Issue: 02 | May-2015 www.irjet.net p-ISSN: 2395-0072

high performance microprocessors. Traditionally a PLL is BIOGRAPHIES

made to function as an analog building block, but
integrating an analog PLL on a digital chip is difficult.
Analog PLLs are also more susceptible to noise and
process variations. Digital PLLs allow a faster lock time to
Ms. Sreelekshmi K. R., received
be achieved and are attractive for clock generation on high
her B. Tech Degree in Electronics
Performance microprocessor. On concerning the future
& Communication Engineering
work the phase locked loop (PLL) has been widely used in
from Cochin University in 2013.
Wireless communication systems due to the high
At present she is pursuing M.
frequency resolution and the short locking time. The usage
Tech in Communication
of Direct Digital Synthesis (DDS) avoids some of the typical
Engineering at Believers Church
tradeoffs in PLL like the achievement of a very high-
Caarmel Engg. College, Kerala.
frequency resolution together with fast settling and
spectral purity. As a part of the future work, the present
work can be extended with a DDS-based PLL architecture.

Ms. Subhalekshmi K. R., received

REFERENCES her B. Tech Degree in Electronics
& Communication Engineering
[1] Saeed Golestan, Member, IEEE, Francisco D. Freijedo, from Cochin University in 2013.
and Josep M. Guerrero, Senior Member, IEEE, “A At present she is pursuing M.
Systematic Approach to Design Higher-Order Phase Tech in Communication
Locked Loops” IEEE Trans. Power Electronics, 2013. Engineering at Believers Church
[2] S. Golestan, M. Ramezani, J. M. Guerrero, F. D. Caarmel Engg. College, Kerala.
Freijedo, and M. Monfared, “Moving average filter
based phase-locked loops: Performance Analysis and
design guidelines,” IEEE Trans. Power Electron., vol. Mr. Jacob Thomas received his
29,no. 6, pp. 2750-2763, Jun. 2014. B. Tech Degree in Electronics &
[3] F. D. Freijedo, A. G. Yepes, O. Lopez, P. Fernandez- Communication Engineering
Comesana, and J. Doval-Gandoy, “An optimized from St. Joseph’s College of
implementation of phase locked loops for grid Engineering and Technology,
applications,” IEEE Trans. Instrum. Meas., vol. 60, no. Affiliated to Mahatma Gandhi
9, pp.3110-3119, Sep. 2011. University, in 2007. He got M.
[4] F. Gonzalez-Espin, G. Garcera, I. Patrao, and E. Tech in Network and Internet
Figueres, “An adaptive control system for three- Engineering from Karunya
phase photovoltaic inverters working in a polluted University, Coimbatore, in 2011. At present he is working
and variable frequency electric grid,” IEEE Trans. in Believers Church Caarmel Engg. College as Assistant
Power Electron., vol. 27, no. 10, pp. 4248-4261, Oct professor in Electronics and Communication Engineering
2012. Department. His research areas includes R. F.
[5] S. Golestan, F. D. Freijedo, A. Vidal, J. M. Guerrero, and Communication and Networking.
J. Doval-Gandoy, “A quasi-type-1 phase-locked loop
structure,” IEEE Trans. Power Electron., vol. PP, no.
99, pp. 1-7, Jun. 2014.
[6] S. Golestan, M. Monfared, F. D. Freijedo, J. M.
Guerrero, “Design and tuning of a modified power-
based PLL for single-phase grid connected power
conditioning systems,” IEEE Trans. Power Electron.,
vol. 27, no.8, pp. 3639-3650, Aug. 2012.
[7] Y. F. Wang, and Y. W. Li, “Grid synchronization PLL
based on cascaded delayed signal cancellation,” IEEE
Trans. Power Electron., vol. 26, no. 7, pp. 1987-1997,
Jul. 2011.
[8] H. Awad, J. Svensson, and M. J. Bollen, “Tuning
software phase-locked loop for series-connected
converters,” IEEE Trans. Power Del., vol. 20, no. 1, pp.
300-308, Jan. 2005.

© 2015, IRJET.NET- All Rights Reserved Page 1004