# test group test condition

1 PTB write all words

1
1 read all words
1
1 transmit all words
1 full, TBUF write-locked
1 overwrite actual slot
1 unused words
1 IDE, RTR, EDL, BRS (all combinations, incl. auto-reset)
1 STB write all words (actual slot)
1
1 read all words (actual slot)
1
1 transmit all words
1 full
1 full + new message
1
1
1
1 overwrite actual slot
1 unused words
1 IDE, RTR, EDL, BRS (all combinations, incl. auto-reset)
1 prefetch mechanism (fast enough?)
1 RBUF IDE, RTR, EDL, BRS (all combinations, incl. auto-reset)
1 ESI=
1
1 TTCAN timestamp
1 read all slots
1
1 TX=
1
1
1
1
1
1 KOER
1
1
1
1
1
1
1
1
1
1
1
1
1
1 ACF read all words - reset value
1
1
1
1
1
1 write all words
1
1
1
1
1
1
1
1
1
1
1
1 read all words
1
1
1
1
1
1 ACF active=
1
1
1 EID=
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 not accepted -> bus acknowledge?
1 AIDEE=
1
1
1
1
1 write words
1
1 CFG_STAT reset value
1 RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 RACTIVE=
1
1
1 TACTIVE=
1
1
1 BUSOFF=
1
1
1
1
1 TCMD reset value
1 TBSEL
1 STBY
1
1
1
1
1
1
1 TPE
1
1
1
1
1
1 TPA
1
1
1
1
1
1
1
1 TSONE
1
1
1
1
1
1
1
1
1
1 TSALL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 TSA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 LOM (set '1')
1 TCTRL reset value
1 TBSEL=
1
1
1
1
1
1
1
1 FD_ISO
1
1 TSNEXT
1
1
1
1
1
1
1 TSMODE=
1
1
1
1
1
1
1
1
1
1
1 TTTBM=
1
1
1
1
1
1
1
1
1
1
1 TSSTAT
1 RCTRL reset value
1 ROV=
1
1
1
1
1 RREL
1
1
1
1
1
1
1 RSTAT=
1
1
1
1 RBALL=
1
1 SACK=
1
1 reserved bits
1 RTIE reset value
1 RIE=
1
1
1 ROIE=
1
1
1 RFIE=
1
1
1 RAFIE=
1
1
1 TPIE=
1
1
1 TSIE=
1
1
1 EIE=
1
1
1 TSFF=
1
1 RTIF reset value
1 RIF=
1
1
1
1
1
1
1
1 ROIF=
1
1
1
1 RFIF=
1
1
1
1 RAFIF=
1
1
1
1 TPIF=
1
1
1
1 TSIF=
1
1
1
1
1 EIF=
1
1
1
1
1
1
1
1
1
1
1
1
1
1 AIF=
1
1
1
1
1 ERRINT reset value
1 EWARN=
1
1
1 EPASS=
1
1
1 EPIF=
1
1
1
1
1
1
1
1
1
1 ALIF=
1
1
1
1 BEIF=
1
1
1
1 bit timing reset value
1 RESET=
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 TDC / RDC reset value
1 TDCEN
1
1
1
1
1 SSPOFF
1
1
1 real bus delays from a customer: 4MBit/s and 88ns
1 RDC (sync after EDL)
1 LIMIT reset value
1 RBUF_SLOTS
1
1
1
1
1 set EWL
1 EALCAP reset value
1 ALC
1
1
1
1
1
1
1
1
1
1
1 KOER
1
1
1
1
1
1
1
1
1
1
1
1 RECNT reset value
1 RECNT=
1
1
1
1 TECNT reset value
1 TECNT=
1
1
1 error counting ISO 11898-1, chap 12.1.4.2
1 bit error during arbitration
1 ACFCTRL reset value
1 write
1 SELMASK
1 ACFADR
1 reserved bits
1 observation LOM
1
1
1
1
1
1
1
1
1
1
1
1 LBMI
1 LBME
1
1
1
1 TPSS
1
1
1 TSSS
1
1
1
1
1
1 behavior 2 frames, identical ID, but one ID and one EID
1 reset -> startup (delay after RESET) -> transmission
1 CAN FD ESI
1 EDL=1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 BRS
1
1
1
1
1
1
1
1
1
1
1
1 stuff bits stuff bit before bit position
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 protocol frame start at 3rd intermission bit
1 dominant pulse at
1
1 protocol exception
1
1
1
1
1
1
1
1
1
1
1 2nd dominant ACK pulse
1
1 2nd recessive CRC delimiter
1
1 suspended transmission (error passive)
1
1
1 no suspended transmission (error passive)
1 dominant passive error flag
1
1 syn. param. STB_SLOTS=0
1
1
1
1 bit timing max
1 min
1
1
1 reset value
1 TBSLOT reset value
1 TBPTR
1
1
1
1 TBF=
1
1
1 TBE=
1
1
1
1
1
1
1 TTCFG reset value
1 TTEB=
1
1 T_PRESC=
1
1
1
1
1 TTIF
1 TTIE
1 TEIF
1 WTIF
1 WTIE
1 REF_MSG_x reset value
1 REF_ID
1
1 REF_IDE=
1
1 TRIG_CFG_x reset value
1 TTYPE=
1
1
1
1
1
1
1 TEW=
1
1 TTPTR
1
1 TT_TRIG_x reset value
1 TT_TRIG
1
1 TT_WTRIG_x reset value
1 TT_WTRIG
1 TTCAN message transmission
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 active trigger, no overwrite
1
1
1
1 watch trigger
1
1
1 CiA 603 reset value
1
1 TIMEEN=
1
1 TIMEPOS=
1
1
1
1
1
1
1 TIMECFG unused bits
1 TTS
1 RTS
1 TTSEN=
1
1 single port mem host access +
1
1
1 TBPRI +
1
 subcondition #1 subcondition #2
CAN 2.0
CAN FD
CAN 2.0
CAN FD

CAN 2.0
CAN FD
CAN 2.0
CAN FD

last slot no transmission

bus blocked
other slot no transmission
bus blocked

0
1

each single slot

all slots filled - all read
0 normal operation
LBMI
LBME
1 LBMI

LBME
NO ERROR rx

tx (in loop back mode)

BIT ERROR rx (in the ACK field)
tx
FORM ERROR rx (in the ACK field)
tx
STUFF ERROR rx
tx
ACK ERROR rx (in LOM)
tx
CRC ERROR rx
tx
OTHER ERROR
- -

RESET= 0

0
1
ACF_NUMBER
0 each single AMASK/ACODE bit for all ACF=

1 each single AMASK/ACODE bit for all ACF=

0
1 AIDE=

ACFNUM= ACF_NUMBER_MAX-1

TTS
RACTIVE
TACTIVE
BUSOFF
LOM
LBMI
LBME
TPSS
TSSS
TBSEL
STBY
TPE
TPA
TSONE
TSALL
TSALL TSONE
TSALL
IDE= 0

FD_ISO 0=>1

1=>0

no CAN FD support
TSNEXT
TSMODE
TTTBM
TSSTAT
RREL
RREMOTE
RSTAT
RIE
ROIE
RFIE
RAFIE
TPIE
TSIE
EIE
TSFF
RIF
ROIF
RFIF
RAFIF
TPIF
TSIF
EIF
AIF
EWARN
S_SEG_1
S_SEG_2
S_SJW
S_PRESC
F_SEG_1
F_SEG_2
F_SJW
F_PRESC
AFWL
RECNT
TECNT
SJW
SELMASK
ACFADR
TIMEPOS
TIMEEN
ACF_x
TBPTR
TBF
TBE
TTEN
T_PRESC
TTIF
TTIE
TEIF
WTIF
WTIE
REF_ID
REF_IDE
TT_TRIG
SACK
0
1 normal
after arbitration lost
0
1 normal
during arbitration
0
0=>1
1=>0 plus pending transmission

using forced reset (write 1 to BUSOFF)

wakeup
no standby if transmission active TPE
TSONE
TSALL
no transmission if standby active TPE
TSONE
TSALL
successful during transmission
after transmission
bus blocked
abort
TSONE active
TSALL active
abort transmission active, arbitration will be lost
transmission active, arbitration is lost
interframe space
too late (transmission active)
nothing to abort (no TPE)
together with TPE
during STB transmission TSONE
TSALL
successful slots filled before=

bus blocked
TPE=1 PTB wins
STB completes before
abort
TSALL=already set frames to transmit=

together with TPE

successful slots filled before=

one more slot filled during transmission

bus blocked slot=

TPE=1 PTB wins

 STB completes before

abort
TSONE=already set frames in STB=

TSONE set simultaneously

together with TPE
TSONE abort slots filled before=

transmission active

interframe space
too late (transmission active)
empty one STB slot
together with TSONE
during PTB transmision
TSALL abort slots filled before=

transmission active

interframe space
too late (transmission active)
empty all STB slots
together with TSALL
during PTB transmision
nothing to abort
TPE=1

0 IDE=

1 IDE=

other nodes: ISO

othes nodes: non-ISO
TBSEL= 0

1
together with TSONE
together with TSALL
full STB TTEN=

0 (FIFO)
1 (PRIO) all STB slots

new frame during TSONE lower priority

higher priority
new frame during TSALL lower priority
higher priority
mixed Ids standard and extended
priority reordering incomplete next transmission
new frame
equal priority
0 reference message recognition
PTB transmission
STB transmission

TTYPE_IMME (not allowed)

TTYPE_TIME
TTYPE_TSS (not allowed)
TTYPE_TSTART (not allowed)
TTYPE_TSTOP (not allowed)
1

0
1 1 frame lost
2 frames lost
ROM=

slots filled before= 0

1
RBUF_SLOTS

00b
01b
10b
11b
0
1
0
1

0
1 alone
1 together with all other IEs
0
1 alone
1 together with all other IEs
0
1 alone
1 together with all other IEs
0
1 alone
1 together with all other IEs
0
1 alone
1 together with all other IEs
0
1 alone
1 together with all other IEs
0
1 alone
1 together with all other IEs
0
1

0 none (blocked by ACF)

0 disabled
0 cleared after read
1 alone
1 together with ROIF
1 together with RFIF
1 together with RAFIF
1 together with ROIF+RFIF+RAFIF
0 none
0 disabled
0 cleared after read
1 alone
0 none
0 disabled
0 cleared after read
1 alone
0 none
0 disabled
0 cleared after read
1 alone
0 none
0 disabled
0 cleared after read
1
0 none
0 disabled
0 cleared after read
1 TSONE
TSALL
0 none
0 disabled >EWL

<EWL

BUSOFF=

0 cleared after read

1 >EWL

<EWL

BUSOFF=

0 none
0 cleared after read
1 TPA
1 TSA
1 TPA+TSA (not recommended)

0
1 RECNT
TECNT
0
1
during change (immediate)
0 none
0 disabled TECNT

RECNT

0 cleared after read

1 TECNT

RECNT

0 none
0 disabled
0 cleared after read
1
0 none
0 disabled
0 cleared after read
1

0 S_SEG_1
 S_SEG_2
S_SJW
S_PRESC
F_SEG_1
F_SEG_2
F_SJW
F_PRESC
1 S_SEG_1
S_SEG_2
S_SJW
S_PRESC
F_SEG_1
F_SEG_2
F_SJW
F_PRESC

RESET= 0
1
0
1 with bigger delay
without bigger delay
RESET= 0
1
4 (=F_SEG_1)

AFWL= 0
1
2
RBUF_SLOTS
>RBUF_SLOTS
cdc_new_ewl_done='0'

ALIF= 0
1
value 0-10
0-10
0-28
0-28
11
12
31
0
0
000b no error
001b BIT ERROR
010b form error
form error

011b stuff error

100b ACK error
101b CRC error

110b other error

111b -

0 0
value
>127
decrement for CAN FD with 2 ACKs

0
value
>255
rule c exception 2

reception ACK from other node

no ACK

reception with error error flag from other node

no error flag from other node
no transmission if LOM active TPE
TSONE
TSALL
together with LBME rx

tx

transmission + reception
transmission + reception other nodes active
other nodes in LOM

reception (from other node)

successful
with error no ACK
arbitration lost
TSONE successful
with error
arbitration lost
TSALL successful
with error
arbitration lost

RTR= 0
1

IDE= 0

defaults
S_PRESC=255 F_PRESC=0
S_SEG_1=255 F_SEG_1=0
S_SEG_2=0 S_PRES=0
S_SEG_2=127 F_SEG_2=1
S_PRESC=0 F_PRESC=0
S_SEG_1=0 F_SEG_1=31
S_SEG_1=0 F_SEG_2=15
S_SJW=0 F_SJW=15
S_SJW=127 F_SJW=0
error TDC=

CAN20_STD BaseID(4th)
BaseID(5th)
BaseID(6th)

BaseID(last)
 RTR

IDE
r0
DLC(3)
data(3rd)
data(last)

CRC(1st)

CAN20_STD_remote IDE
DLC(0)
CAN20_EXT ExtID(17)
ExtID(0)

RTR

r1
r0
DLC(3)
data(last)

CRC(1st)

CAN20_EXT_remote r1
CANFD_STD EDL
data(last)

CRC(1st)

CANFD_EXT EDL
CRC(1st)
data(last)

CRC(1st)

CAN_FD stuff error CRC17

 CRC21

stuff count

last bit of error delimiter

last bit of overload delimiter
CAN20_STD r0
CAN20_EXT r1
r0

CANFD_STD res

CANFD_EXT res

CAN20 core is CAN FD tolerant

core is not CAN FD tolerant
CAN20
CANFD
CAN20
CANFD
only own retransmission
joined transmission at 3rd bit of intermission

+1 dominant bit as receiver (REC+8 after 1st additional dominant bit)

+8 dominant bits as transmitter (TEC+8 only after 8 additional dominant bits)
TSONE
TSALL
TSA
TBUF

for Seg2 prescaler=1

for Seg1 prescaler=1
prescaler=1/2

PTB
all STB slots
pointer too big
slot marked as filled (overwrite protection)
0
1
1, together with TBE
0
1
1, while transmission active successful
not successful (bit error)
not successful (arbitration lost)
different slot
1, together with TBF

0
1
cannot be changed if TTEN=1
1
2
4
8

toggle all bits

0
1

immediate trigger TTPTR=

time trigger
single shot transmit trigger TTPTR=

transmit start trigger

transmit stop trigger
0
15
all available slots
too big

TTIF
TEIF

immediate trigger single transmitter

arbitration (retransmission)
arbitration + TSSS + TTPTR=0
TSA + TTPTR=0
 empty slot
TTPTR too big
abort
time trigger valid
too low
single shot transmit trigger single transmitter
bus occupied (abort)
empty slot
TTPTR too big
transmit start trigger single transmitter
arbitration

empty slot
TTPTR too big
transmit stop trigger transmission already completed (empty slot)
bus occupied (abort)
transmission active -> successful
transmission active -> unsuccessful
TTYPE_TIME
TTYPE_TSS
TTYPE_TSTART
TTYPE_TSTOP
valid
valid, at the cycle time
too low
TIMECFG
TTS
0
1
0 tx
rx
RBALL=1 and data frame with error
1 tx
rx
RBALL=1 and data frame with error
write-locked because TIMEEN=1

0
1
TBPRI + ACF
TBDAT
RB
ACF
RB
 subcondition #3 subcondition #4 subcondition #5

(TBUF write-locked)
(TBUF write-locked)
(TBUF write-locked)
(TBUF write-locked)

PTB used
STB used

RBALL= 0
1
SELMASK= 0 ACFADR=

SELMASK= 0 ACFADR=

SELMASK= 0 ACFADR=

SELMASK= 0 ACFADR=

0 match others bits=

0 no match others bits=

1 match others bits=

1 no match others bits=

0 match others bits=

0 no match others bits=

1 match others bits=

1 no match others bits=

0 match
no match
1 match
no match
SELMASK= 0
1

TPE
TSONE
TSALL
TPE
TSONE
TSALL
RESET= 0
1
RESET= 0
1
128*11=1408 recessive bits without dominant bits between
with dominant bits between

0
1
STB_SLOTS

2
1 (last)

0
1
STB_SLOTS

1st
2nd
last
1 frame
all frames

1
2

1
2
STB_SLOTS
arbitration will be lost
arbitration is lost

1
2
STB_SLOTS
arbitration will be lost
arbitration is lost

0 use
verify
1 use
verify
0 use
verify
1 use
verify

with TSNEXT
no TSNEXT

0
1
reorder after write to slot
reorder after write to last slot

FIFO mode TSONE

TSALL
PRIO mode TSALL

0
1

release= before new reception

during new reception
no release new frame= valid
invalid
blocked by ACF
TECNT
RECNT
TECNT
RECNT
0
1

TECNT
RECNT
TECNT
RECNT
0
1

switch to error passive mode

switch to error active mode
switch to error passive mode
switch to error active mode

switch to error passive mode

switch to error active mode
switch to error passive mode
switch to error active mode
(SSP shiftbits = 2)
(SSP shiftbits = 0)

BaseID standard ID all arbitration bits

BaseID standard ID all arbitration bits
BaseID, ExtID extended ID all arbitration bits
BaseID, ExtID extended ID all arbitration bits
RTR / SRR last STD arbitration bit
DIE STD remote vs. EXT
RTR last EXT arbitration bit
(error) after last STD arbitration bit
(error) after last EXt arbitration bit

tx: stuff bit in arbitration phase

fixed stuff bit stuff bit count and CRC17
stuff bit count and CRC21

CRC
stuff count

active error flag

passive error flag

ACK from other node

no ACK
SACK= 0
1

SACK= 0
1

no ACK
no ACK

IDE= 0 BRS=

1 BRS=

DLC= 0
7
8
12
16
20
24
32
48
64
DLC= 0
7
8
12
16
20
24
32
48
64

=> F_SEG_2=0 => F_SJW=0

=> S_SEG_1=128 => F_SJW=0

=> S_SEG_2=0 => S_SJW=0

=> F_SEG_1=16 => S_SJW=0
=> F_SEG_2=15 => F_SEG_1=16
=> S_SEG_2=127 => S_SEG_1=128
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
1
0
1
1
0
0 CRC17
CRC21
1 CRC17
CRC21
0 CRC17
CRC21
1 CRC17
CRC21
0
0 (DLC=0)
0 CRC17
CRC21
1 CRC17
CRC21
0 CRC17
CRC21
1 CRC17
CRC21
bit= 0
4
8
 12
16
bit= 0
4
8
12
16
20
bit= 0

CAN_FD= disabled
enabled
upward compatible frame ignored
verification: 11 bits for bus integration
not upward compatible
upward compatible frame ignored
not upward compatible

TEC>=128
REC>=128

slow=6/2 TQ fast=6/2 TQ
slow=5/3 TQ fast=5/3 TQ
slow=2/1 TQ fast=2/1 TQ (outside spec.)
0
1

0
1
TSSS= 0 (retransmission)
1 (single shot)
 number of tests 762
number of passed tests 762

subcondition #6 test name state [0=open, 1=passed]

testvec_tb_ptb 1
testvec_tb_ptb 1
testvec_tb_ptb 1
testvec_tb_ptb 1
testvec_tb_rb_* 1
testvec_TBUF_1 1
testvec_TBUF_1 1
testvec_tb_ptb 1
testvec_frames_1 1
testvec_tb_stb 1
testvec_tb_stb 1
testvec_tb_stb 1
testvec_tb_stb 1
testvec_tb_rb_2 1
testvec_secondary_3 1
testvec_TBUF_2 1
testvec_TBUF_2 1
testvec_TBUF_3 1
testvec_TBUF_3 1
testvec_TBUF_2 1
testvec_tb_stb 1
testvec_frames_1 1
testvec_secondary_29 1
testvec_frames_1 1
testvec_error_6_7 1
testvec_error_6_6 1
testvec_ttcan_* 1
testvec_tb_rb_2 1
testvec_tb_rb_3 1
testvec_tb_rb_3 1
impossible 1
testvec_rb_01 1
testvec_special_features_1aa 1
testvec_special_features_1ab 1
testvec_special_features_1c 1
testvec_tb_rb_3 1
testvec_rb_02 1
testvec_rb_03 1
testvec_rb_04 1
testvec_rb_05 1
testvec_rb_04 1
testvec_rb_04 1
testvec_rb_05 1
impossible 1
 testvec_rb_07 1
testvec_rb_07 1
testvec_rb_08 1
impossible 1
impossible 1
0 testvec_reset_value_acf 1
1 testvec_reset_value_acf 1
2 testvec_reset_value_acf 1
0 testvec_reset_value_acf 1
1 testvec_reset_value_acf 1
2 testvec_reset_value_acf 1
0 testvec_bit_RESET_acode 1
1 testvec_bit_RESET_acode 1
2 testvec_bit_RESET_acode 1
0 testvec_bit_RESET_acode 1
1 testvec_bit_RESET_acode 1
2 testvec_bit_RESET_acode 1
0 testvec_acf_1, testvec_acf_3 1
1 testvec_acf_1, testvec_acf_3 1
2 testvec_acf_1, testvec_acf_3 1
0 testvec_acf_1, testvec_acf_3 1
1 testvec_acf_1, testvec_acf_3 1
2 testvec_acf_1, testvec_acf_3 1
0 testvec_acf_1 1
1 testvec_acf_1 1
2 testvec_acf_1 1
0 testvec_acf_1 1
1 testvec_acf_1 1
2 testvec_acf_1 1
testvec_acf_7 1
testvec_acf_4* 1
testvec_acf_6* 1
0 testvec_acf_4_1* 1
1 testvec_acf_4_2* 1
0 testvec_acf_4_3* 1
1 testvec_acf_4_4* 1
0 testvec_acf_4_7* 1
1 testvec_acf_4_8* 1
0 testvec_acf_4_5* 1
1 testvec_acf_4_6* 1
0 testvec_acf_5_1* 1
1 testvec_acf_5_2* 1
0 testvec_acf_5_3* 1
1 testvec_acf_5_4* 1
0 testvec_acf_5_7* 1
1 testvec_acf_5_8* 1
0 testvec_acf_5_5* 1
1 testvec_acf_5_6* 1
testvec_acf_8 1
testvec_acf_4*, testvec_acf_5 1
testvec_acf_8a 1
testvec_acf_8b 1
testvec_acf_8c 1
testvec_acf_8d 1
testvec_acf_9 1
testvec_acf_9 1
testvec_reset_value_cfg 1
testvec_cia603_01d 1
testvec_swreset_1_2 1
testvec_swreset_1_3 1
testvec_error_4_1 1
testvec_swreset_12 1
testvec_special_features_2a 1
testvec_special_features_2b 1
testvec_swreset_12 1
testvec_swreset_12 1
testvec_swreset_2 1
testvec_special_features_7d 1
testvec_swreset_1_1 1
testvec_swreset_3 1
testvec_swreset_2_1 1
testvec_swreset_2_2 1
testvec_swreset_4_1 1
testvec_swreset_4_2 1
testvec_swreset_1_1 1
testvec_swreset_2_1 1
testvec_swreset_2_2 1
testvec_swreset_1_4 1
testvec_swreset_2_3 1
testvec_swreset_2_4 1
testvec_swreset_13c 1
testvec_swreset_13d 1
testvec_swreset_13a 1
testvec_swreset_13b 1
testvec_swreset_14 1
testvec_swreset_5 1
testvec_swreset_5 1
testvec_swreset_5 1
testvec_swreset_2_1 1
testvec_swreset_6 1
testvec_swreset_7 1
testvec_swreset_6 1
testvec_swreset_8 1
testvec_swreset_8 1
testvec_swreset_8 1
testvec_swreset_8 1
testvec_swreset_8 1
testvec_swreset_8 1
testvec_swreset_8 1
testvec_swreset_9 1
testvec_swreset_10 1
testvec_swreset_10 1
testvec_swreset_10 1
testvec_swreset_10 1
testvec_swreset_10 1
testvec_swreset_11 1
testvec_error_3_3 1
testvec_swreset_10 1
testvec_error_3_3 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_presc 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_presc 1
testvec_swreset_10 1
testvec_error_1 1
testvec_error_1 1
testvec_bit_RESET_acfctrl 1
testvec_bit_RESET_acode 1
testvec_bit_RESET_acode 1
testvec_swreset_17 1
testvec_swreset_17 1
testvec_bit_RESET_acode 1
testvec_swreset_15 1
impossible 1
impossible 1
testvec_swreset_16 1
testvec_swreset_16 1
testvec_ttcan_18 1
testvec_swreset_16 1
testvec_ttcan_19 1
testvec_ttcan_20 1
testvec_swreset_16 1
testvec_ttcan_21 1
testvec_ttcan_21 1
testvec_ttcan_19 1
testvec_special_features_2d 1
testvec_com_1_* 1
testvec_com_1_1 1
testvec_com_2_1 1
testvec_com_1_* 1
testvec_com_1_2 1
testvec_com_2_1 1
testvec_com_1_* 1
testvec_error_4_1 1
testvec_error_4_2a 1
testvec_error_4_2b 1
testvec_error_4_3 1
testvec_reset_value_cfg 1
done in various tests 1
testvec_special_features_3 1
testvec_special_features_4 1
testvec_special_features_5 1
testvec_special_features_6 1
testvec_special_features_7a 1
testvec_special_features_7b 1
testvec_special_features_7c 1
testvec_com_1_2 1
testvec_com_1_* 1
testvec_com_2_* 1
testvec_com_4 1
testvec_secondary_2 1
testvec_secondary_8 1
testvec_com_4 1
testvec_com_5 1
testvec_com_6 1
testvec_com_7 1
testvec_com_8 1
testvec_com_3 1
testvec_secondary_4 1
testvec_secondary_5 1
testvec_secondary_6 1
testvec_secondary_1 1
testvec_secondary_3 1
testvec_secondary_7 1
testvec_secondary_16 1
testvec_secondary_17 1
testvec_secondary_23_1 1
testvec_secondary_13 1
testvec_secondary_12_* 1
testvec_secondary_30_1 1
testvec_secondary_6 1
testvec_secondary_9 1
testvec_secondary_10 1
testvec_secondary_11 1
testvec_secondary_20 1
testvec_secondary_20 1
testvec_secondary_20 1
testvec_secondary_18 1
testvec_secondary_19_2 1
testvec_secondary_19_1 1
testvec_secondary_23_2 1
testvec_secondary_14_1 1
testvec_secondary_14_2 1
testvec_secondary_15 1
testvec_secondary_30_2 1
testvec_secondary_23_1 1
testvec_secondary_24 1
testvec_secondary_26_1 1
testvec_secondary_27_1 1
testvec_secondary_27_3 1
testvec_secondary_27_5 1
testvec_secondary_28_1 1
testvec_secondary_22_2 1
testvec_secondary_21_1 1
testvec_secondary_30_1 1
testvec_secondary_23_2 1
testvec_secondary_25 1
testvec_secondary_26_2 1
testvec_secondary_27_2 1
testvec_secondary_27_4 1
testvec_secondary_27_6 1
testvec_secondary_28_2 1
testvec_secondary_29 1
testvec_secondary_21_2 1
testvec_secondary_30_2 1
testvec_secondary_22_1 1
testvec_hostif_1 1
testvec_reset_value_cfg 1
testvec_TCTRL_1_1 1
testvec_TCTRL_1_1 1
testvec_TCTRL_1_2 1
testvec_TCTRL_1_2 1
testvec_TCTRL_2 1
testvec_TCTRL_2 1
testvec_TCTRL_2 1
testvec_TCTRL_2 1
testvec_fd_36a 1
testvec_fd_36b 1
testvec_com_1_x 1
testvec_TCTRL_1_1 1
testvec_secondary_6 1
tbench_apb 1
tbench_apb 1
done in STB tests 1
testvec_ttcan_07 1
done in STB tests 1
testvec_prio_01a 1
testvec_prio_01b 1
testvec_prio_02a 1
testvec_prio_02b 1
testvec_prio_03a 1
testvec_prio_03b 1
testvec_prio_04 1
testvec_prio_01c 1
testvec_prio_01c 1
testvec_prio_01d 1
testvec_tttbm_01a 1
testvec_tttbm_01a 1
testvec_tttbm_01b 1
testvec_tttbm_01c 1
testvec_tttbm_01d 1
testvec_tttbm_02a 1
testvec_tttbm_02e 1
testvec_tttbm_02b 1
testvec_tttbm_02c 1
testvec_tttbm_02d 1
testvec_ttcan_* 1
testvec_secondary_10 1
testvec_reset_value_cfg 1
testvec_RCTRL_4a 1
testvec_RCTRL_4a 1
testvec_interrupt_6 1
testvec_RCTRL_4a 1
testvec_RCTRL_4b 1
testvec_RCTRL_1 1
testvec_com_1_* 1
testvec_RCTRL_2 1
testvec_RCTRL_3 1
testvec_RCTRL_4a 1
testvec_RCTRL_5 1
testvec_RCTRL_5 1
testvec_RCTRL_1 1
testvec_RCTRL_2 1
testvec_RCTRL_2 1
testvec_RCTRL_4a 1
testvec_tb_rb_3 1
testvec_rb_04 1
testvec_special_features_1b 1
testvec_special_features_1d 1
testvec_reset_value_cfg 1
testvec_reset_value_cfg 1
testvec_interrupt_6 1
testvec_interrupt_1 1
testvec_interrupt_1 1
testvec_interrupt_5 1
testvec_interrupt_6 1
testvec_RCTRL_4a 1
testvec_interrupt_6 1
testvec_interrupt_7 1
testvec_RCTRL_2 1
testvec_interrupt_5 1
testvec_interrupt_2 1
testvec_RCTRL_2 1
testvec_interrupt_4 1
testvec_interrupt_1 1
testvec_com_1_* 1
testvec_interrupt_3 1
testvec_interrupt_2 1
testvec_secondary_1 1
testvec_error_3_1 1
testvec_error_2_1 1
testvec_error_2_1 1
testvec_secondary_9 1
testvec_secondary_10 1
testvec_reset_value_cfg 1
testvec_acf_6* 1
testvec_interrupt_2 1
testvec_interrupt_1 1
testvec_interrupt_1 1
testvec_interrupt_4 1
testvec_interrupt_5 1
testvec_interrupt_2 1
testvec_interrupt_8 1
testvec_interrupt_6 1
testvec_interrupt_4 1
testvec_interrupt_6 1
testvec_interrupt_6 1
testvec_interrupt_7 1
testvec_interrupt_4 1
testvec_interrupt_7 1
testvec_interrupt_7 1
testvec_interrupt_3 1
testvec_interrupt_5 1
testvec_com_1_4 1
testvec_interrupt_3 1
testvec_interrupt_3 1
testvec_interrupt_4 1
testvec_interrupt_1 1
testvec_interrupt_1 1
testvec_interrupt_4 1
testvec_interrupt_3 1
testvec_interrupt_2 1
testvec_interrupt_2 1
testvec_tb_rb_3 1
testvec_error_1 1
testvec_error_3_1 1
testvec_error_3_1 1
testvec_error_3_2 1
testvec_error_3_2 1
testvec_error_5_2 1
testvec_error_5_1 1
testvec_error_2_1 1
testvec_error_2_1 1
testvec_error_2_1 1
testvec_error_2_2 1
testvec_error_2_2 1
testvec_error_4_1 1
testvec_error_4_1 1
testvec_interrupt_1 1
testvec_interrupt_9_* 1
testvec_com_3 1
testvec_secondary_21_1 1
testvec_interrupt_9_* 1
testvec_reset_value_error 1
testvec_TBUF_2 1
testvec_error_3_1 1
testvec_error_3_1 1
testvec_error_6_1 1
testvec_error_6_2 1
testvec_error_8_2 1
testvec_error_6_0 1
testvec_error_7 1
testvec_error_7 1
testvec_error_9 1
testvec_error_9 1
testvec_error_6_3 1
testvec_error_6_2 1
testvec_error_6_4 1
testvec_error_8_1 1
testvec_error_8_2 1
testvec_error_12 1
testvec_error_14 1
testvec_error_12 1
testvec_error_12 1
testvec_error_11 1
testvec_error_7 1
testvec_error_11 1
testvec_error_11 1
testvec_reset_value_timing 1
testvec_bit_RESET_bittime 1
 testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_presc 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_bittime 1
testvec_bit_RESET_presc 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_timing_1_* 1
testvec_reset_value_timing 1
testvec_bit_RESET_tdc 1
testvec_fd_31a 1
testvec_fd_33 1
testvec_fd_31a 1
testvec_fd_31b 1
testvec_bit_RESET_tdc 1
testvec_fd_31a 1
testvec_fd_31a 1
testvec_fd_37 1
testvec_fd_34 1
testvec_reset_value_error 1
testvec_RCTRL_4a 1
testvec_com_1_* 1
testvec_com_2_* 1
testvec_interrupt_10 1
testvec_interrupt_11 1
testvec_hostif_2 1
testvec_reset_value_error 1
testvec_error_14 1
testvec_error_12 1
others 0 testvec_error_15a1 1
others 1 testvec_error_15a1 1
others 0 testvec_error_15a3 1
others 1 testvec_error_15a4 1
testvec_error_16 1
testvec_error_18 1
testvec_error_17 1
testvec_error_18 1
testvec_error_19 1
testvec_error_15a1 1
testvec_error_18b 1
testvec_rb_06 1
testvec_error_2_1 1
testvec_error_20 1
testvec_error_21 1
testvec_error_18 1
testvec_error_6_2 1
testvec_error_2_1 1
testvec_error_22 1
testvec_error_2_1 1
not used 1
testvec_reset_value_error 1
testvec_TBUF_2 1
testvec_error_1 1
testvec_error_3_5 1
testvec_error_27 1
testvec_reset_value_error 1
testvec_TBUF_2 1
testvec_error_1 1
testvec_error_4_1 1
testvec_error_25 1
testvec_error_26 1
testvec_reset_value_timing 1
testvec_acf_1 1
testvec_acf_1 1
testvec_acf_1 1
testvec_reset_value_timing 1
testvec_special_features_8 1
testvec_special_features_9 1
testvec_special_features_9 1
testvec_special_features_13a 1
testvec_special_features_13b 1
testvec_special_features_14a 1
testvec_special_features_14b 1
testvec_special_features_14c 1
testvec_rb_11 1
testvec_rb_13 1
testvec_rb_13 1
testvec_rb_12 1
testvec_special_features_1a 1
testvec_special_features_1c 1
testvec_special_features_1b 1
testvec_special_features_1d 1
testvec_rb_01 1
testvec_special_features_8 1
testvec_special_features_9 1
testvec_error_15b 1
testvec_special_features_10a 1
testvec_special_features_11 1
testvec_error_15c 1
 testvec_special_features_10b 1
testvec_special_features_12 1
testvec_error_15d 1
testvec_behavior_1 1
testvec_behavior_2 1
testvec_error_6_x 1
testvec_fd_20 1
0 testvec_fd_22_1 1
1 testvec_fd_22_3 1
0 testvec_fd_22_2 1
1 testvec_fd_22_4 1
testvec_fd_1 1
testvec_fd_2 1
testvec_fd_3 1
testvec_fd_4 1
testvec_fd_5 1
testvec_fd_6 1
testvec_fd_7 1
testvec_fd_8 1
testvec_fd_9 1
testvec_fd_10 1
testvec_fd_11 1
testvec_fd_12 1
testvec_fd_13 1
testvec_fd_14 1
testvec_fd_15 1
testvec_fd_16 1
testvec_fd_17 1
testvec_fd_18 1
testvec_fd_19 1
testvec_fd_20 1
testvec_fd_21 1
(others default) testvec_fd_23 1
(others default) testvec_fd_24a 1
(no BRS) testvec_fd_24b 1
(others default) testvec_fd_25 1
(others default) testvec_fd_26 1
(others default) testvec_fd_27 1
(others default) testvec_fd_28 1
(others default) testvec_fd_29 1
(others default) testvec_fd_30 1
testvec_fd_32a 1
testvec_fd_32b 1
testvec_stuff_1 1
testvec_stuff_2 1
testvec_stuff_3 1
testvec_stuff_4 1
testvec_stuff_5 1
testvec_stuff_6 1
testvec_stuff_7 1
testvec_stuff_8 1
testvec_stuff_9 1
testvec_stuff_10 1
testvec_stuff_11 1
testvec_stuff_12 1
testvec_stuff_13 1
testvec_stuff_14 1
testvec_stuff_15 1
testvec_stuff_16 1
testvec_stuff_17 1
testvec_stuff_18 1
testvec_stuff_19 1
testvec_stuff_20 1
testvec_stuff_21 1
testvec_stuff_22 1
testvec_stuff_23 1
testvec_stuff_24 1
testvec_stuff_25 1
testvec_stuff_26 1
testvec_stuff_27 1
testvec_stuff_28 1
testvec_stuff_29 1
testvec_stuff_30 1
testvec_stuff_31 1
testvec_stuff_32 1
testvec_stuff_33 1
testvec_stuff_35 1
testvec_stuff_34 1
testvec_stuff_36 1
testvec_stuff_37 1
testvec_stuff_38 1
testvec_stuff_39 1
testvec_stuff_40 1
testvec_stuff_41 1
testvec_stuff_42 1
testvec_stuff_43 1
testvec_stuff_44 1
testvec_stuff_45 1
testvec_stuff_46 1
testvec_stuff_47 1
testvec_stuff_48 1
testvec_stuff_49 1
testvec_stuff_50 1
testvec_stuff_51 1
testvec_stuff_52 1
testvec_stuff_53 1
testvec_stuff_54 1
testvec_stuff_55 1
testvec_stuff_56 1
testvec_stuff_57 1
testvec_stuff_58 1
testvec_stuff_59 1
testvec_stuff_60 1
testvec_stuff_61 1
testvec_stuff_62 1
testvec_protocol_special_01 1
testvec_protocol_special_02 1
testvec_protocol_special_03 1
testvec_protocol_special_04 1
testvec_protocol_special_05 1
testvec_protocol_special_06 1
testvec_protocol_special_07 1
testvec_protocol_special_08 1
testvec_protocol_special_18 1
testvec_protocol_special_12 1
testvec_protocol_special_09 1
testvec_protocol_special_13 1
testvec_protocol_special_10 1
testvec_protocol_special_11 1
testvec_protocol_special_15 1
testvec_protocol_special_14 1
testvec_protocol_special_17 1
testvec_protocol_special_16 1
testvec_error_23 1
testvec_error_24a 1
testvec_error_28 1
testvec_error_24b 1
Bosch testbench EML 1
testvec_error_29* 1
testvec_secondary_31 1
testvec_secondary_32 1
testvec_secondary_33 1
testvec_tb 1
testvec_timing_1_1 1
testvec_timing_1_2 1
testvec_timing_1_3 1
testvec_timing_1_4 1
testvec_timing_1_5 1
testvec_reset_value_ttcan 1
testvec_ttcan_07 1
testvec_ttcan_07 1
testvec_ttcan_11 1
testvec_ttcan_17a 1
testvec_ttcan_03d 1
testvec_ttcan_07 1
testvec_ttcan_12 1
testvec_ttcan_10 1
testvec_ttcan_07 1
testvec_ttcan_08 1
testvec_ttcan_09 1
testvec_ttcan_10 1
testvec_ttcan_08 1
testvec_ttcan_12 1
testvec_reset_value_ttcan 1
all CAN tests, testvec_ttcan_00 1
all TTCAN tests 1
testvec_ttcan_13a 1
testvec_ttcan_01b 1
testvec_ttcan_13b 1
testvec_ttcan_13c 1
testvec_ttcan_13d 1
testvec_ttcan_02a 1
testvec_ttcan_02b 1
testvec_ttcan_02c 1
testvec_ttcan_06a 1
testvec_ttcan_06d 1
testvec_reset_value_ttcan 1
testvec_ttcan_01b 1
testvec_ttcan_22 1
testvec_ttcan_01a 1
testvec_ttcan_01b 1
testvec_reset_value_ttcan 1
testvec_ttcan_01b 1
testvec_ttcan_03c 1
testvec_ttcan_02a 1
testvec_ttcan_04a 1
testvec_ttcan_04b 1
testvec_ttcan_05a 1
testvec_ttcan_05c 1
testvec_ttcan_04b 1
testvec_ttcan_04c 1
testvec_ttcan_14a 1
testvec_ttcan_15* 1
testvec_reset_value_ttcan 1
testvec_ttcan_02a 1
testvec_ttcan_02c 1
testvec_reset_value_ttcan 1
testvec_ttcan_06* 1
testvec_ttcan_01b 1
testvec_ttcan_03a 1
testvec_ttcan_03b 1
testvec_ttcan_03c 1
testvec_ttcan_03d 1
testvec_ttcan_15a 1
testvec_ttcan_03e 1
testvec_ttcan_02a 1
testvec_ttcan_02c 1
testvec_ttcan_04a 1
testvec_ttcan_04b 1
testvec_ttcan_04d 1
testvec_ttcan_15b 1
testvec_ttcan_05a 1
testvec_ttcan_05e 1
testvec_ttcan_05f 1
testvec_ttcan_05d 1
testvec_ttcan_15c 1
testvec_ttcan_05b 1
testvec_ttcan_05c 1
testvec_ttcan_05g 1
testvec_ttcan_05g 1
testvec_ttcan_16a 1
testvec_ttcan_16b 1
testvec_ttcan_16d 1
testvec_ttcan_16d 1
testvec_ttcan_06a 1
testvec_ttcan_06b 1
testvec_ttcan_06c 1
testvec_reset_value_cia603 1
testvec_reset_value_cfg 1
testvec_cia603_01b 1
testvec_cia603_01a 1
testvec_cia603_01a 1
testvec_cia603_01a 1
testvec_rb_10 1
testvec_cia603_01c 1
testvec_cia603_01a 1
testvec_rb_09 1
testvec_swreset_17 1
testvec_cia603_03 1
testvec_cia603_01a 1
testvec_cia603_01a 1
testvec_cia603_04b 1
testvec_cia603_04a 1
testvec_memtraffic_01 1
testvec_memtraffic_01 1
testvec_memtraffic_01 1
testvec_memtraffic_03 1
testvec_memtraffic_02 1
comment
others covered by ISO 116845-1 tests using a Verification IP
package RBUF_SLOTS STB_SLOTS STB_PRIO ACF_NUMBER CAN_FD
can_package_synparam_vip_1 8 3 0 1 0
can_package_synparam_vip_2 2 3 1 1 1
can_package_synparam_vip_3 15 3 1 9 0
can_package_synparam_4 2 1 1 3 0
can_package_synparam_5 64 16 1 16 0
can_package_synparam_6 3 0 1 3 1
TBENCH_* RAM_MEMTYPE RAM_TYPE UPWARD_COMPATIBILITY SHORT_SEG2 TTCAN
0 1 0 0 0 1
0 3 0 1 1 0
0 3 0 1 1 0
0 2 2 1 1 0
0 4 3 1 1 1
1 3 0 0 1 0
CIA603 CIA603_CLK
2 0
2 3
0 0
1 1
1 2
0 0