COMPUTER ORGANIZATION AND ARCHITECHTURE

UNIT - 1
INTRODUCTION OF DIGITAL COMPUTER:

• The digital computer is a digital system that performs various computational tasks.
• Digital computers usethe binary number system, which has two digits : 0 and 1. A binary digit is
called a bit.
• A sequence of instructions for the computer is called program. The data that are manipulated by by
program constitute the database. Computer consist of hardware and software.
• Two types of software are available in computer, they are system software and Application software.

• The system software will make use of computer very effectively.

SYSTEM SOFTWARE:
Operating Software:
System software that manages computer hardware, and software resources, and provides common services for
computer programs.

Utility Software:
Utility software are DBMS, excel, word.
Device Driver:
A particular form of software application that allows one hardware device to interact with another hardware
device. Device driver is also called as software driver.

Firmware:
Combination of both hardware and software.
Language Translator:
Language translators are compilers like C, JAVA, C++.
APPLICATION SOFTWARE:
• Application programs are like payroll, student system, railway reservation software.

BLOCK DIAGRAM OF DIGITAL COMPUTER

A computer in its simplest form comprises five functional units namely input unit, output
unit memory unit, arithmetic & logic unit and control unit.
Below figure depicts the functional units of a computer system.

Input unit:
• Take the data to be processed by the user.
• Convert the given data into machine-readable form.
• And then, transmit the converted data into the main memory of the computer. The sole purpose is to
connect the user and the computer. In addition, this creates easy communication between them.
Example include mouse, joystick,Tracker ball, Light pen,Digitizer, scanner etc
Memory Unit:
•
Memory unit stores the program instructions (Code), data and results of
computations etc.
• The memory unit works in sync with the CPU. This helps in faster accessing and
processing of the data. Thus, making tasks easier and quicker.
Memory unit is classified as:
• Primary /Main Memory/Volatile Memory
• Secondary /Auxiliary Memory/Non Volatile
Primary memory – This type of memory cannot store a vast amount of data. Therefore, it is only used to
store recent data. The data stored in this is temporary. It can get erased once the power is switched off.
Therefore, is also called temporary memory or main memory.
RAM stands for Random Access Memory. It is an example of primary memory. This memory is directly
accessible by the CPU. It is used for reading and writing purposes. For data to be processed, it has to be first
transferred to the RAM and then to the CPU.

Secondary memory – As explained above, the primary memory stores temporary data. Thus it
cannot be accessed in the future. For permanent storage purposes, secondary memory is used. It is
also called permanent memory or auxiliary memory. The hard disk is an example of secondary
memory. Even in a power failure data does not get erased easily.
Control Unit:(CU)

• The control unit as the name suggests is the controller of all the activities/tasks and operations. All
this is performed inside the computer.
• The memory unit sends a set of instructions to the control unit. Then the control unit in turn converts
those instructions. After that these instructions are converted to control signals.
• These control signals help in prioritizing and scheduling activities. Thus, the control unit coordinates
the tasks inside the computer in sync with the input and output units.

Arithmetic and Logical unit:(ALU)

The Arithmetic Logic Unit is made of two terms, arithmetic and logic. There are two primary functions that
this unit performs.
• Data is inserted through the input unit into the primary memory. Performs the basic arithmetical
operation on it. Like addition, subtraction, multiplication, and division. It performs all sorts of
calculations required on the data. Then sends back data to the storage.
• The unit is also responsible for performing logical operations like AND, OR, Equal to, Less than, etc.
In addition to this it conducts merging, sorting, and selection of the given data.

Output Unit:

Computer after computations returns the computed result, error messages etc via output unit.
Devices like printers, monitors, projectors, etc. all come under the output unit.
Additional requirement of memory could be supplied as auxiliary memory at cheaper cost.
Secondary memories are non-volatile in nature. Hard disk, CD, DVD, Floppy.
Tape devices are examples of Tertiary Memory.
 COMPUTER ARCHITECTURE AND COMPUTER ORGANIZATION

Computer Architecture

Computer Organization

MICROOPERATION AND REGISTER TRANSFER LANGUAGE:

Registers contain data and operations are performed on the data stored in them. The
operations executed on data stored in registers are called microoperations. A microoperation
is an elementary operation performed on the data stored in one or more registers. The
result of the operation may replace the previous data of a register or may be transferred
to another register. Examples of microoperations are shift, count, clear, and load.

The symbolic notation used to describe the microoperation transfers among registers is
called a register transfer language.
1) Computer registers are designated by capital letters to denote the function of the register.
For example:
memory address register and is designated by the name MAR.
PC (for program counter),
IR (for instruction register),
R1 (for processor register).

R1 7 6 5 4 3 2 1 0

2.1 a) Register R 2.1 b) Showing individual bits

15 0 8 7 0

R2 PC(H) PC(L)

2.1 c) Numbering of bits 2.1 d) Divided into two parts

2) The most common way to represent a register is by a rectangular box with the
name of the register inside, as in Fig.2.1 (a).
3) The individual flip-flops in an n-bit register are numbers in sequence from 0
through n-1, starting from 0 in the rightmost position and increasing the numbers
toward the left. Fig.2.1b.
4) The numbering of bits in a 16-bit register can be marked on top of the box as
shown in2.1(c).
5) A 16-bit register is partitioned into two parts in 2.1 (d). Bits. 0 through 7 are
assigned the symbol L (for low byte) and bits 8 through 15 are assigned
the symbol H (for high byte). The name of the 16-bit register is PC. The
symbol PC (0-7) or PC (L) refers to the low-order byte and PC (8-15) or PC
(H) to the high-order byte.
6) The statement R2← R1 denotes a transfer of the content of register R1 into
register R2. It designates a replacement of the content of R2 by the content of
R1. By definition, the content of the source register R1 does not change after
the transfer.
7) Normally, we want the transfer to occur only under a predetermined
control condition. This can be shown by means of an if-then statement.
If (P = 1) then (R2← R1 )
where P is a control signal generated in the control section. A control function is
a Boolean variable that is equal to 1 or 0. The control function is included in the
statement as follows:
P: R2← R1
The control condition is terminated with a colon. It symbolizes the
requirement that the transfer operation be executed by the hardware only if P
= 1.
8) Fig.2.2 shows the block diagram to show the transfer from R1 to R2.
 The n outputs of register R1 are connected to the n inputs of register
R2.
  The letter n will be used to indicate any number of bits for the
register. It will be replaced by an actual number when the length of
the register is known.
 Register R2 has a load input that is activated by the control variable
P. It is assumed that the control variable is synchronized with the
same clock as the one applied to the register.
 As shown in the timing diagram (b), P is activated in the control
section by the rising edge of a clock pulse at time t. The next positive
transition of the clock at time t + 1 finds the load input active and the
data inputs of R2 are then loaded into the register in parallel. P may
go back to 0 at time t + 1; otherwise, the transfer will occur with
every clock pulse transition while P remains active.

Fig. 2.2: Transfer from R1 to R2 when P = 1

MULTIpLEXWER
It is a combinational circuit which have many data inputs and single output depending on
control or select inputs. Multiplexers are also known as parallel to serial convertor,
many to one circuit, universal logic circuit”. Multiplexers are mainly used to increase
amount of the data that can be sent over the network within certain amount of time and
bandwidth.

Bus
A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be excessive if
separate lines are used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between registers in
a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by the
bus during a particular register transfer.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The
selection lines choose the four bits of one register and transfer them into the four-line common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the bus
lines to receive the content of register A since the outputs of this register are connected to the 0 data
inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided
by register B.

The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.

A bus system can also be constructed using three-state

gates instead of multiplexers.
The three state gates can be considered as a digital circuit that has three
gates, two of which are signals equivalent to logic 1 and 0 as in a conventional
gate. However, the third gate exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is
a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point of
time.

Memory Transfers
Most of the standard notations used for specifying operations on memory transfer are stated below.

o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

Read: DR ← M [AR]
 o The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:
o The Write statement causes a transfer of information from register R1 into the memory word
(M) selected by address register (AR).

Arithmetic Microoperations:
A microoperation is an elementary operation performed with the data stored in
registers. The microoperations most often encountered in digital computers are classified into
four categories:
• Register transfer microoperations transfer binary information from one register
to another.
• Arithmetic microoperations perform arithmetic operations on numeric data stored in
registers.
• Logic microoperations perform bit manipulation operations on non-numeric data stored in
registers.
• Shift microoperations perform shift operations on data stored in registers.

Addition –
In addition micro-operation, the value in register R1 is added to the value in the register R2 and then
the sum is transferred into register R3.

Subtraction –
In subtraction micro-operation, the contents of register R2 are subtracted from contents of the
register R1, and then the result is transferred into R3.

There is another way of doing the subtraction. In this, 2’s complement of R2 is added to R1, which is
equivalent to R1 – R2, and then the result is transferred into register R3.

Increment –
In Increment micro-operation, the value inside the R1 register is increased by 1.

Decrement –
In Decrement micro-operation, the value inside the R1 register is decreased by 1.
 1’s Complement –
In this micro-operation, the complement of the value inside the register R1 is taken.

2’s Complement –
In this micro-operation, the complement of the value inside the register R2 is taken and then 1 is
added to the value and then the final result is transferred into the register R2. This process is also
called Negation. It is equivalent to -R2.

Table 2.3: Arithmetic Microoperations

Binary Adder:
The digital circuit that forms the arithmetic sum of two bits and a previous carry is called a full-
adder. The digital circuit that generates the arithmetic sum of two binary numbers of any lengths is
called a binary adder. The binary adder is constructed with full-adder circuits connected in
cascade, with the output carry from one full-adder connected to the input carry of the next
full-adder. Fig.2.6 shows the interconnections of four full-adders (FA) to provide a 4-bit binary
adder. The augend bits of A and the addend bits of B are designated by subscript numbers
from right to left, with subscript 0 denoting the low-order bit. The carries are connected in a
chain through the full-adders. The input carry to the binary adder is C 0 and the output carry is C 4.
The S outputs of the full-adders generate the required sum bits.

Fig. 2.6: 4-bit binary adder

An n-bit binary adder requires n full-adders. The output carry from each full-adder
is connected to the input carry of the next-high-order full-adder. The n data bits for the A
inputs come from one register (such as R1), and the n data bits for the B inputs come
from another register (such as R2). The sum can be transferred to a third register or to
one of the source registers (R1 or R2), replacing its previous content.
Binary Adder-Subtractor:
The subtraction of binary numbers can be done most conveniently by means of
complements. Remember that the subtraction, A B can be done by taking the 2’s complement of B
and added with A.

The addition and subtraction operations can be combined into one common circuit by
including an exclusive-OR gate with each full-adder. A 4-bit adder-subtractor circuit is shown in
Fig.4.7. The mode input M controls the operation. When M = 0 the circuit is an adder and when

one of the inputs of B. When M = 0, we have B ⊕ 0 = B. The full-adders receive the value of
M = 1 the circuit becomes a subtractor. Each exclusive-OR gate receives input M and

B, the input carry is 0, and the circuit performs A plus B. When M = 1, we have B ⊕ 1 = B’ and
C0=1. The B inputs are all complemented and a 1 is added through the input carry. The circuit
performs the operation A plus the 2’s complement of B.

Binary Incrementer:

Fig. 2.8: 4-bit binary incrementer

 The increment microoperation adds one to a number in a register. For example, if a 4-bit register has
a binary value 0110, it will go to 0111 after it is incremented. This microoperation is easily
implemented with a binary counter. Every time the count enable is active, the clock pulse transition
increments the content of the register by one.
The diagram of a 4-bit combinational circuit incrementer is shown in Fig.2.8. One of the
inputs to the least significant half-adder (HA) is connected to logic-1 and the other input
is connected to the least significant bit of the number to be incremented. The output carry from one
half-adder is connected to one of the inputs of the next-higher-order half-adder. The circuit
receives the four bits from A0 through A3, adds one to it, and generates the incremented output in
S0 through S3. The output carry C4 will be 1 only after incrementing binary 1111. This
also causes outputs S0 through S3 to go to 0.

Arithmetic Circuit
The arithmetic microoperations listed in Table 2.3 can be implemented in one composite
arithmetic circuit. The basic component of an arithmetic circuit is the parallel adder. By
controlling the data inputs to the adder, it is possible to obtain different types of
arithmetic operations.
The diagram of a 4-bit arithmetic circuit is shown in Fig.2.9. It has four full-adder circuits
that constitute the 4-bit adder and four multiplexers for choosing different operations. There are
two 4-bit inputs A and B and a 4-bit output D. The four inputs from A go directly to the X inputs
of the binary adder. Each of the four inputs from B is connected to the data inputs of
the multiplexers. The multiplexer’s data inputs also receive the complement of B. The other two
data inputs are connected to logic-0 and logic-1. The four multiplexers are controlled by two
selection inputs, S1 and S0. The input carry Cin goes to the carry input of the FA in the least
significant position. The other carries are connected from one stage to the next.
Table 2.4: Arithmetic Circuit Function

Selector Input Output Microoperation

S1 S0 Cin D=A+Y+Ci
0 0 0 B D=A+B ADD
0 0 1 B D=A+B+1 Add with carry
0 1 0 Subtract With Borrow
0 1 1 2’s Complement
Subtraction
1 0 0 0 D=A Transfer
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
 Figure 2.9: 4-Bit Arithmetic Circuit

The output of the binary adder is calculated from the following arithmetic sum

D = A + Y + Cin
When S1S0 = 00, the value of B is applied to the Y inputs of the adder.
If Cin = 0, the output D=A +B.
If Cin = 1, output D = A + B + 1.
Both cases perform the add microoperation with or without adding the input carry.
When S1S0 = 01, the complement of B is applied to the Y inputs of the adder.
When Cin = 0, then D = A-B-1. This is equivalent to subtract with borrow.
If Cin = 1, the complement of B, which is equivalent to a subtraction of A - B.
When S1S0 = 10 the inputs from B are neglected, and instead, all 0’s are inserted into the Y
inputs.
When Cin is = 0, The output becomes D = A + 0 + Cin. This gives D = A . Direct Transfer.
when Cin = 1 and D = A + 1. A is incremented by 1.
When S1S0 = 1 1 the all 1’s are inserted into the Y inputs of the adder. to produce the
When Cin = 0, decrement operation D = A – 1
when Cin = 1, and D=A Transfer (D=A-1+1)
 Logic Microoperations
Logic microoperations specify binary operations for strings of bits stored in registers.
These operations consider each bit of the register separately and treat them as binary variables.
For example, the OR microoperation with the contents of two registers R1 and R2 is
symbolized by the statement
P: R1 ← R1 V R2
It specifies a logic microoperation to be executed on the individual bits of the
registers provided that the control variable P = 1. As a numerical example, assume that each
register has four bits. Let the content of R1 be 1010 and the content of R2 be 1100. The OR
microoperation stated above symbolizes the following logic computation:
1010 Content of R1
1100 Content of R2
1110 Content of R1 after P = 1
List of Logic Microoperations
There are 16 different logic microoperations that can be performed with two binary
variables. They can be determined from all possible truth tables obtained with two binary
variables as shown in Table 2.5. In this table, each of the 16 columns F0 through F15 represents a
truth table of one possible Boolean function for the two variables x and y. Note that the functions
are determined from the 16 binary combinations that can be assigned to F.

The 16 Boolean functions of two variables x and y are expressed in algebraic form in the
first column of Table 2.6. The 16 logic microoperations are derived from these functions
by replacing variable x by the binary content of register A and variable y by the binary content of
register B.

Table 2.6. The 16 logic microoperations

 Hardware Implementation: Sixteen Logic Microoperations
The hardware implementation of logic microoperations requires that logic gates be inserted for
each bit or pair of bits in the registers to perform the required logic function. Although there are 16
logic microoperations, most computers use only four – AND, OR, XOR (exclusive-OR), and
complement–from which all others can be derived. Shows one stage of a circuit that generates the
four basic logic microoperations. It consists of four gates and a multiplexer. Each of the four logic
operations is generated through a gate that performs the required logic. The two selection inputs S1
and S0 choose one of the data inputs of the multiplexer and direct its value to the output. The
diagram shows one typical stage with subscript i. For a logic circuit with n bits, the diagram must
be repeated n times for I = 0, 1, 2,…,n-1. The selection variables are applied to all stages

One stage of logic circuit

Some Applications:
Logic microoperations are very useful for manipulating individual bits or a portion of
a word stored in a register. They can be used to change bit values, delete a group of bits, or insert
new bit values into a register.
The selective-set operation sets to 1 the bits in register A where there are corresponding 1’s
in register B. It does not affect bit positions that have 0’s in B. The following numerical example
clarifies this operation:
1010 A before
1100 B (logic operand)
1110 A after
The two leftmost bits of B’s are 1’s, so the corresponding bits of A are set to 1. One of these
two bits was already set and the other has been changed from 0 to 1. The two bits of A
with corresponding 0’s in B remain unchanged. From the truth table we note that the bits of A
after the operation are obtained from the logic-OR operation of bits in B and previous values of A.
Therefore, the OR microoperation can be used to selectively set bits of a register.

The selective-complement operation complements bits in A where there are corresponding

1’s in B. It does not affect bit positions that have 0’s in B.
For example:
1010 A before
1100 B (logic operand)
0110 A after
Again the two leftmost bits of B’s are 1’s, so the corresponding bits of A are
complemented. This example selective-complement operation is just an exclusive-OR
microoperation. Therefore, the exclusive-OR microoperation can be used to selectively
complement bits of a register.
 The selective-clear operation clears to 0 the bits in A only where there are corresponding
1’s in B. For example:
1010 A before
1100 B (logic operand)
0010 A after
Again the two leftmost bits of B’s are 1’s, so the corresponding bits of A are cleared to 0.
One can deduce that the Boolean operation performed on the individual bits is AB’. The
corresponding logic microoperation is

The mask operation is similar to the selective-clear operation except that the bits of A are
cleared only where there are corresponding 0’s in B. The mask operation is an AND
micro operation as seen from the following numerical example:
1010 A before
1100 B (logic operand)
1000 A after masking
The two rightmost bits of A are cleared because the corresponding bits of B are 0s. The
two leftmost bits are left unchanged because the corresponding bits of B are 1s. The mask
operation is more convenient to use than the selective-clear operation because most
computers provide an AND instruction, and few provide an instruction that executes the
microoperation for selective-clear.

The insert operation inserts a new value into a group of bits. This is done by first masking
the bits and then ORing them with the required value. For example, suppose that an A register
contains eight bits, 0110, 1010. To replace the four leftmost bits by the value 1001 we first mask
the four unwanted bits:
0110 1010 A before
0000 1111 B (mask)
0000 1010 A after masking

and then insert the new value:

0000 1010 A before
1001 0000 B (insert)
1001 1010 A after insertion
The mask operation is an AND microoperation and the insert operation is an OR
microoperation.
The clear operation compares the words in A and B and produces an all 0s result if the
two numbers are equal. This operation is achieved by an exclusive-OR microoperation as shown
by the following example:
1010 A
1010 B
0000 A exclusive-or A
When both A and B are equal, the two corresponding bits are either both 0 or 1. In either
case the exclusive-OR operation produces a 0. The all-0s result is then checked to determine if the
two numbers were equal.

Shift Microoperations
Shift microoperations are used for serial transfer of data. The contents of a register can be shifted
to the left or the right. At the same time that the bits are shifted, the first flip-flop receives its binary
information from the serial input. During a shift-left operation the serial input transfers a bit into the
rightmost position. During a shift-right operation the serial input transfers a bit into the leftmost
position. The information transferred through the serial input determines the type of shift.
There are three types of shifts: logical, circular, and arithmetic.
Logical Left Shift:

In this shift, one position moves each bit to the left one by one. The Empty least
significant bit (LSB) is filled with zero (i.e, the serial input), and the most significant bit
(MSB) is rejected. Every one bit left shift is Multiplication by 2.
Initial value 0010 = 2
Left shift will become 0100 and is equal to 4.
Logical Right Shift
In this shift, each bit moves to the right one by one and the least significant bit(LSB) is
rejected and the empty MSB is filled with zero.

Every time we shift a number towards the right by 1 bit it divides that
number by 2.
Initial value is 0100 = 4, Right shift will become 0010 = 2.

Circular Shift:
The circular shift (also known as a rotate operation) circulates the bits of the
register around the two ends without loss of information. This is accomplished by connecting the
serial output of the shift register to its serial input. We will use the symbols cil and cir for the
circular shift left and right, respectively.

Circular Left Shift:

In this micro shift operation each bit in the register is shifted to the left one by one.
After shifting, the LSB becomes empty, so the value of the MSB is filled in there.
Circular Right Shift:
In this micro shift operation each bit in the register is shifted to the right one by one. After
shifting, the MSB becomes empty, so the value of the LSB is filled in there.

Arithmetic Shift:
The arithmetic shift micro-operation moves the signed binary number either to the left or to the
right position.
Arithmetic Left Shift:
In this shift, each bit is moved to the left one by one. The empty least significant bit (LSB) is
filled with zero and the most significant bit (MSB) is rejected. Same as the Left Logical Shift.

Arithmetic Right Shift:

In this shift, each bit is moved to the right one by one and the least significant(LSB) bit is
rejected and the empty most significant bit(MSB) is filled with the value of the previous
MSB.
 .
Hardware Implementation:

Fig 2.12: 4-bit combinational circuit shifter

A possible choice for a shift unit would be a bidirectional shift register with parallel load.
Information can be transferred to the register in parallel and then shifted to the right or left. A
combinational circuit shifter can be constructed with multiplexers as shown in Fig.2.12. The 4-bit
shifter has four data inputs. A0 through A3, and four data outputs, H0 through H3. There are two
serial inputs, one for shift left (IL) and the other for shift right (IR). When the selection
input S=0, the input data are shifted right (down in the diagram). When S=1, the input data are
shifted left (up in the diagram). The function table in Fig.2.12 shows which input goes to each
output after the shift. A shifter with n data inputs and outputs requires n multiplexers. The two
serial inputs can be controlled by another multiplexer to provide the three possible types of
shifts.

Arithmetic Logic Shift Unit

 2.13 One stage of an arithmetic logic shift unit
shown in Fig.2.13

To perform a microoperation, the contents of specified registers are placed in the inputs of
the common ALU. The ALU performs an operation and the result of the operation is then
transferred to a destination register.
The ALU is a combinational circuit so that the entire register transfer operation from the
source registers through the ALU and into the destination register can be performed during one
clock pulse period. The shift microoperations are often performed in a separate unit, but
sometimes the shift unit is made part of the overall ALU.
The arithmetic, logic, and shift circuits introduced in previous sections can be combined
into one ALU with common selection variables. One stage of an arithmetic logic shift unit
is shown in Fig.2.13. The subscript I designates a typical stage. Inputs Ai and Bi are applied to
both the arithmetic and logic units. A particular microoperation is selected with inputs S1 and S0.
A 4x 1 multiplexer at the output chooses between an arithmetic output in Ei and a logic output in
Hi. The data in the multiplexer are selected with inputs S3 and S2. The other two data inputs to the
multiplexer receive inputs Ai-1 for the shift-right operation and Ai+1 for the shift-left operation.

The circuit of Fig.2.13 must be repeated n times for an n-bit ALU. The output carry Ci+1 of a
given arithmetic stage must be connected to the input carry Ci of the next stage in sequence. The
input carry to the first stage is the input carry Cin, which provides a selection variable for the
arithmetic operations.
The circuit whose one stage is specified in Fig.2.13 provides eight arithmetic operation,
four logic operations, and two shift operations. Each operation is selected with the five variables
S3, S2, S1, S0, and Cin. The input carry Cin is used for selecting an arithmetic operation only.
Table 4.8 lists the 14 operations of the ALU. The first eight are arithmetic operations and
are selected with S3S2=00. The next four are logic operations and are selected with S3S2=01. The
input carry has no effect during the logic operations and is marked with don’t-care x’s. The last
two operations are shift operations and are selected with S3S2=10 and 11.

Instruction Codes
Every different processor type has its own design (different registers, buses, microoperations,
machine instructions, etc).

Modern processor is a very complex device It contains Many registers, Multiple

arithmetic units, for both integer and floating point calculations, The ability to pipeline several
consecutive instructions to speed execution, etc…
The Basic Computer has two components, a processor and memory. The memory has 4096
12
words in it, 4096 = 2 , so it takes 12 bits to select a word in memory. Each word is 16 bits long.
Program is A sequence of (machine) instructions. An Instruction is A group of bits that tell the
computer to perform a specific operation.
The instructions of a program, along with any needed data are stored in memory. The CPU reads
the next instruction from memory. It is placed in an Instruction Register (IR).

Instruction Formats & Addressing modes:

An instruction is divided into two parts: An opcode (Operation Code) and Address. An
opcode specifies the operation. An address specifies the registers and/or locations in
memory to use for that operation.
12
In the Basic Computer, memory contains 4096 (= 2 ) words, we needs 12 bit to specify
memory address. In the Basic Computer, bit 15 of the instruction specifies the addressing
mode (0: direct addressing, 1: indirect addressing). Since the memory words, and hence the
instructions, are 16 bits long.
Effective Address ▪ The operand address in computation-type instruction or the target address in a
branchtype instruction
Direct address - the address part of instruction specifies the address of operand(data) in
memory. In the above fig, when 15th bit is 0, address part contains 457. Effective Address(EA) =
457. So, operand is at 457.
Indirect address- the address part of instruction specifies the address of address operand in
memory. When 15th bit is 1, address part contains 300. EA=1350. so operand is at 1350.

Computer Registers
 Since memory is 4K in size, it requires 12 address bits. Each word of memory contains
16 bits of data. The address register (AR) is 12 bits wide.
 program counter (PC), It contains the address of next instruction to be fetched from the
memory. So, it is also 12 bits wide.
 Each data word is 16 bits wide. The Data Register (DR) must also be 16 bits wide, since
it receives data from and sends data to memory.
 The accumulator (AC) acts on 16 bits of data. So, it is also 16 bits wide.
 The Instruction Register (IR) receives instruction codes from memory which are 16 bits
wide.
 TR is a temporary register. Only the CPU can cause it to be accessed. The programmer
cannot directly manipulate the contents of TR. It is also 16 bit register.
 The input and output registers (INPR and OUTR) are 8 bits wide each. For this CPU,
I/O instructions only transfer 8 bits of data at a time.
 The 3-bit sequence counter (SC) is used to generate the correct timing (T) states.
Other 1-bit registers are the carry out (E), the indirect register (I), the interrupt enable
(IEN) and the input and output flags (FGI and FGO).
 Label Bits Register Name Description
--------------------------------------------------------------------------------------------------------
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

Common Bus
The registers in the Basic Computer are connected using a bus. This gives a savings in circuitry over
complete connections between registers. It can be showed as below

The CPU is designed around an internal common bus with a common clock. Each register can place its data
onto the bus, and has internal tri-state buffers on the outputs. The control unit must make sure that at most
one register (or memory unit) places data onto the bus at one time. The memory unit is external to the CPU.
It always receives its address from the address register (AR) and makes its data available to the CPU bus. It
receives data from the CPU bus as well. Read and write signals are supplied by the control unit. The address
registers, program counter (PC) and data register (DR) each load data onto and receive data from the system
bus. Each has a load, increment and clear signal derived from the control unit. These signals are
synchronous; each register combines these signals with the system clock to activate the proper function.
Since AR and PC are only 12- bits each, they use the low order 12 bits of the bus. The accumulator makes its
data available on the bus but does not receive data from the bus. Instead, it receives data solely from an
ALU, labeled “Adder and Logic” in the diagram. To load data into AC, place it onto the bus via DR and pass it
directly through the ALU. The synchronous load, increment and clear signals act as in the previous registers.
Note that E, the 1-bit carry flag, also receives its data from the ALU. The input register, INPR, receives data
from an external input port, not shown here, and makes its data available only to AC. The output register
makes its data available to the output port via hardware not shown here. We will examine these two
components in more detail later in this module. The instruction register, IR, can only be loaded; it cannot be
incremented nor cleared. Its output is used to generate Di and Ti . We will look at that hardware later in this
module. TR is a temporary register. The CPU uses this register to store intermediate results of operations. It
is not accessible by the external programs. It is loaded, incremented and cleared like the other registers.
 Computer Instructions formats
Computer Instructions are classified into three types, based on the Mode bit and Op-code field. Those are;
1)Memory Reference: As their name implies, memory reference instructions are those that reference
memory. Some read data from memory, others write data to memory, and one instruction does both. For
these instructions, the most significant bit is the indirect bit. If this bit is 1, the instruction must use indirect
memory addressing. That is, the address given is not the address of the operand. It is the address of a
memory location which contains the address of the operand. The next three bits are the OPR field, or
operation field. These three bits may take on any value except for 111; that is reserved for other
instructions. The OPR field tells the CPU which instruction is to be performed.

Finally, the 12 low order bits contain the memory address to be used by this instruction (or in the case of
indirection the address of a memory location which contains the address to be used by this instruction).

2)Register Reference: Register reference instructions are those which access data and
manipulate the contents of registers. They do not access memory. These instructions are
executed in one clock cycle.
Note that the 12 low-order bits serve a different function depending on the
instruction format used.
3)I/O Instructions: This class of instructions accesses I/O devices. The instructions in this class also enable
and disable interrupts. Since this computer only allows for a single input device and a single output device,
no address information is needed

Timing and control signals

The instruction register is shown again in Fig. 5.6, where it is divided
into three parts:

1. the 1 bit,
2. the operation code, and
3. bits 0 through 11.

 The operation code in bits 12 through 14 are decoded with a 3 x 8

decoder. The eight outputs of the decoder are designated by the
symbols D0 through D7.
 Bit 15 of the instruction is transferred to a flip-flop designated by
the symbol I.
 Bits 0 through 11 are applied to the control logic gates.
 The 4-bit sequence counter can count in binary from 0 through 15.
The outputs of the counter are decoded into 16 timing signals
T0 through T15.
 The sequence counter SC can be incremented or cleared
synchronously.
 Once in a while, the counter is cleared to 0, causing the next
active timing signal to be T0.
As an example, consider the case where SC is incremented to provide
timing signals T0, T1, T2, T3, and T4 in sequence. At time T4, SC is
cleared to 0 if decoder output D3 is active. This is expressed
symbolically by the statement
D3T4: SC <__ 0
 The sequence counter SC responds to the positive transition of the
clock. Initially, the CLR input of SC is active. The first positive
transition of the clock clears SC to 0, which in tum activates the
timing signal T0 out of the decoder. T0 is active during one clock
cycle. The positive clock transition labeled T0 in the dagram will
trigger only those registers whose control inputs are transition, to
timing signal T0.
 SC is incremented with every positive clock transition unless its
CLR input is active. This produces the sequence of timing signals
T0, T1, T2, T3 ,T4 and so on, as shown in the diagram. If SC is not
cleared, the timing signals will continue with T5, T6 up to T15 and
back to T0
 The last three waveforms in Fig. 5-7 show how SC is cleared when
D3T4 = 1. Output D3 from the operation decoder becomes active at
the end of timing signal T2. When timing signal T4 becomes active,
the output of the AND gate that implements the control function
D3T4 becomes active. This signal is applied to the CLR input of SC.
On the next positive clock transition (the one marked T 4 in the
diagram) the counter is cleared to 0. This causes the timing signal
 T0 to become active instead of T5 that would have been active if
SC were incremented instead of cleared.

For example, the register transfer statement

T0: AR <__ PC
specifies a transfer of the content of PC into AR if timing signal T 0 is
active. T0 is active during an entire clock cycle intervaL During this time
the content of PC is placed onto the bus (with S 2S1S0 = 010) and the LD
(load) input of AR is enabled. This same positive clock transition
increments the sequence counter SC from 0000 to 0001 . The next
clock cycle has T1 active and T0 inactive.
Instruction Cycle
In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
After an instruction is executed, the cycle starts again at step 1, for the next instruction.
Note: Every different processor has its own (different) instruction cycle.

Initially, the program counter PC is loaded with the address of the first
instruction in the program. The sequence counter SC is cleared to 0,
providing a decoded timing signal To. After each clock pulse, SC is
incremented by one, so that the timing signals go through a sequence
T0, T1, T2, and so on. The rnicrooperations for the fetch and decode
phases can be specified by the following register transfer statements.
T0: AR <- PC
T,: IR <-M[AR], PC <- PC + 1
T2: D0, ••• , D7 <-Decode IR(12-14), AR <---IR(0-11), 1 <---IR(lS)
Since only AR is connected to the address inputs of memory, it is
necessary to transfer the address from PC to AR during the clock
transition associated with timing signal T0• The instruction read from
memory is then placed in the instruction register IR with the clock
transition associated with timing
signal T1• At the same time, PC is incremented by one to prepare it for
the address of the next instruction in the program. At time T2, the
operation code in IR is decoded, the indirect bit is transferred to flip-flop
I, and the address part of the instruction is transferred to AR . Note that
SC is incremented after each clock pulse to produce the sequence To,
T1, and T2•
Figure 5-8 shows how the first two register transfer statements are
implemented in the bus system. To provide the data path for the transfer
of PC to AR we must apply timing signal T0 to achieve the following
connection:
1. Place the content of PC onto the bus by making the bus selection
inputs 525150 equal to 010. 2. Transfer the content of the bus to AR by
enabling the LD input of AR .
The next clock transition initiates the transfer from PC to AR since T0 =
1. In a-d'CY" ,tJ' .it is necessary to use timing signal T1 to provide the
following connections in the bus system.
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making 525150 = Ill.
3. Transfer the content of the bus to IR by enabling the LD input of _ JR.
4. Increment PC by enabling the INR input of PC.
The next clock transition initiates the read and increment operations
since T, = 1.
Figure 5-8 duplicates a portion of the bus system and shows how T0
and T, are connected to the control inputs of the registers, the memory,
and the bus selection inputs. Multiple input OR gates are included in the
diagram because there are other control functions that will initiate similar
operations.

Determine the Instruction:

If we show the clock pulses for finding the Effective Address (EA), then it can be as

Memory Reference Instruction

The AND instruction performs a bit-wise logical AND.

The ADD instruction performs a regular addition.
The LDA and STA are regular load and store instructions.
The BUN (branch unconditional) is a jump instruction.
The BSA is used to call subroutines in the Basic Computer.
The ISZ instruction is used for program loops. Note the semicolon in this instruction. It
means that the first part is performed, then the second part is performed in the following
clock cycle.
Later in this module, we will examine exactly how each of these instructions
is implemented on the Basic Computer.

LDA: Load to AC
DT: DR M[AR]
2 4

DT: AC DR, SC 0
2 5

STA: Store AC
DT: M[AR] AC, SC 0
3 4

BUN: Branch Unconditionally

DT: PC AR, SC 0

BSA: Branch and Save Return Address

M[AR] PC, PC AR + 1
 Register Reference Instruction:
Each register reference instruction is performed in a single clock cycle. Each instruction
manipulates the contents of a register within the CPU, so the relatively time consuming accesses
to memory are avoided. There are 12 register reference instructions overall, each of which
is encoded by one of the 12 low order bits of the instruction code.

I/O Instruction and Interrupt:

The input/output instructions, like the register reference instructions, are performed in a
single clock cycle. Note that there are no instructions to set FGI or FGO to 1. These flags are set by
external hardware when input data is ready or output data is requested. When the CPU
performs the proper input or output instruction (INP or OUT), it resets the flag to allow for future
I/O data transfers.

Possible I/O Instructions are specified below:

open communication only when some data has to be passed. When it getting an
interrupt,
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to
the service routine to process the data transfer, and then returns to the task it was performing.
The T signals occur in sequence and are never skipped over. The only two options during a
T-state are to proceed to the next T-state or to return to T state
0.
The D signals decode the instruction and are used to select the correct execute routine.
I is used to select the indirect routine and also to select the correct execute routine for
non- memory reference instructions.
R is used for interrupt processing flip-flop.

- The interrupt cycle is a HW implementation of a branch and save return address operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory is in
address 1.
- At memory address 1, the programmer must store a branch instruction that sends the control to
an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0".
 The fetch and decode phases of the instruction cycle must be modified Replace T 0, T1,
T2 with R'T0, R'T1, R'T2
The interrupt cycle:
RT0: AR 0, TR PC RT1:
M[AR] TR, PC 0
RT2: PC PC + 1, IEN 0, R 0, SC 0.