SANSKRITHI SCHOOL OF ENGINEERING

SAIDABAD, HYDERABAD – 500 059

DEPARTMENT OF ELECTRONICS &COMMUNICATION ENGINEERING

Dept: ECE Academic year:2018-19

COURSE FILE

FACULTY Name : A S KEERTHI NAYANI Dept ECE

SUBJECT NAME : LINEAR INTEGRATED CIRCUITS Code PC501EC
AND APPLICATIONS
YEAR : 2018-19 Semester V SEM
DEGREE & BRANCH : BE ECE Academic Year 2018-19
L=3;T=1;Sessional=30;External=70 Credits=3
CONTENTS:

1. Cover page
2. Syllabus copy
3. Vision of the Department
4. Mission of the Department
5. PEOs ,POs & PSOs
6. Course Objectives and outcomes
7. Brief notes on the importance of the course and how it fits into the curriculam
8. Prerequisites, if any
9. Instructional learning outcomes
10. Course mapping with POS
11. Class time table
12. Individual Timetable
13. Lecture schedule with methodology being used /adopted
14. Detailed notes(printed version only)
15. Additional topics (practical oriented)
16. University Question papers of previous years
17. Question Bank
18. Assignment Questions
19. Tutorial problems
20. Discussion topics, if any
21. References,journals,websites and e-links , if any
22. Quality Measurement sheets
23. Student list
a.Course end survey
b. Teaching evaluation
24. Group Wise students list for discussion topics
25. Any other relevant material like web resources etc.
 COURSE FILE
ACADEMIC YEAR 2018-2019

V Semester(CBCS)

PC501 EC–LINEAR INTEGRATED CIRCUITS AND

APPLICATIONS

By

A S KEERTHI NAYANI
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SANSKRITHI SCHOOL OF ENGINEERING
(Sponsored by Matrusri Education Society, Estd.1980)

(Approved by AICTE & Affiliated to Osmania University)

#16-1-486, Saidabad, Hyderabad – 500 059, Ph: 040-24072764

Email: matrusri.principal@gmail.com, www.matrusri.edu.in

Faculty of Engineering O.U. With effect from Academic Year 2018 – 19

 Course Course Title Core /
Code Elective

PC501EC LINEAR ICs AND APPLICATIONS Core

Prerequisite Contact Hours per Credits

Week CIE SEE

AEC L T D P

3 1 - - 30 70 3

Unit I
Differential Amplifiers: Classification, DC and AC analysis of single / dual input
Balanced and unbalanced output Configurations of Differential amplifiers using BJTs,
Level Translator.
Operational Amplifier: Ideal, Practical, General (741) bipolar Operational Amplifier,
AC and DC performance characteristics, Frequency Compensation, Open-loop and
close-loop configurations, 741 Manufacturers data sheet- description, specifications
and packages.
Unit II
Operational Amplifier Applications-I: Adder, subtractor, Ideal and practical integrator
& differentiator, Voltage to current converter , current to voltage converter,
differential amplifier, instrumentation amplifier, Log and antilog amplifiers.
Unit III
Operational Amplifier Applications -II: Comparator, Precision rectifier, Peak
detector, Clippers, Clampers, Sample-and-Hold circuits.
Active Filters Introduction – First order, Second order Active filters – LP, HP, BP,
BR and All pass.
Unit IV
Waveform Generators: Square wave, Monostable Multivibrator, Schmitt Trigger, saw
tooth & Triangular wave generators. Voltage Controlled Oscillator, PLL, NE 555 and
its applications. Function Generator –8038.
Unit V
Voltage Regulators: Basic of voltage Regulators, Linear regulators using opamp, IC
Regulators 78XX and 723.
Data Converters: Introduction, Digital to Analog Converters : Weighted Resistor
DAC & Inverted R-2R Ladder DAC. Analog to digital Converters: Parallel
Comparator ADC, Successive Approximation ADC and Dual Slope ADC. DAC and
ADC specifications.

Suggested Readings:
1. David A Bell, “Operational Amplifiers and Linear ICs,” 3/e, Oxford Publications, 2011.
2. Ramakant A. Gayakwad, “Op-Amps and Linear Integrated Circuits,” 4/e, PHI, 2010.
3. D.Roy Chowdhury, Shail B.Jain, “Linear Integrated Circuits”, 4/e, New / Age International
(P) Ltd., 2008.

VISION OF THE DEPARTMENT

To become a reputed centre of learning in Electronics and Communicationand transform the

students into accomplished professionals.
MISSION OF THE DEPARTMENT

M1 To provide the learning ambience to nurture the young minds with theoretical and
practical knowledge to produce employable and competent engineers.
M2 To provide a strong foundation in fundamentals of electronics and communication
engineering to make students explore advances in research for higher learning.
M3 To inculcate awareness for societal needs, continuous learning and professional
practices.
M4 To imbibe team spirit and leadership qualities among students

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

After graduation, the students will have the ability to:

PEO1 Acquire, comprehend, and apply, basic Sciences & Engineering knowledge to
analyze, evaluate, design and implement solutions in Electronics and
communication Engineering.
PEO2 Engage in higher learning, for contributing to technological innovations, and adapt
to changes in technology by continuous Learning.
PEO3 Work with respect for societal values and concern for environment in implementing
engineering solutions.
PEO4 Perform with professional ethics as an individual or as a team player to realize the
goals of the organization/society.

PROGRAM OUTCOMES
PO1 Engineering Apply the knowledge of mathematics, science, engineering fundamentals, and an
knowledge: engineering specialization to the solution of complex engineering problems.

PO2 Problem Identify, formulate, review research literature, and analyze complex engineering
Analysis: problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.

PO3 Design/ Design solutions for complex engineering problems and design system
Development of components or processes that meet the specified needs with appropriate
solutions: consideration for the public health and safety, and the cultural, societal, and
environmental considerations.

PO4 Conduct Use research-based knowledge and research methods including design of
Investigations of experiments, analysis and interpretation of data, and synthesis of the information
complex to provide valid conclusions.
problems:
PO5 Modern tool Create, select, and apply appropriate techniques, resources, and modern
usage: engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.

PO6 The engineer Apply reasoning informed by the contextual knowledge to assess societal,
and Society: health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.

PO7 Environment Understand the impact of the professional engineering solutions in societal and
 and environmental contexts, and demonstrate the knowledge of, and need for
sustainability : sustainable development.

PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

PO9 Individual and Function effectively as an individual, and as a member or leader in diverse
team work: teams, and in multidisciplinary settings.

PO10 Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations,
and give and receive clear instructions.

PO11 Project Demonstrate knowledge and understanding of the engineering and management
management and principles and apply these to one’s own work, as a member and leader in a team,
finance: to manage projects and in multidisciplinary environments.

PO12 Life-Long Recognize the need for, and have the preparation and ability to engage in
learning: independent and life-long learning in the broadest context of technological
change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

ECE graduates will be able to:

Carry out Electronic system design and contribute towards Electronic

PSO1 Hardware/Software design solutions required for Industries.

Analyze societal requirements for providing/taking up higher studies and research in

PSO2 allied areas.

Use acquired technical soft skills to qualify for working in Public, Private and IT
PSO3 sector.

COURSE OBJECTIVES

Course Explanation
Objective
1 Describe various configurations of Op-amp.

2 Describe the basic principles and practical limitations of Op-amp.

3 Describe the various linear and non linear applications of Op-amp.

4 Describe frequency generators , active filters and voltage regulators.

5 Discuss the operation of the most commonly used D/A and A/D converters

COURSE OUTCOMES
Upon the completion of the course the students will be able to

Course Explanation
Outcome
CO1 Understand basic concepts of differential amplifiers and its electrical
characteristics of Op-Amp.
CO2 Design and analyze various linear applications of op-amp.
CO3 Apply concepts of op-amp to design and analyse various non-linear
applications, multivibrators and active filters.
CO4 Model applications of 555timer ,waveform generators,VCO and PLL.
CO5 Analyze and design various IC regulators can also able to choose
appropriate A/D and D/A converters for signal processing applications.
BRIEF NOTES ON THE IMPORTANCE OF THE COURSE AND HOW IT FITS IN
TO THE CURRICULAM

This course is essential for all future ECE engineers to thoroughly learn about the
fundamentals of various integrated circuits and their applications. This course is designed to
impart a basic knowledge in the subject to the undergraduate students.Linear ICs and
applications subject teaches about the basic knowledge about operational amplifiers required
to design an amplifier circuit, oscillators etc..It provides a clear and easily understandable
discussion of designing of different types Linear ICs and their parameters.

PREREQUISITES

C.CODE COURSE NAME DESCRIPTION SEM

PC EC Electronics Devices and Circuits Different Types of diodes and Transistor III Sem
Characteristics, Regulators

PC EC ANALOG ELECTRONIC CIRCUITS Types of feedback and their applications IV sem

PC EC PULSE AND DIGITAL CIRCUITS Types of multi vibrators IV sem

INSTRUCTIONAL LEARNING OUTCOMES

1. Understand and analyse different types of differential amplifiers and significance
of level translator.
2. Understand electrical characteristics of Op-Amp.
3. Design and analyze various applications of op-amp(Adder, subtractor,
integrator ,differentiator, log-antilog amplifiers.
4. Apply concepts of op-amp to design and analyse various non-linear applications,
multivibrators and active filters.
5. Generate waveforms for required frequency.
6. Model applications of 555timer ,
7. Understand VCO and applications of PLL.
8. Analyze and design various fixed and variable IC regulators.
9. Understand and learn A/D and D/A converters for signal processing applications.

COURSE MAPPING WITH POs

 PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO PSO
1 2 3 4 5 6 7 8 9 0 1 2 1 2 3
EC 301 3 3 1 2 - 2 1 - - - - 1 3 2 1

CO MAPPING WITH POS AND PSOs

CO’s PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO
3
EC 301.1 3 2 1 - - 1 - - - - - - 3 - 1

EC 301.2 2 3 1 - - 1 - - - - - - 3 1 1

EC 301.3 3 3 2 2 - 2 - - - - - - 3 2 1

EC 301.4 2 2 1 2 - - 1 - - - - - 2 1 2

EC 301.5 3 3 2 1 - 2 1 - - - - 1 3 2 2

EC 301.Avg 2.6 2.6 1.4 1.6 - 1.5 1 - - - - 1 3 1.5 1.4

CLASS TIME TABLE

V SEM A- SEC

TIME
10:40 am 11:40 am 1:40 pm
9.40am to 12:40 pm 02:10pm
to 11:40 to 12:40 to 3:10 pm to 4:10 pm
10.40am to 1:40pm to 03:10
am pm 02:10PM
DAY

MON AC DSP COA DSD SSP LAB/ICA LAB

L
TUE ACS LICA DSD DSP COA LIBRARY/SPORTS
U
WED COA LICA SSP LAB/ICA LAB ACS DSD
N
THU ACS AC CRT DSD LICA
C
FRI AC DSP SSP LAB/ICA LAB COA ACS
H
SAT LICA AC DSP
 V SEM B- SEC

TIME
10:40 am 11:40 am 12:40 1:40 pm
9.40am to 02:10pm to 3:10 pm to 4:10
to 11:40 to 12:40 pm to to
10.40am 03:10 pm
am pm 1:40pm 02:10PM
DAY

MON COA LICA DSD ACS AC LIBRARY/SPORTS

L
TUE AC ACS DSP LICA SSP LAB/ICA LAB
U
WED LICA ACS COA AC SSP LAB/ICA LAB
N
THU DSD COA CRT LICA DSP
C
FRI DSP DSD ACS COA SSP LAB/ICA LAB
H
SAT AC DSP DSD

INDIVIDUAL TIME TABLE

1 2 3 4 5 6
MON LICA-B  IC LAB-A
TUE LICA-A LICA-B L  IC LAB-B
WED LICA-B LICA-A  IC LAB-A U  IC LAB-B
THU N LICA-B LICA-A
FRI  IC LAB-A C  IC LAB-B
SAT LICA-A H
LECTURE SCHEDULE WITH METHODOLOGY BEING USED

UNIT I

S. PEDAGOG
No. CLASSES
No Y
REQUIRED
: DIFFERENTIAL AMPLIFIERS & OPERATIONAL AMPLIFIER

1 Background of Electronics and Op amps 1

UNIT-1:
2 Operational Amplifiers: Manufacturers data sheet- 1
description, Specifications and Package

3 Block diagram of operational amplifier 1

Ideal, Practical, General (741)bipolar Operational

4 1
Amplifier

5 Common mode ,differential mode of differential amplifier 1

Differential Amplifiers Classification, DC analysis Of a

6 1
Differential Amplifier
CHALK
AC analysis of Dual input Balanced Output Differential AND TALK
7 1
Amplifier using BJT’s

AC analysis of single Dual input Unbalanced Output

8 1
Differential Amplifier using BJT’s

9 Constant Current Biasing Circuits 1

10 Cascaded Differential Amplifier, Level Translator 1

AC,DC performance charecteristics and Frequency

11 1
compensation

12 Open loop and closed loop ap-amp configurations 1

No. CLASSES REQUIRED: 12

UNIT II

S. No. CLASSES
No OP-AMP APPLICATIONS-I REQUIRED

Inverting and Non-inverting Amplifiers with ideal and CHALK

1 1
non-ideal Op-amps AND TALK
2 Difference Amplifier(subtractor), Summing 1
Amplifier(adder)
 Ideal and Practical Integrator, Ideal and Practical
3 2
Differentiator

4 V to I and I to V converters 1

5 Instrumentation Amplifier 1

6 Log and Antilog amplifiers 1

7 Problems 1

No. CLASSES REQUIRED: 8

UNIT III

No .CL
S. ASSES
No REQUI
OP-AMP APPLICATIONS-II RED

1 Comparator,presicion rectifier,peak detector 1

2 Clippers,clampers, Sample and Hold Circuit 2

CHALK
Introduction to Active Filters , Design of 1 st & 2nd order Low Pass AND TALK
3 2
Butterworth Filters

4 Design of 1st & 2nd order High Pass Butterworth Filters 2

7 Wide and Narrow Band-pass, Band-reject and All-pass filters 2

8 All pass filters, Problems 1

No .CLASSES REQUIRED: 10

UNIT IV

No .CL
S. ASSES
No REQUI
WAVE FORM GENERATORS RED

1 Square wave 1

2 monostable multivibrator, 1 CHALK

AND TALK
3 schimitt trigger, 1

4 sawtooth and triangular wave generators 1

5 Introduction to 555 timer and its functional diagram 1

6 The 555 timer as Monostable Multivibrator and its applications 1

The 555 timer as Astable Multivibrator and Schmitt Trigger and

7 2
applications

8 Analysis and Design of Function Generators using IC 8038 2

PLL: Introduction, Principles, Block Schematic and Description of

9 1
IC 565

Applications of PLL: Frequency multiplication and frequency

10 1
synthesis.

11 VCO: Operation and Applications using IC 566 1

No. CLASSES REQUIRED:13

UNIT V

No.
CLASSE
S.
S
No
REQUI
IC REGULATORS & DATA CONVERTERS RED

Introduction, Analysis and design of regulators using 78XX and 723

1 2
monolithic ICs

2 Current limiting and Current fold back techniques using IC 723 1

Data Converters: Introduction, basic Digital to Analog Converter CHALK

3 1
techniques AND TALK
4 Weighted Resistor DAC, Inverted R-2R Ladder DAC 1 &
PPTS
A to D Converter Types, Parallel Comparator ADC, Successive
5 1
Approximation ADC

6 Dual Slope ADC, DAC and ADC specifications. 1

No. CLASSES REQUIRED: 07

TOTAL CLASSES REQUIRED: 50

 UNIT -I

DIFFERENTIAL AMPLIFIERS
AND
OPERATIONAL AMPLIFIERS
OPERATIONAL AMPLIFIER (OP-AMP):

An operational amplifier is a direct-coupled high-gain amplifier usually consisting of

one or more differential amplifiers and usually followed by a level translator and an output
stage. An operational amplifier is available as a single integrated circuit package.

The operational amplifier is a versatile device that can be used to amplify dc as well as
ac input signals and was originally designed for computing such mathematical functions as
addition, subtraction, multiplication, and integration. Thus the name operational amplifier
stems from its original use for these mathematical operations and is abbreviated to op-amp.
With the addition of suitable external feedback components, the modern day op-amp can be
used for a variety of applications, such as ac and dc signal amplification, active filters,
oscillators, comparators, regulators, and others.

Ideal op-amp:

An ideal op-amp would exhibit the following electrical characteristics:

1. Infinite voltage gain

2. Infinite input resistance so that almost any signal source can drive it and there is no
loading on the preceding stage.

3. Zero output resistance Ro so that output can drive an infinite number of other devices.

4. Zero output voltage when input voltage is zero.

5. Infinite bandwidth so that any frequency signal from 0 to ∞Hz can be amplified without

attenuation.

6. Infinite common mode rejection ratio so that the output common-mode noise
voltage is zero.

7. Infinite slew rate so that output voltage changes occur simultaneously with input
voltage changes.

Equivalent circuit of an op-amp:

 Fig. 1.1 shows an equivalent circuit of an op-amp. V1 and V2are the two input voltage
voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin’s voltage
source and RO is the Thevenin’s equivalent impedance looking back into the terminal.

This equivalent circuit is useful in analysing the basic operating principles of op-amp
and in observing the effects of standard feedback arrangements.

VO = Ad (V1-V2) = AdVd.

Fig. 1.1 Equivalent circuit of OP-AMP

This equation indicates that the output voltage Vo is directly proportional to the
algebraic difference between the two input voltages. In other words the opamp amplifies the
difference between the two input voltages. It does not amplify the input voltages themselves.
The polarity of the output voltage depends on the polarity of the difference voltage Vd.

Ideal Voltage Transfer Curve:

Fig. 1.2 Ideal voltage transfer curve

 The graphic representation of the output equation is shown infig.1.2 in which the
output voltage Vo is plotted against differential input voltage Vd, keeping gain Ad constant.
The output voltage cannot exceed the positive and negative saturation voltages. These
saturation voltages are specified for given values of supply voltages. This means that the
output voltage is directly proportional to the input difference voltage only until it reaches the
saturation voltages and thereafter the output voltage remains constant. Thus curve is called an
ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. If
thecurve is drawn to scale, the curve would be almost vertical because of very large values of
Ad.

INTERNAL CIRCUIT :

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over
1MHz to which feedback is added to control its overall response characteristic i.e. gain and
bandwidth. The op-amp exhibits the gain down to zero frequency.

The internal block diagram of an op-amp is shown in the fig 1.3. The input stage is the
dual input balanced output differential amplifier. This stage generally provides most of the
voltage gain of the amplifier and also establishes the input resistance of the op-amp. The
intermediate stage is usually another differential amplifier, which is driven by the output of the
first stage. On most amplifiers, the intermediate stage is dual input, unbalanced output.
Because of direct coupling, the dc voltage at the output of the intermediate stage is well above
ground potential. Therefore, the level translator (shifting) circuit is used after the intermediate
stage downwards to zero volts with respect to ground. The final stage is usually a push pull
complementary symmetry amplifier output stage. The output stage increases the voltage swing
and raises the ground supplying capabilities of the op-amp. A well designed output stage also
provides low output resistance.

Fig.1.3 Block Diagram of OP-AMP

Differential amplifier:

Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is
to amplify the difference between two input signals. The two transistors Q1 and Q2 have identical
characteristics. The resistances of the circuits are equal, i.e. RE1 = R E2, RC1 = R C2 and the magnitude
of +VCC is equal to the magnitude of -VEE. These voltages are measured with respect to ground.

Fig. 1.4 Differential Amplifier

To make a differential amplifier, the two circuits are connected as shown in fig. 1.4.
The two +VCC and -VEE supply terminals are made common because they are same. The two
emitters are also connected and the parallel combination of RE1 and RE2 is replaced by a
resistance RE. The two input signals v1& v2 are applied at the base of Q1 and at the base of
Q2. The output voltage is taken between two collectors. The collector resistances are equal and
therefore denoted by RC = RC1 = RC2.

Ideally, the output voltage is zero when the two inputs are equal. When v1 is greater
then v2 the output voltage with the polarity shown appears. When v1 is less than v2, the output
voltage has the opposite polarity.

The differential amplifiers are of different configurations.

Fig1.5. Dual input, balanced output differential amplifier.Fig.1.6. Dual input, unbalanced

Fig.1.7.Single input, balanced output differential amplifierFig.1.8.Single input, unbalanced

output differential amplifier.

The four differential amplifier configurations are following:

1. Dual input, balanced output differential amplifier.

2. Dual input, unbalanced output differential amplifier.

3. Single input balanced output differential amplifier.

4. Single input unbalanced output differential amplifier.

These configurations are shown in fig(1.5,1.6,1.7, 1.8), and are defined by number of
input signals used and the way an output voltage is measured. If use two input signals, the
configuration is said to be dual input, otherwise it is a single input configuration. On the other
hand, if the output voltage is measured between two collectors, it is referred to as a balanced
output because both the collectors are at the same dc potential w.r.t. ground. If the output is
measured at one of the collectors w.r.t. ground, the configuration is called an unbalanced
output.

A multistage amplifier with a desired gain can be obtained using direct connection
between successive stages of differential amplifiers. The advantage of direct coupling is that
it removes the lower cut off frequency imposed by the coupling capacitors, and they are
therefore, capable of amplifying dc as well as ac input signals.

1) Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig.1.10V1 and V2 are the two inputs, applied to the bases of
Q1 and Q2 transistors. The output voltage is measured between the two collectors C1 and C2,
which are at same dc potentials.

D.C. Analysis:

To obtain the operating point (ICQ and VCEQ) for differential amplifier dc
equivalent circuit is drawn by reducing the input voltages V1 and V2 to zero as shown in
fig1.9.
Fig.1.9Differential Amplifier

The internal resistances of the input signals are denoted by RS because RS1= RS2.
Since both emitter biased sections of the different amplifier are symmetrical in all respects,
therefore, the operating point for only one section need to be determined. The same values of
ICQ and VCEQ can be used for second transistor Q2. Applying KVL to the base emitter loop
of the transistor Q1.

The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of
VEE. The emitter current in Q1 and Q2 are independent of collector resistance RC. The
voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is
negligible. Knowing the value of IC the voltage at the collector VCis given by

VC =VCC- IC RC and VCE = VC- VE

= VCC - IC RC + VBE VCE = VCC + VBE -

ICRC
 From the two equations VCEQ and ICQ can be determined. This dc analysis is
applicable for all types of differential amplifier.

A.C. Analysis :

The circuit is shown in fig.1.10 V1 and V2 are the two inputs, applied to the bases of
Q1 and Q2 transistors. The output voltage is measured between the two collectors C1 and C2,
which are at same dc potentials.

Dc analysis has been done to obtain the operating point of the two transistors. To find
the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac equivalent
circuit is drawn using r-parameters as shown infig1.11. The dc voltages are reduced to zero
and the ac equivalent of CE configuration is used.

ince the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal
and designated by r'e . This voltage across each collector resistance is shown 180° out of
phase with respect to the input voltages v1 and v2. This is same as in CE configuration. The
polarity of the output voltage is shown in Figure. The collector C2 is assumed to be more
positive with respect to collector C1 even though both are negative with respect to ground.
The output voltage VO is given by
Substituting ie1, & ie2 in the above expression

Thus a differential amplifier amplifies the difference between two input signals. Defining the
difference of input signals as Vd =V1-V2 the voltage gain of the dual input balanced output
differential amplifier can be given by (E-2)

Differential Input Resistance:

Differential input resistance is defined as the equivalent resistance that would be

measured at either input terminal with the other terminal grounded. This means that the input
resistance Ri1 seen from the input signal source V1 is determined with the signal source V2
set at zero.
 Similarly, the input signal V1 set at zero to determine the input resistance Ri2 seen
from the input signal source V2. Resistance RS1 and RS2 are ignored because they are very
small.

Substituting ie1,

Similarly

The factor of 2 arises because the re' of each transistor is in series. To get very high
input impedance with differential amplifier is to use Darlington transistors. Another ways is
to use FET.

Output Resistance:

Output resistance is defined as the equivalent resistance that would be measured at

output terminal with respect to ground. Therefore, the output resistance RO1 measured
between collector C1 and ground is equal to that of the collector resistance RC. Similarly the
output resistance RO2 measured at C2 with respect to ground is equal to that of the collector
resistor RC.RO1 = RO2 = RC (E-5)

The current gain of the differential amplifier is undefined. Like CE amplifier the
differential amplifier is a small signal amplifier. It is generally used as a voltage amplifier
and not as current or power amplifier.

2) Dual Input, Unbalanced Output Differential Amplifier:

Fig. 1.12 Differential Amplifier

 In this case, two input signals are given however the output is measured at only one of
the two- collector w.r.t. ground as shown infig1.12. The output is referred to as an unbalanced
output because the collector at which the output voltage is measured is at some finite dc
potential with respect to ground.

In other words, there is some dc voltage at the output terminal without any input
signal applied. DC analysis is exactly same as that of first case.

AC Analysis:

The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential
amplifier. Since at the output there is a dc error voltage, therefore, to reduce the voltage to
zero, this configuration is normally followed by a level translator circuit.

Level Translator:

Because of the direct coupling the dc level at the emitter rises from stages to stage.
This increase in dc level tends to shift the operating point of the succeeding stages and
therefore limits the output voltage swing and may even distort the output signal.

To shift the output dc level to zero, level translator circuits are used. An emitter follower with
voltage divider is the simplest form of level translator as shown in fig 1.13. Thus a dc voltage
at the base of Q produces 0V dc at the output. It is decided by R1 and R2. Instead of voltage
divider emitter follower either with diode current bias or current mirror bias as shown in fig
1.14may be used to get better results.
 Fig1.14 Common collector Amplifier

In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V. If this shift is
not sufficient, the output may be taken at the junction of two resistors in the emitter leg.

Fig.1.15 shows a complete op-amp circuit having input different amplifiers with
balanced output, intermediate stage with unbalanced output, level shifter and an output
amplifier.

Fig.1.15 Circuit Diagram of OP-AMP

 OP-AMP CHARACTERISTICS
DC CHARACTERISTICS:

a) Input offset voltage:

Input offset voltage Vio is the differential input voltage that exists between two input
terminals of an op-amp without any external inputs applied. In other words, it is the amount
of the input voltage that should be applied between two input terminals in order to force the
output voltage to zero. Let us denote the output offset voltage due to input offset voltage Vio
as Voo. The output offset voltage Voo is caused by mismatching between two input
terminals. Even though all the components are integrated on the same chip, it is not possible
to have two transistors in the input differential amplifier stage with exactly the same
characteristics. This means that the collector currents in these two transistors are not equal,
which causes a differential output voltage from the first stage. The output of first stage is
amplified by following stages and possibly aggravated by more mismatching in them.

Fig 1.16 Input offset voltage in op-amp Fig 1.17 Output offset voltage in op-amp

Fig 1.18.Op-Amp with offset voltage compensating network

 The op-amp with offset-voltage compensating network is shown in Figure1.18. The
Compensating network consists of potentiometer Ra and resistors Rb and Re. To establish a
relationship between Vio, supply voltages, and the compensating components, first Thevenize
the circuit, looking back into Ra from point T. The maximum Thevenin’s equivalent
resistance Rmax, occurs when the wiper is at the center of the Potentiometer, as shown in
Figure.

Rmax =(R a /2)||(R a /2)

Supply voltages VCC and –VEE are equal in magnitude therefore; let us denote their

magnitude by voltage V.

Thus Vmax= V.

where V2 has been expressed as a function of maximum Thevenin‘s voltage Vmax and
maximum Thevenin‘s resistance, But the maximum value of V2 can be equal to Vio since V1

— V2 = Vio. Thus Equation becomes

Assume Rb >Rmax >Rc, where Rmax = Ra/4. Using this assumption

Rmax+Rb+Rc=Rb Therefore
 Let us now examine the effect of Vio in amplifiers with feedback. The non-
inverting and inverting amplifiers with feedback are shown in Figure.1.19. To determine
the effect of Vio, in each case, we have to reduce the input voltage vin to zero.

Fig 1.19 Closed loop non inverting or inverting Amp

With vin reduced to zero, the circuits of both non-inverting and inverting amplifiers
are the sameas the circuit in Figure. The internal resistance Rin of the input signal voltage is
negligibly small.In the figure, the non-inverting input terminal is connected to ground;
therefore, assume voltageV1 at input terminal to be zero. The voltageV2 at the inverting input
terminal can be determinedby applying the voltage-divider rule:

b) Input offset voltage

A small voltage applied to the input terminals to make the output voltage as zero
when the two input terminals are grounded is called input offset voltage c) Input bias
currentInput bias current IB as the average value of the base currents entering into terminal of
an op-amp.
 IB=IB1=IB2

Obtaining the expression for the output offset voltage caused by the input bias current
IB in the inverting and non-inverting amplifiers and then devise some scheme to eliminate or
minimize it.

Fig 1.20 Op-Amp

In the figure, the input bias currents ‘81 and 1 are flowing into the non-inverting and
inverting input leads, respectively. The non-inverting terminal is connected to ground;
therefore, the voltage V1 = 0 V. The controlled voltage source A Vio =0 V since Vio= 0 V is
assumed. With output resistance Ro is negligibly small, the right end of RF is essentially at
ground potential; that is, resistors R1, and RF are in parallel and the bias current I, flows
through them. Therefore, the voltage at the inverting terminal is d) Thermal Drift:Bias
current, offset current and offset voltage change with temperature. A circuit carefully nulled
at 25oc may not remain so when the temperature rises to 35oc. This is called thermal drift.

AC CHARACTERISTICS:

a) Slew Rate

The slew rate is defined as the maximum rate of change of output voltage caused by a
step input voltage. An ideal slew rate is infinite which means that op-amp’s output voltage
should change instantaneously in response to input step voltage. The symbolic diagram of an
OPAMP is shown in fig 1.21

Fig.1.21 Op-Amp Symbol

b) Frequency Response

Need for frequency compensation in practical op-amps:

Frequency compensation is needed when large bandwidth and lower closed loop gain
is desired. Compensating networks are used to control the phase shift and hence to improve
the stability Frequency compensation methods: a) Dominant- pole compensation b) Pole-
zero compensation. 741c is most commonly used OPAMP available in IC package. It is an 8-
pin DIP chip.
Parameters of OPAMP:

1. Input Offset Voltage:

Fig. 1.22 Input offset voltage

 If no external input signal is applied to the op-amp at the inverting and non-inverting
terminals the output must be zero. That is, if Vi=0, Vo=0. But as a result of the given biasing
supply voltages, +Vcc and –Vcc, a finite bias current is drawn by the op-amps, and as a result
of asymmetry on the differential amplifier configuration, the output will not be zero. This is
known as offset. Since Vo must be zero when Vi=0 an input voltage must be applied such
that the output offset is cancelled and Vo is made zero. This is known as input offset voltage.
Input offset voltage (Vio) is defined as the voltage that must be applied between the two input
terminals of an OPAMP to null or zero the output voltage. Fig 1.22 shows that two dc
voltages are applied to input terminals to make the output zero.

Vio = Vdc1- Vdc2

Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference
of Vdc1 and Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value
of Vio is 6mV. It means a voltage ± 6 mV is required to one of the input to reduce the output
offset voltage to zero. The smaller the input offset voltage the better the differential amplifier,
because its transistors are more closely matched.
2. Input offset Current:
Though for an ideal op-amp the input impedance is infinite, it is not so practically. So
the IC draws current from the source, however smaller it may be. This is called input offset
current Iio. The input offset current Iio is the difference between the currents into inverting
and non-inverting terminals of a balanced amplifier as shown in fig 1.22.

Iio = | IB1- IB2 |

The Iio for the 741C is 200nA maximum. As the matching between two input
terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value
decreases further. For a precision OPAMP 741C, Iio is 6 nA
3. Input Bias Current:
The input bias current IB is the average of the current entering the input terminals of a balanced
amplifier i.e.
IB = (IB1 + IB2 ) / 2
For ideal op-amp IB=0. For 741C IB(max) = 700 nA and for precision 741C IB = ± 7 nA

4. Differential Input Resistance: (Ri)

Ri is the equivalent resistance that can be measured at either the inverting or non-
inverting input terminal with the other terminal grounded. For the 741C the input resistance is
relatively high 2 MΩ. For some OPAMP it may be up to 1000 G ohm.

5. Input Capacitance: (Ci)

Ci is the equivalent capacitance that can be measured at either the inverting and non
inverting terminal with the other terminal connected to ground. A typical value of Ci is 1.4 pf
for the 741C.
6. Offset Voltage Adjustment Range:

741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null
for this purpose. It can be done by connecting 10 K ohm pot between 1 and 5.

By varying the potentiometer, output offset voltage (with inputs grounded) can be
reduced to zero volts. Thus the offset voltage adjustment range is the range through which the
input offset voltage can be adjusted by varying 10 K pot. For the 741C the offset voltage
adjustment range is ± 15 mV.

7. Input Voltage Range :

Input voltage range is the range of a common mode input signal for which a
differential amplifier remains linear. It is used to determine the degree of matching between
the inverting and non-inverting input terminals. For the 741C, the range of the input common

mode voltage is ± 13V maximum. This means that the common mode voltage applied at both
input terminals can be as high as +13V or as low as -13V.

8. Common Mode Rejection Ratio (CMRR).

CMRR is defined as the ratio of the differential voltage gain Ad to the common mode
voltage gain

ACM CMRR = Ad / ACM.

For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is
the matching between two input terminals and the smaller is the output common mode
voltage.

9. Supply voltage Rejection Ratio: (SVRR)

SVRR is the ratio of the change in the input offset voltage to the corresponding
change in power supply voltages. This is expressed inΔV / V or in decibels, SVRR can be
defined as

SVRR =ΔVio / ΔV
Where ΔV is the change in the input supply voltage and ΔVio is the corresponding change
in the offset voltage.

For the 741C, SVRR = 150 μ V / V.

For 741C, SVRR is measured for both supply magnitudes increasing or decreasing
simultaneously, with R3= 10K. For same OPAMPS, SVRR is separately specified as positive
SVRR and negative SVRR.

10. Large Signal Voltage Gain:

Since the OPAMP amplifies difference voltage between two input terminals, the
voltage gain of the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage gain
is commonly called large signal voltage gain. For 741C is voltage gain is 200,000 typically.

11. Output voltage Swing:

The ac output compliance PP is the maximum unclipped peak to peak output voltage
that an OPAMP can produce. Since the quiescent output is ideally zero, the ac output voltage
can swing positive or negative. This also indicates the values of positive and negative
saturation voltages of the OP-AMP. The output voltage never exceeds these limits for a given
supply voltages +VCC and -VEE. For a 741C it is ± 13 V.

12. Output Resistance: (RO)

RO is the equivalent resistance that can be measured between the output terminal of
the OPAMP and the ground. It is 75 ohm for the 741C OPAMP.

13. Output Short circuit Current :

In some applications, an OPAMP may drive a load resistance that is approximately

zero. Even its output impedance is 75 ohm but cannot supply large currents. Since OPAMP
is low power device and so its output current is limited. The 741C can supply a maximum
short circuit output current of only 25mA.
14. Supply Current:

IS is the current drawn by the OP-AMP from the supply. For the 741C OPAMP the
supply current is 2.8 m A.

15. Power Consumption:

Power consumption (PC) is the amount of quiescent power (Vin= 0V) that must be
consumed by the OPAMP in order to operate properly. The amount of power consumed by
the 741C is 85 m W.

16. Gain Bandwidth Product:

The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage
gain is reduced to

1. From open loop gain vs frequency graph At 1 MHz shown in.fig.1.24,it can be found
1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage
gain is 100, 000 and cut off frequency is 10Hz.

Fig.1.24 Band width of OP-AMP

17. Slew Rate: Slew rate is defined as the maximum rate of change of output voltage per unit

of time under large signal conditions and is expressed in volts / μsecs.

 To understand this, consider a charging current of a capacitor

If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is
also limited. Slew rate indicates how rapidly the output of an OP-AMP can change in
response to changes in the input frequency with input amplitude constant. The slew rate
changes with change in voltage gain and is normally specified at unity gain.

If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the
slew rate is low 0.5 V / μS which limits its use in higher frequency applications.

18. Input Offset Voltage and Current Drift:

It is also called average temperature coefficient of input offset voltage or input offset
current. The input offset voltage drift is the ratio of the change in input offset voltage to
change in temperature and expressed in ΔV /° C. Input offset voltage drift = ( ΔVio /ΔT).
Similarly, input offset current drift is the ratio of the change in input offset current to the
change in temperature. Input offset current drift = ( ΔIio / ΔT).

For 741C,

ΔVio / ΔT = 0.5 V / C. Iio/ ΔT = 12 pA / C

PIN DIAGRAM OF 741-OP AMP
FEATURES OF 741 OP-AMP:

1. No External frequency compensation is required

2. Short circuit Protection

3. Off Set Null Capability

4. Large Common mode and differential Voltage ranges

5. Low Power Dissipation

6. No-Latch up Problem

7.741 is available in three packages:- 8-pin metal can, 10-pin flat pack and 8 or 14-pin DI.

MODES OF OPERATION OF OP-AMP

There are 2 modes in which an op-amp operates:

1. open loop mode

2. closed loop mode

Open loop OPAMP mode:

In the case of amplifiers the term open loop indicates that no connection exists between
input and output terminals of any type. That is, the output signal is not fedback in any form
as part of the input signal. In open loop configuration, The OPAMP functions as a high gain
amplifier. There are three open loop OPAMP configurations.

1. The Differential Amplifier:

The open loop differential amplifier in which input signals vin1 and vin2 are applied

to the positive and negative input terminals. Since the OPAMP amplifies the difference the

between the two input signals, this configuration is called the differential amplifier. The

OPAMP amplifies both ac and dc input signals. The source resistance Rin1 and Rin2 are

normally negligible compared to the input resistance Ri. Therefore voltage drop across these

resistances can be assumed to be zero.

Therefore
 v1 = vin1 and v2 = vin2. vo = Ad (vin1- vin2 )

where, Ad is the open loop gain.

2. The Inverting Amplifier:

If the input is applied to only inverting terminal and non-inverting terminal is

grounded then it is called inverting amplifier. This configuration is shown in fig 1.27.

v1= 0, v2 = vin. vo = -Ad vi

Fig.1.27 Inverting Amplifier

The negative sign indicates that the output voltage is out of phase with respect to input 180 °
or is of opposite polarity. Thus the input signal is amplified and inverted also.

3 .The non-inverting amplifier:

In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is
ground as shown in fig.1.28

v1 = +vin , v2 = 0 vo = +Ad vin

This means that the input voltage is amplified by Ad and there is no phase reversal at
the output.

ig.1.28 Non Inverting Amplifier

 In all there configurations any input signal slightly greater than zero drive the output
to saturation level. This is because of very high gain. Thus when operated in open-loop, the
output of the OPAMP is either negative or positive saturation or switches between positive
and negative saturation levels. Therefore open loop op-amp is not used in linear applications.

Closed Loop mode:

The Open Loop Gain of an ideal operational amplifier can be very high, as much as
1,000,000 (120dB) or more. However, this very high gain is of no real use to us as it makes
the amplifier both unstable and hard to control as the smallest of input signals, just a few
micro-volts, (μV) would be enough to cause the output voltage to saturate and swing towards
one or the other of the voltage supply rails losing complete control of the output.

As the open loop DC gain of an operational amplifier is extremely high we can

therefore afford to lose some of this high gain by connecting a suitable resistor across the
amplifier from the output terminal back to the inverting input terminal to both reduce and
control the overall gain of the amplifier. This then produces and effect known commonly as
Negative Feedback, and thus produces a very stable Operational Amplifier based system.

Negative Feedback is the process of "feeding back" a fraction of the output signal
back to the input, but to make the feedback negative, we must feed it back to the negative or
"inverting input" terminal of the op-amp using an external Feedback Resistor called Rƒ. This
feedback connection between the output and the inverting input terminal forces the
differential input voltage towards zero.

This effect produces a closed loop circuit to the amplifier resulting in the gain of the
amplifier now being called its Closed-loop Gain. Then a closed-loop inverting amplifier uses
negative feedback to accurately control the overall gain of the amplifier, but at a cost in the
reduction of the amplifiers bandwidth. This negative feedback results in the inverting input
terminal having a different signal on it than the actual input voltage as it will be the sum of
the input voltage plus the negative feedback voltage giving it the label or term of a Summing
Point. We must therefore separate the real input signal from the inverting input by using an
Input Resistor, Rin. As we are not using the positive non-inverting input this is connected to a
common ground or zero voltage terminal as shown below, but the effect of this closed loop
feedback circuit results in the voltage potential at the inverting input being equal to that at the
non-inverting input producing a Virtual Earth summing point because it will be at the same
potential as the grounded reference input. In other words, the op-amp becomes a "differential
amplifier".
 Inverting Amplifier Configuration

Fig 1.29 Inverting amplifier with feedback.

In this Inverting Amplifier circuit the operational amplifier is connected with

feedback to produce a closed loop operation. For ideal op-amps there are two very important
rules to remember about inverting amplifiers, these are: "no current flows into the input
terminal" and that "V1 equals V2", (in real world op-amps both of these rules are broken).

This is because the junction of the input and feedback signal ( X ) is at the same
potential as the positive ( + ) input which is at zero volts or ground then, the junction is a
"Virtual Earth". Because of this virtual earth node the input resistance of the amplifier is
equal to the value of the input resistor, Rin and the closed loop gain of the inverting amplifier
can be set by the ratio of the two external resistors.We said above that there are two very
important rules to remember about Inverting Amplifiers or any operational amplifier for that
matter and these are.

1. No Current Flows into the Input Terminals

2. The Differential Input Voltage is Zero as V1 = V2 = 0 (Virtual Earth)

Then by using these two rules we can derive the equation for calculating the closed-loop
gain of an inverting amplifier, using first principles.

Current ( i ) flows through the resistor network as shown.

Then, the Closed-Loop Voltage Gain of an Inverting Amplifier is given

as

and this can be transposed to give Vout as:

The negative sign in the equation indicates an inversion of the output signal with respect to
the input as it is 180o out of phase. This is due to the feedback being negative in value.

The Non-inverting Amplifier

The second basic configuration of an operational amplifier circuit is that of a Non-

inverting Amplifier. In this configuration, the input voltage signal, ( Vin ) is applied directly
to the non- inverting ( + ) input terminal which means that the output gain of the amplifier
becomes "Positive" in value in contrast to the "Inverting Amplifier" circuit we saw in the last
tutorial whose output gain is negative in value. The result of this is that the output signal is
"in-phase" with the input signal.

Feedback control of the non-inverting amplifier is achieved by applying a small part

of the output voltage signal back to the inverting ( - ) input terminal via a Rƒ - R2 voltage

divider network, again producing negative feedback. This closed-loop configuration produces
a non-inverting amplifier circuit with very good stability, very high input impedance, Rin
approaching infinity, as no current flows into the positive input terminal, (ideal conditions)
and low output impedance, Rout as shown below.

Non-inverting Amplifier Configuration

Fig 1.30 Non-inverting amplifier with feedback.

As said in the Inverting Amplifier that "no current flows into the input" of the
amplifier and that "V1 equals V2". This was because the junction of the input and feedback
signal ( V1 ) are at the same potential. In other words the junction is a "virtual earth"
summing point. Because of this virtual earth node the resistors, Rƒ and R2 form a simple
potential divider network across the non-inverting amplifier with the voltage gain of the
circuit being determined by the ratios of R2 and Rƒ as shown below.

Equivalent Potential Divider Network

Fig 1.31 potential divider in non-inverting op-amp

From the fig 1.31 using the formula to calculate the output voltage of a potential divider
network, we can calculate the closed-loop voltage gain ( A V ) of the Non-inverting
Amplifier as follows:

We can see from the equation above, that the overall closed-loop gain of a non-
inverting amplifier will always be greater but never less than one (unity), it is positive in
nature and is determined by the ratio of the values of Rƒ and R2. If the value of the feedback
resistor Rƒ is zero, the gain of the amplifier will be exactly equal to one (unity). If resistor R2
is zero the gain will approach infinity, but in practice it will be limited to the operational
amplifiers open-loop differential gain, ( Ao ).

Voltage Follower (Unity Gain Buffer)

If we made the feedback resistor, Rƒ equal to zero, (Rƒ = 0), and resistor R2 equal to
infinity, (R2 = ∞) as shown in fig 1.32, then the circuit would have a fixed gain of "1" as all
the output voltage would be present on the inverting input terminal (negative feedback). This
would then produce a special type of the non-inverting amplifier circuit called a Voltage
Follower or also called a "unity gain buffer".

As the input signal is connected directly to the non-inverting input of the amplifier the output
signal is not inverted resulting in the output voltage being equal to the input voltage, Vout =
Vin. This then makes the voltage follower circuit ideal as a Unity Gain Buffer circuit because
of its isolation properties as impedance or circuit isolation is more important than
amplification while maintaining the signal voltage. The input impedance of the voltage
follower circuit is very high, typically above 1MΩ as it is equal to that of the operational
amplifiers input resistance times its gain ( Rin x Ao ). Also its output impedance is very low
since an ideal op-amp condition is assumed.

Fig 1.32 voltage follower

In this non-inverting circuit configuration, the input impedance Rin has increased to
infinity and the feedback impedance Rƒ reduced to zero. The output is connected directly
back to the negative inverting input so the feedback is 100% and Vin is exactly equal to Vout
giving it a fixed gain of 1 or unity. As the input voltage Vin is applied to the non-inverting
input the gain of the amplifier is given as:

One final thought, the output voltage gain of the voltage follower circuit with closed
loop gain is Unity, the voltage gain of an ideal operational amplifier with open loop gain (no
feedback) is Infinite. Then by carefully selecting the feedback components we can control
the amount of gain produced by an operational amplifier anywhere from one to infinity.
 UNIT-II
OP-AMP APPLICATIONS-I
OPEN LOOP OP-AMP CONFIGURATIONS

In the case of amplifiers the term open loop indicates that no connection exists between input and output
terminals of any type. That is, the output signal is not fed back in any form as part of the input signal.

In open loop configuration, The Op-Amp functions as a high gain amplifier. There are three open loop
Op-Amp configurations namely

1).The Inverting Amplifier

2).The non-inverting amplifier

3).The Differential Amplifier

THE INVERTING AMPLIFIER

If the input is applied to only inverting input terminal and non-inverting input terminal is grounded then
it is called inverting amplifier. This configuration is as shown in fig.

V1=Voltage at non-inverting input terminal= 0 V

Fig V2 = Voltage at non-inverting input terminal= Vin V

Vo = Ad (V1- V2)= -Ad Vin

Where Ad = Differential Voltage Gain.

The negative sign indicates that the output voltage is out of phase with respect to input by 180 °. Thus
the input signal is amplified and inverted also.

THE NON-INVERTING AMPLIFIER

If the input is applied to only non-inverting input terminal and inverting input terminal is grounded then
it is called non-inverting amplifier. This configuration is as shown in fig.

V1=Voltage at non-inverting input terminal= Vin V

Fig V2 = Voltage at non-inverting input terminal= 0 V

 Vo = Ad (V1- V2)= Ad Vin

Where Ad = Differential Voltage Gain.

This means that the input voltage is amplified by Ad and there is no phase reversal at the output.

THE DIFFERENTIAL AMPLIFIER

Fig shows the open loop differential amplifier in which input signals Vin1 and Vin2 are applied to the non-
inverting and inverting input terminals.

Fig.

Since the Op-Amp amplifies the difference between the two input signals, this configuration is called the
differential amplifier. The Op-Amp amplifies both ac and dc input signals. The source resistance
Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop across
these resistances can be assumed to be zero.

Therefore

V1 = Vin1 and V2 = Vin2.

Vo = Ad (V1 – V2) = Ad (Vin1 – Vin2)

Where, Ad = Differential Voltage Gain.

In all three configurations any input signal slightly greater than zero drive the output to saturation level.
This is because of very high gain. Thus when operated in open-loop, the output of the Op-Amp is either
negative or positive saturation or switches between positive and negative saturation levels. Therefore
open loop Op-Amp is not used in linear applications.

CLOSED LOOP OP-AMP CONFIGURATIONS

 The gain of the Op-Amp can be controlled if feedback is introduced in the circuit, i.e an output
signal is fedback to the input either directly or via another network. If the signal fedback is of
opposite or out phase by 180° with respect to the input signal, the feedback is called negative
feedback.
 An amplifier with negative fedback has a self-correcting ability of change in output voltage
caused by changes in environmental conditions. It is also known as degenerative feedback
because it reduces the output voltage and in turn reduces the voltage gain.

 If the signal is fedback in phase with the input signal, the feedback is called positive feedback. In
positive feedback the feedback signal aids the input signal. It is also known as regenerative
feedback. Positive feedback is necessary in oscillator circuits.
Advantages Of negative feedback:

1. The negative fedback stabilizes the gain.

2. Increases the bandwidth.

3. Changes the input and output resistances.

4. Reduces harmonic or non-linear distortions.

5. Reduces the effect of input offset voltage at the output.

6. It also reduces the effect of temperature and supply voltage variation on the output of an Op-
Amp.

 A closed loop amplifier can be represented by two blocks one for an Op-Amp and other for a
feedback circuit. There are four ways to connect these blocks. These connections are shown
in fig.

 These connections are classified according to whether the voltage or current is fedback to the
input in series or in parallel as

1. Voltage – series feedback

2. Voltage – shunt feedback
3. Current – series feedback
4. Current – shunt feedback

Fig

 In all these circuits the signal direction is from input to output for Op-Amp and output to input
for feedback circuit.
 Only first two, feedback circuits are important.

Voltage series feedback:

  The schematic diagram of the Voltage series feedback amplifier is as shown in fig. The Op-
Amp is represented by its schematic symbol, including its large signal voltage gain Ad or A, and
the feedback circuit is composed of two resistors R1 and Rf.
 The circuit is commonly known as a non-inverting amplifier with feedback or a closed loop
non-inverting amplifier because it uses feedback, and the input signal is applied to the non-
inverting input terminal of the Op-amp.

 Before proceeding, it is necessary to define some important terms for the voltage
series feedback amplifier. Especially the voltage gain of the Op-Amp with feedback
and voltage gain of the feedback circuit as below.

Negative Feedback:

The feedback voltage always opposes the input voltage, (or is out of phase by 180° with respect to input
voltage), hence the feedback is said to be negative.

Closed Loop Voltage Gain:

Closed loop voltage gain is defined as

The product A and B is called loop gain. The gain loop gain is very large such that AB >> 1
  This shows that overall voltage gain of the circuit equals the reciprocal of B, the feedback gain. It
means that closed loop gain is no longer dependent on the gain of the Op-Amp, but depends on
the feedback of the voltage divider. The feedback gain B can be precisely controlled and it is
independent of the amplifier.

 Physically, what is happening in the circuit? The gain is approximately constant, even though
differential voltage gain may change. Suppose A increases for some reasons (temperature
change). Then the output voltage will try to increase. This means that more voltage is fedback to
the inverting input, causing Vd voltage to decrease. This almost completely offset the attempted
increases in output voltage.

 Similarly, if A decreases, The output voltage decreases. It reduces the feedback voltage Vf and
hence, Vd voltage increases. Thus the output voltage increases almost to same level.

Block Diagram representation of non-inverting amplifier with feedback

Difference Input voltage Ideally zero:

Again considering the voltage equation,

VO = Ad Vd

or Vd = VO / Ad

Since Ad is very large (ideally infinite)

Vd = ͌ 0.

and V1 = V2 (ideal).

This says that the voltage at non-inverting input terminal of an Op-Amp is approximately equal to that at
the inverting input terminal provided that Ad is very large. This concept is useful in the analysis of
closed loop Op-Amp circuits. For example, ideal closed loop voltage again can be obtained using the
results.
Input Resistance with Feedback:

Fig shows a voltage series feedback with the Op-Amp equivalent circuit.

Fig. 1
In this circuit Ri is the input resistance (open loop) of the Op-Amp and Rif is the input resistance of the
feedback amplifier. The input resistance with feedback is defined as

Since AB is much larger than 1, which means that Rif is much larger that Ri. Thus Rif approaches infinity
and therefore, this amplifier approximates an ideal voltage amplifier.

Output Resistance with Feedback:

Output resistance is the resistance determined looking back into the feedback amplifier from the output
terminal. To find output resistance with feedback Rof , input Vin is reduced to zero, an external voltage
Vo is applied as shown in fig.

The output resistance (Rof ) is defined as

This shows that the output resistance of the voltage series feedback amplifier is ( 1 / 1+AB )
times the output resistance Ro of the Op-Amp . It is very small because (1+AB) is very large. It
approaches to zero for an ideal voltage amplifier.

Reduced Non-linear Distortion:

The final stage of an Op-Amp has non-linear distortion when the signal swings over most of the ac load
line. Large swings in current cause the r'e of a transistor to change during the cycle. In other words, the
open loop gain varies throughout the cycle of when a large signal is being applied. It is this changing
voltage gain that is a source of the non-linear distortion.

Non-inverting voltage feedback reduces non-linear distortion because the feedback stabilizes the closed
loop voltage gain, making it almost independent of the changes in open loop voltage gain. As long as
loop gain, is much greater than 1, the output voltage equals 1/B times the input voltage. This implies that
output will be a more faithful reproduction of the input.
Consider, under large signal conditions, the open loop Op-Amp circuit produces a distortion voltage,
designated Vdist. It can be represented by connecting a source Vdist in series with Avd. Without negative
feedback all the distortion voltage Vdist appears at the output. But with negative feedback, a fraction of
Vdist is feedback to inverting input. This is amplified and arrives at the output with inverted phase almost
completely canceling the original distortion produced by the output stage.

The first term is the amplified output voltage. The second term in the distortion that appears at the final
output. The distortion voltage is very much, reduced because AB>>1

Bandwidth with Feedback:

The bandwidth of an amplifier is defined as the band of frequencies for which the gain remains
constant. Fig shows the open loop gain vs frequency curve of µA741C Op-Amp. From this curve for a
gain of 2 x 105 the bandwidth is approximately 5Hz. On the other hand, the bandwidth is approximately
1MHz when the gain is unity.

Fig. 3

 The frequency at which gain equals 1 is known as the unity gain bandwidth.
 It is the maximum frequency the Op-Amp can be used for.

 Furthermore, the gain bandwidth product obtained from the open loop gain vs frequency curve is
equal to the unity gain bandwidth of the Op-Amp .
Since the gain bandwidth product is constant obviously the higher the gain the smaller the
bandwidth and vice versa.

 If negative feedback is used gain decrease from A to A / (1+AB). Therefore the closed loop
bandwidth increases by (1+AB).

Bandwidth with feedback = (1+ A B) x (B.W. without feedback)

ff= fo (1+A B)
Total output Offset Voltage with Feedback:

 In an Op-Amp when the input is zero the out is also expected to be zero. However because of
the effect of input offset voltage and current the output is significantly large, resulting in high
open loop gain i.e the high gain aggravates the effect of input offset and current at the output.
 We call this enhanced output voltage the total output offset voltage (VOOT). In an open loop
op-amp the total output offset voltage is equal to either the positive or negative saturation
voltage. The saturation voltage is equal to output voltage swing.
 Since with feedback the gain of the non-inverting amplifier changes from A to A /1+AB the
total output offset voltage with feedback must also be 1/1+AB times the voltage without
feedback i.e

(Total output offset voltage ) = Total output offset voltage without feedback with feed back
1+AB

VOOT = ± Vsat / 1+AB

Where 1/1+AB is always less than 1 and ± Vsat= saturation voltages.

Voltage Follower:

The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When the non-
inverting amplifier gives unity gain, it is called voltage follower because the output voltage is equal to
the input voltage and in phase with the input voltage. In other words the output voltage follows the input
voltage.

To obtain voltage follower, R1 is open circuited and Rf is shorted in a negative feedback amplifier. The
resultant circuit is shown in fig
Vout = AVd= A (V1 – V2)

V1 = Vin

V2 =Vout

V1 = V2 if A >> 1

Vout = Vin.

The gain of the feedback circuit (B) is 1. Therefore

Fig.
Af = 1 / B = 1

Voltage shunt Feedback:

Fig. Shows the voltage shunt feedback amplifier using Op-Amp .

Fig.

The input voltage drives the inverting terminal, and the amplified as well as inverted output signal is also
applied to the inverting input via the feedback resistor R f. This arrangement forms a negative feedback
because any increase in the output signal results in a feedback signal into the inverting input signal
causing a decrease in the output signal. The non-inverting terminal is grounded. Resistor R 1 is connected
in series with the source.

The closed loop voltage gain can be obtained by, writing Kirchhoff’s current equation at the input node
V2.
The negative sign in equation indicates that the input and output signals are out of phase by 180.
Therefore it is called inverting amplifier. The gain can be selected by selecting R f and R1 (even < 1).

Inverting Input at Virtual Ground:

In the fig shown earlier, the non-inverting terminal is grounded and the- input signal is applied to the
inverting terminal via resistor R1. The difference input voltage vd is ideally zero, (vd= vO/ A) is the
voltage at the inverting terminals (v 2) is approximately equal to that of the noninverting terminal (V1). In
other words, the inverting terminal voltage (V1) is approximately at ground potential. Therefore, it is
said to be at virtual ground.

Input Resistance with Feedback:

To find the input resistance Miller
equivalent of the feedback resistor Rf, is
obtained, i.e. Rf is splitted into its two
Miller components as shown in fig. .
Therefore, input resistance with feedback
Rif is then

Fig.

Output Resistance with Feedback:

The output resistance with feedback Rof is

the resistance measured at the output
terminal of the feedback amplifier. The
output resistance can be obtained using
Thevenin's equivalent circuit,shown in fig.

i O = ia + ib

Since RO is very small as compared to Rf +

(R1 || R2 )

Therefore,i.e. iO= ia

vO = RO iO + A vd.

vd= vi – v2 = 0 - B vO

Fig.

Similarly, the bandwidth increases by (1+

AB) and total output offset voltage reduces
by (1+AB).

Example - 1
(a).An inverting amplifier is implemented with R 1 = 1K and Rf = 100 K. Find the percentge change in
the closed loop gain A is the open loop gain a changes from 2 x 10 5 V / V to 5 x 104 V/V.
(b) Repeat, but for a non-inverting amplifier with R1 = 1K at Rf = 99 K.

Solution: (a). Inverting amplifier

Here Rf = 100 K
R1 = 1K

When,

(b) Non-inverting amplifier

Here Rf =99K and R1 = 1K

Example - 2

An inverting amplifier with R1 = 10Ω and R2 = 1MΩ is driven by a source V1 = 0.1 V. Find the closed
loop gain A, the percentage division of A from the ideal value - R 2 / R1, and the inverting input voltage
VN for the cases A = 100 V/V, 105 and 105 V/V.
Solution:

we have

when A = 103,

Fig. 4

Example - 3

Find VN, V1 and VO for the circuit shown in fig.

Solution:

Applying KCL at N

or 2VN + VN = VO.

Now VO - Vi = 6 as point A and N are virtually shorted.

VO - VN = 6 V Fig.
Therefore, VO = VN + 6 V
Therefore, VN = Vi = 3 V.

SUMMING AMPLIFIER

Analog Inverter and Scale Changer:

The circuit of analog inverter is shown in fig. It is same as inverting voltage amplifier.

Assuming OP-AMP to be an ideal one, the

differential input voltage is zero.

i.e. Vd = 0
Therefore, V1 = V2 = 0

Since input impedance is very high, therefore, input

current is zero. OP-AMP do not sink any current.

Therefore iin= if

Vin / R = - VO / Rf
Vo = - (Rf / R) Vin

If R = Rf then VO = -Vin the circuit Fig.

behaves like an inverter.

If Rf / R = K (a constant) then the circuit is called

inverting amplifier or scale changer voltages.

Inverting summer:

The configuration is shown in fig. With three input voltages Va, Vb & Vc. Depending upon the
value of Rf and the input resistors Ra, Rb, Rc the circuit can be used as a summing amplifier,
scaling amplifier, or averaging amplifier.

Applying KCL at V2 node

This means that the output voltage is equal to the Fig.

negative sum of all the inputs times the gain of the
circuit Rf/ R; hence the circuit is called a summing
amplifier. When Rf= R then the output voltage is
equal to the negative sum of all inputs.
Vo= -(Va+ Vb+ Vc)

If each input voltage is amplified by a different factor in other words weighted differently at the output,
the circuit is called then scaling amplifier.

The circuit can be used as an averaging circuit, in which the output voltage is equal to the average of all
the input voltages.

In this case, Ra= Rb= Rc = R and Rf / R = 1 / n where n is the number of inputs. Here Rf / R =
1 / 3. Vo = -(Va+ Vb +
Vc) / 3

In all these applications input could be either ac or dc.

Non-inverting configuration:

If the input voltages are connected to non-inverting input through resistors, then the circuit can be used
as a summing or averaging amplifier through proper selection of R1, R2, R3 and Rf. as shown in fig.

To find the output voltage expression, V1 is required.

Applying superposition theorem, the voltage V1 at the
non-inverting terminal is given by

Hence the output voltage is

Fig.

This shows that the output is equal to the average of all input voltages times the gain of the circuit (1+
Rf / R1), hence the name averaging amplifier.

If (1+Rf/ R1) is made equal to 3 then the output voltage becomes sum of all three input voltages.

Vo =V a + Vb+ Vc

Hence, the circuit is called summing amplifier.

Example - 1

Find the gain of VO / Vi of the circuit of fig.

Solution:

Current entering at the inveting terminal is

Applying KCL to node 1,

Applying KCL to node 2,

Fig.

Thus the gain A = -8 V / VO

Example – 2

Find a relationship between VO and V1 through V6 in the circuit of fig.

Fig.
Solution:

Let's consider of V1 (singly) by shorting the others i.e. the circuit then looks like as shown in fig.

The current flowing through the resistor R into the i/e.

The current when passes through R, output an

operational value of

Let as Fig.
now consider the case of V2 with other inputs shorted,
circuit looks like as shown in fig.
Now VO is given by

same thing to V4 and V6

net output V" = V2 + V4 + V6 (3)

From (2) & (3)

V' + V" = (V2 + V4 + V6 ) - (V1 + V3 + V5) Fig.

So VO = V2 + V4 + V6 - V1 - V3 - V5.

Example - 3

1. Show that the circuit of fig. has A = VO / Vi = - K (R2 / R1) with K=1+
R4 / R2 + R4 / R3, and Ri = R1.
2. Specify resistance not larger than 100 K to achieve A = -200 V / V and Ri = 100 K.
 Fig.

Solution:

Differential Amplifier(Subtractor):

The basic differential amplifier is shown in fig.

Fig.

Since there are two inputs superposition theorem can be used to find the output voltage. When Vb= 0,
then the circuit becomes inverting amplifier, hence the output due to Va only is

Vo(a) = -(Rf / R1) Va

Similarly when, Va = 0, the configuration is a inverting amplifier having a voltage divided network at the
non-inverting input

INTEGRATOR

A circuit in which the output voltage waveform is the integral of the input voltage waveform is called
integrator. Fig. , shows an integrator circuit using OP-AMP.
Fig.

Here, the feedback element is a capacitor. The current drawn by OP-AMP is zero and also the V2 is
virtually grounded.

Therefore, i1 = if and V2 = V1 = 0

Integrating both sides with respect to time from 0 to t, we get

The output voltage is directly proportional to the negative integral of the input voltage and inversely
proportional to the time constant RC.

If the input is a sine wave the output will be cosine wave. If the input is a square wave, the output will be
a triangular wave. For accurate integration, the time period of the input signal T must be longer than or
equal to RC.

Fig. Shows the output of integrator for square and sinusoidal inputs.
Fig.

Example

Prove that the network shown in fig. is a non-inverting integrator with .

Solution:

The voltage at point A is VO / 2 and it is also the

voltage at point B because different input voltage is
negligible.

VB = VO / 2

Therefore, applying Node current equation at point B,

Fig.
DIFFERENTIATOR

Ideal Differentiator:

A circuit in which the output voltage waveform is the differentiation of input voltage is called
differentiator. As shown in fig.

Fig. (Ideal Differentiator)

The expression for the output voltage can be obtained from the Kirchhoff’s current equation written at
node V2.

Thus the output Vo is equal to the RC times the negative instantaneous rate of change of the input
voltage Vin with time. A cosine wave input produces sine wave output and a Square wave
input produces Spikes as output.

Practical Differentiator:

The input signal will be differentiated properly if the time period T of the input signal is larger than or
equal to Rf C, i.e T ≥ Rf C.

As the frequency changes, the gain changes. Also at higher frequencies the circuit is highly susceptible
at high frequency noise and noise gets amplified. Both the high frequency noise and problem can be
corrected by adding, few components. As shown in fig.
Fig. (Practical Differentiator)

VOLTAGE TO CURRENT CONVERTER

Floating Load:

Fig. shows a voltage to current converter in which load resistor RL is floating (not connected to ground).

The input voltage is applied to the non-inverting input terminal and the feedback voltage across R drives
the inverting input terminal. This circuit is also called a current series negative feedback, amplifier
because the feedback voltage across R depends on the output current i L and is in series with the input
difference voltage vd.

Writing the voltage equation for the input

loop.

Vin = Vd + Vf

But Vd =͌ 0 since A is very large, therefore,

Vin = Vf
Vin = R iin
iin = V in / R.

and since input current is zero.

iL = iin = Vin / R

The value of load resistance does not appear

in this equation. Therefore, the output
current is independent of the value of load
resistance. Thus the input voltage is Fig.
converted into current ,the source must be
capable of supplying this load current.
Grounded Load:

If the load has to be grounded, then the above circuit cannot be used. The modified circuit is shown
in fig.

Since the collector and emitter currents are equal to a close

approximation and the input impedance of OP-AMP is very
high, the load current also flows through the feedback
resistor R. On account of this, there is still current feedback,
which means that the load current is stabilized.

Since Vd= 0
V2 = V1 = Vin
iout = (VCC – Vin ) / R

Thus the load current becomes nearly equal to iout. There is a

limit to the output current that the circuit can supply. The
base current in the transistor equals iout /βdc. Since the Op-
Amp has to supply this base current iout /βdc must be less than
Iout (max) of the Op-Amp , typically 10 to 15mA.

There is also a limit on the output voltage, as the load

resistance increases, the load voltage increases and then the
transistor goes into saturation. Since the emitter is at Vin w. r. Fig.
t. ground, the maximum load voltage is slightly less than Vin.

In this circuit, because of negative feedback VBE is automatically adjusted. For instance, if the load
resistance decreases the load current tries to increase. This means that more voltage is feedback to the
inverting input, which decreases VBE just enough to almost completely nullify the attempted increase in
load current. From the output current expression it is clear that as Vin increases the load current
decreases.

Another circuit in which load current increases as Vin increases is shown in fig.

The current through the first transistor is

i = Vin / R

This current produces a collector voltage of

VC = VCC– i R = VCC – Vin

Since this voltage drives the non-inverting

input of the second Op-Amp. The inverting
voltage is VCC - Vin to a close
approximation. This implies that the voltage
across the final R is

VCC - (VCC - Vin ) = Vin

and the output current .

iout = Vin / R

As before, this output current must satisfy

the condition, that Iout/ βdc must be less
than the Iout(max) of the OP-AMP .
Furthermore, the load voltage cannot Fig.
exceed VCC- Vin because of transistor
saturation, therefore Iout R must be less than
VCC- Vin. This current source
produces unidirectional load current. fig.
shows a Howland current source, that can
produce a bi-directional load current.

Fig.

The maximum load current is VCC/ R. In this circuit v in

may be positive or negative.

CURRENT TO VOLTAGE CONVERTER

The circuit shown in fig. is a current to voltage converter.

Fig.

Due to virtual ground the current through R is zero and the input current flows through Rf. Therefore,
Vout =-Rf * iin

The lower limit on current measure with this circuit is set by the bias current of the inverting input.

Example –1:

For the current to current converter shown in fig. , prove that

Fig.

Solution:

The current through R1 can be obtained from the current divider circuit.

Since, the input impedance of OP-AMP is very large, the input current of OP-AMP is negligible.

Thus,

LOG AMPLIFIER

Log amplifier is a linear circuit in which the output voltage will be a constant times the natural logarithm
of the input. The basic output equation of a log amplifier is v Vout = K ln (Vin/Vref); where Vref is the
constant of normalization and K is the scale factor. Log amplifier finds a lot of application in electronic
fields like multiplication or division (they can be performed by the addition and subtraction of the logs
of the operand), signal processing, computerized process control, compression, decompression, RMS
value detection etc. Basically there are two log amp configurations: Op-Amp-diode log amplifier and
Op-Amp-transistor log.

Op-Amp-diode log amplifier:

The schematic of a simple Op-amp-diode log amplifier is shown above. This is nothing but an op-amp
wired in closed loop inverting configuration with a diode in the feedback path. The voltage across the
diode will be always proportional to the log of the current through it and when a diode is placed in the
feedback path of an op-amp in inverting mode, the output voltage will be proportional to the negative
log of the input current. Since the input current is proportional to the input voltage, we can say that the
output voltage will be proportional to the negative log of the input voltage.
According to the PN junction diode equation, the relationship between current and voltage for a diode is

Id=Is(e(Vd/Vt)-1)…………(1)

Where Id is the diode current, Is is the saturation current, Vd is the voltage across the diode and Vt is the
thermal voltage.
Since Vd the voltage across the diode is positive here and Vt the thermal voltage is a small quantity, the
equation (1) can be approximated as

Id = Is e(Vd/Vt)…………………(2)

Since an ideal op-amp has infinite input resistance, the input current Ir has only one path that is through
the diode. That means the input current is equal to the diode current (Id).
i.e Ir = Id ………………….(3)

Since the inverting input pin of the op-amp is virtually grounded, we can say that
Ir = Vin/R

Since Ir=Id from equation (3)

Vin/R = Id ………………….. (4)

Comparing equation (4) and (2) we have

Vin/R = Is e (Vd/Vt)
i.e. Vin = Is R e(Vd/Vt)……………(5)

Considering that the negative of the voltage across diode is the output voltage Vout

Vout = -Vt In(Vin/IsR)

Op-amp transistor log amplifier:
In this configuration a transistor is placed in the feedback path of an op-amp wired in inverting mode.
Collector of the transistor is connected to the inverting input of the op-amp, emitter to output and base
is grounded. The necessary condition for a log amp to work is that the input voltage must be always
positive. Circuit diagram of an Op-amp transistor log amplifier is shown below.

From Fig 2 it is clear that base-emitter voltage of the transistor

Vbe = -Vout ………(1)

We know that
Ic=Iso(e(Vbe/Vt)-1) ………….(2)

Where Ic is the collector current of the transistor, Iso the saturation current, Vbe the base emitter voltage
and Vt the thermal voltage.
Equation (1) can be approximated as

Ic=Isoe(Vbe/Vt) ………….(3)

i.e, Vbe = Vt In (Ic/Iso) …………….(4)

Since input pin of an ideal op-amp has infinite input impedance, the only path for the input current Ir is
through the transistor and that means Ir = Ic.
Since the inverting input of the op-amp is virtually grounded
Ir = Vin/R
That means Ic = Vin/R ……………(5)
From equations (5) , (4) and (1) it is clear that

Vout = -Vt ln (Vin/IsoR)………….(6)

INSTRUMENTATION AMPLIFIER
In many industrial and consumer applications the measurement and control of physical conditions are
very important. For example, measurements of temperature and humidity inside a diary or meat plant
permit the operator to make necessary adjustments to maintain product quality. Similarly, precise
temperature control of a plastic furnace is needed to produce a particular type of plastic.

Generally, a transducer is used at the measuring site to obtain the required information easily and
safely. The transducer is a device that converts one form of Energy into another. For example, a
strain gage when subjected to pressure or force undergoes a change in its resistance.

An Instrumentation system is used to measure the output signal produced by a transducer and often to
control the physical signal producing it.

The Block Diagram of an Instrumentation system.


The input stage is composed of a pre-amplifier and some sort of transducers, depending on the
physical quantity to be measured. The output stage may use devices such as meters,
oscilloscopes, charts or magnetic recorders.

 The connecting lines between the blocks represent transmission lines, used especially when the
transducer is at a remote test site monitoring hazardous conditions such as High temperatures or
liquid levels of flammable chemicals. These transmission lines permit signal transfer from unit to
unit.

 The signal source of the Instrumentation amplifier is the output of the transducer. Although
some transducers produce outputs with sufficient strength to permit their use directly, many do
not. To amplify the low level output signal of the transducer so that it can drive the indicator or
display is the major function of an Instrumentation amplifier. In short, Instrumentation amplifier
is intended for precise, low level signal amplification where low noise, low thermal and time
drifts, high input resistance, and accurate closed loop gain are required. Besides, low power
consumption, high common mode rejection ratio, and high slew rate are desirable for superior
performance.

INSTRUMENTATION AMPLIFIER USING TRANSDUCER BRIDGE

Following figure shows a simplified instrumentation amplifier using a transducer bridge. A

resistive transducer whose resistance changes as a function of some physical energy is connected in one
arm of the bridge with a small circle around it and is denoted by where RT is the resistance
of the transducer and ∆R is the change in resistance RT.
The bridge in circuit is dc excited but could be ac excited as well.
For the balanced bridge at some reference condition,

 Generally, resistors RA, RB, and Rc. are selected so that they are equal in value to the transducer
resistance RT at some reference condition. The reference condition is the specific value of the
physical quantity under measurement at which the bridge is balanced. This value is normally
established by the designer and depends on the transducer’s characteristics, the type of physical
quantity to be measured, and the desired application.
  The bridge is balanced initially at a desired reference condition. However, as the physical
quantity to be measured changes, the resistance of the transducer also changes, which causes the
bridge to unbalance (Va≠Vb). The output voltage of the bridge can be expressed as a function of
the change in resistance of the transducer, as described next.
 Let the change in the resistance of the transducer be ∆R. since RB and Rc are fixed resistors, the
voltage Vb is constant. However, voltage Va, varies as a function of the change in transducer
resistance.
 Therefore, according to the voltage-divider rule,

The negative sign in this equation indicated that Va<Vb because of the increase in the value of ∆R.
The output voltage Vab of the bridge is then applied to the differential instrumentation amplifier
composed of three op-amps. The voltage followers preceding the basic differential amplifier help to
eliminate loading of the bridge circuit. The gain of the basic differential amplifier is (-Rf/R1); therefore,
the output Vo of the circuit is,

Generally, the change in resistance of the transducer ∆R is very small. Therefore, we can approximate
(2R+∆R) ≈2R. Thus, the output voltage is,
The equation indicates that Vo is directly proportional to the change in resistance ∆R of the transducer.
Since the change in resistance is caused by a change in physical energy, a meter connected at the output
can be calibrated in terms of the units of that physical energy.

 Before proceeding with specific bridge applications, let us briefly consider the important
characteristics of some resistive types of transducers. In these resistive types of transducers the
resistance of the transducer changes as a function of some physical quantity.
 Thermistor, photoconductive cells, and strain gages are some of the most commonly used
resistive transducers hence they will be further discussed here.
 Thermistors are essentially semiconductors that behave as resistors, usually with a negative
temperature coefficient of resistance. That is, as the temperature of a thermistor increase, its
resistance decreases. The temperature coefficient of the resistance is expressed in ohms per unit
change in degrees Celsius. Thermistors with a high temperature coefficient of resistance are
more sensitive to temperature change and are therefore well suited to temperature measurement
and control. Thermistors are available in a wide variety of shapes and sizes. However, thermistor
beads sealed in the tips of glass rods are most commonly used because they are relatively easy to
mount.
 The photoconductive cell belongs to the family of photo-detectors (photosensitive devices)
whose resistance varies with an incident radiant energy or with light. As the intensity of incident
light increases, the resistance of the cell decreases. The resistance of the photoconductive cell in
darkness is typically on the order of I00 KΩ. Generally, the resistance of the cell in darkness and
at particular light intensities is listed on the data sheet. The intensity of light is expressed in meter
candles (lux).
 Materials such as cadmium sulfide and silicon, whose conductivity is a function of incident
radiant energy, are used for photoconductive cells. Some cells are extremely sensitive to light
and hence can be used into the ultraviolet and infrared regions. The photoconductive cell is
typically composed of a ceramic base, a layer of photoconductive material. A moisture-proof
enclosure, and metallic leads. Photoconductive cells are also known as photocells or light
dependent resistors (LDRs).
 Another important resistive transducer is the strain gage, whose resistance changes due to
elongation or compression when an external stress is applied. The stress is defined as force per
unit area (newtons/meter^2) and can be related to I pressure, torque, and displacement.
Therefore, a strain gage may be used to monitor change in applied pressure, torque, and
displacement by measuring the corresponding change in the gage’s resistance.
 Two basic types of strain gages are wire and semiconductor. Semiconductor strain gages are
much more sensitive than the wire type and therefore provide better accuracy and resolution. The
sensitivity of a strain gage is defined as unit change in resistance per unit change in length and is
a dimensionless quantity.
 The thermistor, photocell, and strain gage are all passive transducers, meaning that they require
external voltage (ac or dc) for their operation.
 UNIT-III
OP- AMP APPLICATIONS –II
AND
FILTERS
 OP-AMP COMPARATOR
COMPARATOR:

Voltage comparator circuit:

Voltage comparator is a circuit which compares two voltages and switches the output to either high or
low state depending upon which voltage is higher. A voltage comparator based on opamp is shown here.
Fig2.14 shows a voltage comparator in inverting mode and Fig shows a voltage comparator in non
inverting mode.

Fig 1.43 Circuit Diagram of Comparator

Non inverting comparator:

In non inverting comparator the reference voltage is applied to the inverting input and
the voltage to be compared is applied to the non inverting input. Whenever the voltage to be
compared (Vin) goes above the reference voltage , the output of the opamp swings to positive
saturation (V+) and vice versa. Actually what happens is that, the difference between Vin and
Vref, (Vin – Vref) will be a positive value and is amplified to infinity by the opamp. Since
there is no feedback resistor Rf, the opamp is in open loop mode and so the voltage gain (Av)
will be close to infinity. So the output voltage swings to the maximum possible value ie; V+.
Remember the equation Av = 1 + (Rf/R1).

When the Vin goes below Vref, the reverse occurs.

Inverting comparator.

In the case of an inverting comparator, the reference voltage is applied to the non
inverting input and voltage to be compared is applied to the inverting input. Whenever the
input voltage (Vin) goes above the Vref, the output of the op-amp swings to negative
saturation. Here the difference between two voltages (Vin-Vref) is inverted and amplified to
infinity by the op-amp. Remember the equation Av = -Rf/R1. The equation for voltage gain
in the inverting mode is Av = -Rf/R1.Since there is no feedback resistor, the gain will be
close to infinity and the output voltage will be as negative as possible i.e., V-

Practical voltage comparator circuit.

A practical non inverting comparator based on uA741 opamp is shown below. Here
the reference voltage is set using the voltage divider network comprising of R1 and R2. The
equation is Vref = (V+/ (R1 + R2)) x R2. Substituting the values given in the circuit diagram
into this equation gives Vref = 6V. Whenever Vin goes above 6V, the output swings to
~+12V DC and vice versa. The circuit is powered from a +/- 12V DC dual supply.

Fig 1.44 Circuit diagram of Practical voltage comparator.

We know that when the op-amp is used in open-loop configuration any input signal, which even slightly
exceeds zero, drives the output into saturation because of very high open-loop voltage gain of op-amp. It
means that the application of a small differential input signal of appropriate polarity causes the output to
switch to its either saturation. Thus op-amp comparator is a circuit with two inputs and one output. The
two inputs can be compared with each other i.e. one of them can be considered a reference voltage, Vref.
Figure shows an op-amp comparator circuit. A fixed reference voltage Vref is applied to the inverting
input terminal and sinusoidal signal Vin is applied to the non-inverting input terminal. When Vin exceeds
Vref the output voltage goes to positive saturation because the voltage at the inverting input is smaller
than at the non-inverting input. On the other hand, when Vin is less than Vref the output voltage goes to
negative saturation. Thus output voltage Vout changes from one saturation level to another whenever
Vin = Vref ,as illustrated in figure. In short, the comparator is a type of an analog-to-digital converter
(ADC). At any given time the output voltage waveform shows whether Vin is greater or less than Vref.
The comparator is sometimes referred to as a volt-level detector because for a desired value of Vref, the
voltage level of the input voltage Vin can be detected.
Diodes D1 and D2 are provided in the circuit to protect the op-amp against damage due to excessive input
voltage. Because of these diodes, the differential input voltage Vd is clamped to either + 0.7 V or -0.7 V,
hence the diodes are called clamp diodes. There are some op-amps with built-in input protection. Such
op-amps need not to be provided with protection diodes. The resistance R1 in series with Vin is used to
limit the current through protection diodes D1 and D2 while resistance R is connected between the
inverting input terminal and Vref to reduce the offset problem.
When the reference voltage Vref is negative with respect to ground, with a sinusoidal signal applied to
the non-inverting input terminal, the output voltage will be as illustrated in figure. Obviously, the
amplitude of Vin must be large enough to pass through Vref for switching action to take place. Since the
sinusoidal input signal is applied to the non-inverting terminal, this circuit is called the non-inverting
op-amp comparator.

Similarly an inverting op-amp comparator can be had by applying the sinusoidal input to the inverting
input terminal to the op-amp.
Figure shows the circuit for an inverting comparator in which the sinusoidal input signal Vin is applied to
the inverting input terminal while the reference voltage Vref is applied to the non-inverting input
terminal. In this circuit Vref is obtained by the use of a potentiometer forming a potential divider
arrangement with dc supply voltage + Vcc and – VEE. As the wiper connected to non-inverting input
terminal is moved toward + Vcc, Vref becomes more positive, while if it is moved toward – VEE, Vref
becomes more negative.
The input and output waveforms are shown in figures.Comparators are used in circuits such as dis-
criminators, voltage level detectors, oscillators, digital interfacing, Schmitt trigger etc.

Zero Crossing Detector :

Zero-crossing detector is an applied form of comparator. Either of the op-amp basic comparator
circuits discussed can be employed as the zero-crossing detector provided the reference voltage Vref is
made zero. Zero-crossing detector using inverting op-amp comparator is depicted in figure. The output
voltage waveform shown in figure indicates when and in what direction an input signal Vin crosses zero
volt.
SCHMITT TRIGGER:

Below fig shows an inverting comparator with +ve feed back. This circuit converts an
irregular shaped wave forms to a square wave form or pulse. The circuit is known as schmitt
trigger or squaring circuit. The i/p voltage being triggers the o/p Vo every time it exceeds
certain voltage levels called the upper threshold voltage Vut and lower threshold voltage Vlt
as shown in fig 1.45 (b).In fig 1.45 (a) these threshold voltages are obtained by using the
voltage divider R1, R2, where the voltage across R1 is F/B to +ve i/p. The voltage across R1
is a variable reference, threshold voltage that depends on the value and polarity of the output
voltage Vo. when Vo=+Vsat, the voltage across R1 is called the upper threshold voltage Vut.

Fig 1.46 Schmitt Trigger

The input voltage Vin must be slightly more positive then Vut in order to cause the
out put Vo to switch from +Vsat to –Vsat.as long as Vin less then Vut,Vo is at +Vsat. using
the voltage divider rule, On the other hand,when Vo=-Vsat, the voltage across R1 is referred
to as the lower threshold voltage,Vlt.Vin must be slightly more negative than Vlt.in order to
cause Vo to switch from-Vsat to +Vsat.in other words,for Vin values greater than Vlt,Vo is at
– Vsat.Vlt is given by the following equation.
Thus if the threshold voltages Vut and Vlt are made large than the input noise
voltages, the positive fed back will eliminate the false output transitions.Also the +ve
feedback because of its regenerative action will make Vo switch faster between +Vsat and –
Vsat.
SAMPLE AND HOLD CIRCUIT USING OP-AMP
As the name indicates, a sample and hold circuit is a circuit which samples an input signal and holds
onto its last sampled value until the input is sampled again. Sample and hold circuits are commonly used
in analog to digital converts, communication circuits, PWM circuits etc. The circuit shown below is of a
sample and hold circuit using µA741 op-amp , n-channel E- MOSFET and few passive components.

Description:
In the circuit E-MOSFET works as a switch that is controlled by the sample and hold control voltage
Vs .While op-amp µA741 is wired as a voltage follower. The signal to be sampled (Vin) is applied to the
drain of E-MOSFET while the sample and hold control voltage (Vs) is applied to the source of the E-
MOSFET. The source pin of the E-MOSFET is connected to the non-inverting input of the op-amp
through the resistor R3. C1 which is a polyester capacitor serves as the charge storing device. Resistor R2
serves as the load resistor while preset R1 is used for adjusting the offset voltage.
During the positive half cycle of the Vs , the E-MOSFET is ON which acts like a closed switch and the
capacitor C1 is charged by the Vin and the same voltage (Vin) appears at the output of the op-amp. When
Vs is zero E-MOSFET is switched off and the only discharge path for C1 is through the inverting input
of the op-amp. Since the input impedance of the op-amp is too high the voltage Vin is retained and it
appears at the output of the op-amp.
The time periods of the Vs during which the voltage across the capacitor (Vc) is equal to Vin are called
sample periods (Ts) and the time periods of Vs during which the voltage across the capacitor C1 (Vc) is
held constant are called hold periods (Th). Taking a close look at the input and output wave forms of the
circuit will make it easier to understand the working of the circuit.
Circuit diagram:

Input and output waveforms:

PRECISION RECTIFIERS

Half Wave Rectifiers:

If a sinusoid whose peak value is less than the threshold or cut in voltage Vd (0.6V) is applied to the
conventional half-wave rectifier circuit, output will remain zero. In order to be able to rectify small
signals (mV), it is necessary to reduce Vd. By placing a diode in the feedback loop of an OP-AMP, the
cut in voltage is divided by the open loop gain A of the amplifier. Fig. shows an active diode circuit.

Fig. (Positive Half Wave Rectifier)

Hence VD is virtually eliminated and the diode approaches the ideal rectifying element. If the input
Vin goes positive by at least VD/A, then the output voltage Vo=A Vd exceeds VD and D conducts and thus,
provides a negative feedback. Because of the virtual connection between the two inputs VO= Vin-
Vd=Vin- VD / A =͌ Vin.
Therefore, the circuit acts as voltage follower for positive (above 60µV=0.6 / 1*10 5) when Vin swing
negatively, D is OFF and no current is delivered to the external load.

Note: By reversing the diode, the negative half wave rectifier can be made.

Another negative half wave rectifier is shown in fig.

Fig
 If Vin is positive then output of the OPAMP becomes negative inverting .Thus diode
D2 conducts and provides a negative feedback.
 Because of the feedback through D2 a virtual ground exists at the input. Thus diode D1 acts as
open circuit. The output voltage under this condition is given by
Vo = 0.

If Vin goes negative, then output of the OPAMP becomes positive. Thus D1 is conducting and D2 is
off. Thus, the circuit behaves as an inverting amplifier. The output of the circuit is given by

The resultant output voltage will be positive. If Vin is a sinusoid, the circuit performs half wave
rectification. The output does not depend upon the diode forward voltage (Vd). Thus, because of the high
open loop gain of the OP-AMP, the feedback acts to cancel the diode turn-on (forward) voltage. This
leads to improved performance since the diode more closely approximates the ideal device.

Full Wave Rectifier:

The full wave rectifier makes use of two OP-AMPs, as shown in fig.It rectifies the input with a gain of R
/ R1, controllable by one resistor R1.
Fig.

When Vin is positive then V' = negative, D1 is ON and D2 is virtual ground at the input to (Op-Amp1).
Because D2 is non-conducting, and since there is no current in the R which is connected to the non-
inverting input to (Op-Amp2), therefore, V1 =0.

Hence, the system consists of two OP-AMPs in cascade with the gain of A1 equal to (-R / R1) and
the gain of A2 equal to (-R / R) = -1.

The resultant voltage at output is

Vo = (R / R1 ) Vin > 0 (for Vin > 0 voltage output of (Op-Amp1) )

Consider now next half cycle when Vin is negative. The V' is positive D1 is OFF and D2 is ON. Because
of the virtually ground at the input to (Op-Amp2)

V2 = V1 = V

Since the input terminals of (Op-Amp2) are at the same (ground) potential, the current coming to the
inverting terminal of (Op-Amp1) is as indicated in fig.

The output voltage is

Vo = i R + V

where

i = V / 2R (because input impedance of OP-AMP is very high).

The sign of Vo is again positive because Vin is negative in this half cycle. Therefore, outputs during two
half cycles are same and full wave rectified output voltage is obtained also shown in fig
ACTIVE FILTERS

A filter is a frequency selective circuit that passes a specified band of frequencies and blocks or
attenuates signals of frequencies outside this band. Filter may be classified on a number of ways.

1. Analog or digital
2. Passive or active
3. Audio or radio frequency

 Analog filters are designed to process only signals while digital filters process analog signals
using digital technique. Depending on the type of elements used in their consideration, filters
may be classified as passive or active.

 Elements used in passive filters are resistors, capacitors and inductors. Active filters, on the other
hand, employ transistors or Op-Amps, in addition to the resistor and capacitors. Depending upon
the elements the frequency range is decided.

 RC filters are used for audio or low frequency operation. LC filters are employed at RF or high
frequencies.

The most commonly used filters are:

1. Low pass filters

2. High pass filter
3. Band pass filter
4. Band reject filter.
5. All pass filter
  A low pass filter has a constant gain from 0 Hz to a high cutoff frequency fH. Therefore, the
bandwidth is fH. At fH the gain is down by 3db. After that the gain decreases as frequency
increases. The frequency range 0 to fH Hz is called pass band and beyond fH is called stop band.
 Similarly, a high pass filter has a constant gain from very high frequency to a low cutoff
frequency fL. Below fL the gain decreases as frequency decreases. At fL the gain is down by 3db.
The frequency range fL Hz to ∞ (infinity) is called pass band and below fL is called stop band.

 When the filter circuit passes signals that are above one cut-off frequency and below a second
cut-off frequency, it is called a band-pass filter, Thus a band-pass filter has a pass band between
two cut-off frequencies fLand fH where fH > fL . The bandwidth of the band-pass filter is, therefore,
equal to fH – fL where fL and fH are lower and higher cut-off frequencies respectively.
 The band-stop or band-reject filter performs exactly opposite to the band-pass i.e. it has a
band-stop between two cut-off frequencies fH and fL and two pass-bands:
0 < f < fH and f > fL. The ideal response of a band-stop filter is illustrated in fig. This is also
called a band-elimination or notch filter.
 The ideal response of an all-pass filter is shown in fig. This filter passes all frequencies
equally well, i.e., output and input voltages are equal in amplitude for all frequencies. The
important feature of this filter is that it provides predictable phase shift for frequencies of
different input signals.
 The filter discussed above has ideal characteristics and a sharp cut-off but unfortunately, ideal
filter response is not practical because linear networks cannot produce the discontinuities.
However, it is possible to obtain a practical response that approximates the ideal response by
using special design techniques, as well as precision component values and high-speed op-amps.

ACTIVE AND PASSIVE FILTERS – A COMPARISON

 The simplest approach to building a filter is with passive components (resistors,

capacitors, and inductors). In the R-F range it works quite well but with the lower
frequencies, inductors create problems. AF inductors are physically larger and heavier, and
therefore expensive. For lower frequencies the inductance is to be increased which needs
 more turns of wire. It adds to the series resistance which degrades the inductor’s
performance.
 Input and output impedances of passive filters are both a problem, especially below RF.
The input impedance is low, that loads the source, and it varies with the frequency. The
output impedance is usually relatively high, which restricts the load impedance that the
passive filter can drive. There is no isolation between the load impedance and the passive
filter. Thus the load will have to be considered as a component of the filter and will have to
be taken into consideration while determining filter response or design. Any change in load
impedance may significantly alter one or more of the filter response characteristics.
 An active filter uses an amplifier with R-C networks to overcome these problems of
passive filters. Originally built with vacuum tubes and then transistors, active filters now
normally are centered on op-amps. By enclosing a capacitor in a feedback loop, the inductor
(with all its low frequency problems) can be eliminated. By proper configuration input
impedance can be increased. The load is driven from the output of the op-amp, giving very
low output impedance. Not only does this improve load drive capability, but the load is now
isolated from the frequency determining network. Thus variation in load will have no effect
on the characteristics of the active filter.
 The amplifier allows us to specify and easily adjust pass-band gain, pass-band ripple,
cutoff frequency, and initial roll-off. Because of high input impedance of the op-amp, large
value resistors can be used and therefore size and cost of the capacitors used are reduced. By
selecting a quad op-amp IC, steep roll-off can be built in very little space and at very little
cost.
 Active filters also have their limitations. High frequency response is limited by the gain
bandwidth (GBW) and slew-rate of the op-amps. High frequency op-amps are expensive,
making passive filters a more economical choice for RF applications. Active filter needs a
power supply. For op-amps this may be two supplies. Variations in the power supplies output
voltage may affect, to some extent, the signal output from the active filter. In multi-stage
applications, the common power supply provides a bus for high frequency signals. Feedback
along the power supply lines may cause oscillations unless decoupling techniques are
rigorously applied. Active devices, and therefore active filters, are much more susceptible to
RF interference and ionization than are passive R-L-C filters. Practical considerations limit
the Q of the band-pass and notch filters to less than 50. For circuits requiring very selective
(narrow) filtering, a crystal filter, because of its high Q value, will prove to be the best.
 Although active filters are most widely employed in the field of communications and
signal processing, they are used in one form or another in almost all sophisticated electronic
systems. Radio, TV, telephone, RADAR, space-satellites, and biomedical equipment are but
a few systems that make use of active filters.

FIRST ORDER LOW PASS FILTER

Fig. shows a first order low pass Butter-worth filter that uses an RC network for filtering, Op-Amp is
used in non-inverting configuration, R1 and Rf decides the gain of the filter

.
According to voltage divider rule, the voltage at the non-inverting terminal is:
Thus the low pass filter has a nearly constant gain Af from 0 Hz to high cut off frequency fH. At fH the
gain is 0.707 Af and after fH it decreases at a constant rate with an increases in frequency. fH is called
cutoff frequency because the gain of filter at this frequency is reduced by 3dB from 0Hz.

Filter Design:

A low pass filter can be designed using the following steps:

1. Choose a value of high cutoff frequency fH.

2. Select a value of C less than or equal to 1 µF.

3. Calculate the value of R using .

4. Finally, select values of R1 and RF to set the desired gain using .

Example - 1

Design a low pass filter at a cutoff frequency of 1 kH z with a pass band gain of 2.

Solution:

Given fH = 1 kHz. Let C = 0.01 µF.

Therefore, R can be obtained as

A 20 kΩ potentiometer can be used to set the resistance R.

Since the pass band gain is 2, R1 and RF must be equal. Let R1 = R2 = 10 kΩ.

SECOND ORDER LOW-PASS BUTTERWORTH FILTER

A stop-band response having a 40-dB/decade at the cut-off frequency is obtained with the second-order
low-pass filter. A first order low-pass filter can be converted into a second-order low-pass filter by using
an additional RC network as shown in fig.

The gain of the second order filter is set by R 1 and RF, while the high cut-off frequency fH is determined
by R2, C2, R3 and C3 as follows:

Furthermore, for a second-order low pass Butterworth response, the voltage gain magnitude is given by

where,

Except for having the different cut off frequency, the frequency response of the second order low pass
filter is identical to that of the first order type as shown in fig.

Filter Design:

The design steps of the second order filter are identical to those of the first order filter as given bellow:

1. Choose a value of high cutoff frequency fH.

2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C. Then choose a value of C
less than 1 µF.

3. Calculate the value of R using .

4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3) values, the pass band
voltage gain AF has to be equal to 1.586. This gain is necessary to guarantee Butterworth
 response. Therefore, RF = 0.586 R1. Hence choose a value of R1= 100 kΩ and calculate the value
of RF.

First Order High Pass Butterworth filter:

Fig. shows the circuit of first order high pass filter. This is formed by interchanging R and C in low
pass filter.

The lower cut off frequency is fL. This is the frequency at which the magnitude of the gain is 0.707 times
its pass band value. All frequencies higher than fL are pass band frequencies with the highest frequency
determined by the closed loop bandwidth of the OP-AMP.

The magnitude of the gain of the filter

is
HIGHER ORDER FILTERS

 From the discussion made so far on the filters, it may be concluded that in the stop-band the gain
of the filter changes at the rate of 20 db/decade for first-order filters and 40 db/decade for
second-order filters. This means that as the order of the filter is increased, the actual stop-band
response of the filter approaches its ideal stop-band characteristics. In general, a third-order filter
produces 60 db/decade, a fourth-order filter produces 80 db/decade and so on.
 Higher-order filters, such as third, fourth, fifth, and so on, are built simply by using the
first and second-order filters.
 The simplest way to build a third-order low-pass filter is by cascading a first order filter with a
second-order. Similarly a fourth-order low-pass filter can be formed by cascading two second-
order low-pass filters. Although there is no limit to the order of the filter that can be formed, as
the order of the filter increases, so does its size. Also the accuracy declines, in that the difference
between the actual stop-band response and the theoretical stop-band response increases with an
increase in the order of the filter.

A third-order low-pass Butterworth filter is illustrated in figure.

 The voltage-gain of the first section is optional, it can be set, whatever is required. The voltage-
gain of the second section, however affects the flatness of the overall response. If closed-loop
gain is kept 1.586, then the overall gain will be down 6 db (3 db for each section) at the cut-off
frequency. By increasing the voltage gain of the second section slightly, cumulative loss of
voltage gain is offset. By using an advanced mathematical derivation, it can be proved that an Af
, of 2 is the critical value required for a maximally flat response.

In this case Rf = R1

When Af = 2, the cut-off frequency is given as

fH = 1 / 2∏RC
Where R and C are the resistance and capacitance of each section. At cut-off frequency, the overall
voltage gain is down 3 db. Above the cut-off frequency, the voltage gain drops at a rate of 60 db per
decade equivalent to 18 db per octave.

 A fourth-order low-pass Butterworth filter is illustrated in figure. It is formed by cascading

two second-order low-pass filters. If Af , of 1.586 is used for both sections, the voltage gain will
be down 6 db at the cut-off frequency. By using different gain for each section, we can strike a
compromise that produces a maximally flat response. An advanced derivation shows that we
need to use Af = 1.152 for the first section and Af = 2.235 for the second section.
Also, the overall filter gain is equal to the product of the individual voltage gains of the filter sections.
Hence, the overall gain of a fourth-order filter is 1.152 x 2.235 = 2.575.

 In all our Butterworth designs, the cut-off frequency is given as 1 / 2∏RC

As with the first- and second-order filters, the third- and fourth-order high-pass filters are formed by
simply interchanging the positions of the frequency determining resistors and capacitors in the
corresponding low-pass filters. The high-order filters can be designed by following the procedures
outlined for the first- and second-order filters.

 Generally, the minimum-order filter required depends on the application specifications. Although
a high-order filter than necessary provides a better stop-band response, the high-order filter is
more complex, occupies more space and is more expensive.

 It is worth mentioning here that in all filters, the same resistance and capacitance values are used
in the bypass or R-C networks, a definite convenience in selection of components and ease of
construction. This fixes the overall gain of the high-order filters. Furthermore, the 3-db cut-off
frequency is always the same and is equal to 1/2∏RC
BAND PASS FILTER

 A band-pass filter is a circuit which is designed to pass signals only in a certain band of
frequencies while attenuating all signals outside this band. The parameters of importance in a
band-pass filter are the high and low cut-off frequencies (fH and fL), the bandwidth (BW), the
centre frequency fc, centre-frequency gain, and the selectivity or Q.
 There are basically two types of band-pass filters viz wide band-pass and narrow band-pass
filters. Unfortunately, there is no set dividing line between the two. However, a band-pass filter
is defined as a wide band-pass if its figure of merit or quality factor Q < 10 while the band-
pass filters with Q > 10 are called the narrow band-pass filters. Thus Q is a measure of
selectivity, meaning the higher the value of Q the more selective is the filter, or the narrower is
the bandwidth (BW). The relationship between Q, 3-db bandwidth, and the centre frequency fc is
given by an equation
 Q=

For a wide band-pass filter the centre frequency can be defined as fc =

BW= fH - fL

Where fH and fL are respectively the high and low cut-off frequencies in Hz.In a narrow band-pass filter,
the output voltage peaks at the centre frequency fc.

WIDE BANDPASS FILTER

A wide band-pass filter can be formed by simply cascading high-pass and low-pass sections and is
generally the choice for simplicity of design and performance though such a circuit can be realized by a
number of possible circuits. To form a ± 20 db/ decade band-pass filter, a first-order high-pass and first-
order low-pass sections are cascaded; for a ± 40 db/decade band-pass filters, second-order high- pass
filter and a second-order low-pass filter are connected in series, and so on. It means that, the order of the
band-pass filter is governed by the order of the high-pass and low-pass filters it consists of.
A ± 20 db/decade wide band-pass filter composed of a first-order high-pass filter and a first-order low-
pass filter, is illustrated in fig, Its frequency response is illustrated in fig.

A narrow bandpass filter employing multiple feedback is depicted in figure. This filter employs only one
op-amp, as shown in the figure. In comparison to all the filters discussed so far, this filter has some
unique features that are given below.
1. It has two feedback paths, and this is the reason that it is called a multiple-feedback filter.
2. The op-amp is used in the inverting mode.
The frequency response of a narrow bandpass filter is shown in fig(b).
 Generally, the narrow bandpass filter is designed for specific values of centre frequency fc and Q or
fc and BW. The circuit components are determined from the following relationships. For simplification
of design calculations each of C1 and C2 may be taken equal to C.
R1 = Q/2∏ fc CAf
R2 =Q/2∏ fc C(2Q2-Af)
and R3 = Q / ∏ fc C
where Af, is the gain at centre frequency and is given as
Af = R3 / 2R1
The gain Af however must satisfy the condition Af < 2 Q2.
The centre frequency fc of the multiple feedback filter can be changed to a new frequency f c‘ without
changing, the gain or bandwidth. This is achieved simply by changing R2 to R’2 so that
R’2 = R2 [fc/f’c]2
Band Stop Filter:
The band-pass filter passes one set of frequencies while rejecting all others. The band-stop filter does
just the opposite. It rejects a band of frequencies, while passing all others. This is also called a band-
reject or band-elimination filter. Like band-pass filters, band-stop filters
may also be classified as (i) wide-band and (ii) narrow band reject filters.
The narrow band reject filter is also called a notch filter. Because of its higher Q, which exceeds 10, the
bandwidth of the narrow band reject filter is much smaller than that of a wide band reject filter.
Wide Band-Stop (or Reject) Filter:

A wide band-stop filter using a low-pass filter, a high-pass filter and a summing amplifier is shown in
figure. For a proper band reject response, the low cut-off frequency fL of high-pass filter must be larger
than the high cut-off frequency fH of the low-pass filter. In addition, the pass-band gain of both the high-
pass and low-pass sections must be equal.

This is also called a notch filter. It is commonly used for attenuation of a single frequency such as 60
Hz power line frequency hum. The most widely used notch filter is the twin-T network illustrated in
fig. (a). This is a passive filter composed of two T-shaped networks. One T-network is made up of two
resistors and a capacitor, while the other is made of two capacitors and a resistor.One
drawback of above notch filter (passive twin-T network) is that it has relatively low figure of merit Q.
However, Q of the network can be increased significantly if it is used with the voltage follower, as
illustrated in fig. (a). Here the output of the voltage follower is supplied back to the junction of R/2 and
2 C. The frequency response of the active notch filter is shown in fig (b).
Notch filters are most commonly used in communications and biomedical instruments for eliminating
the undesired frequencies.

A mathematical analysis of this circuit shows that it acts as a lead-lag circuit with a phase angle, shown
in fig. (b). Again, there is a frequency fc at which the phase shift is equal to 0°. In fig. (c), the voltage
gain is equal to 1 at low and high frequencies. In between, there is a frequency fc at which voltage gain
drops to zero. Thus such a filter notches out, or blocks frequencies near fc. The frequency at which
maximum attenuation occurs is called the notch-out frequency given by
fn = Fc = 2∏RC
Notice that two upper capacitors are C while the capacitor in the centre of the network is 2C. Similarly,
the two lower resistors are R but the resistor in the centre of the network is 1/2R. This relationship must
always be maintained.

All pass filters:

An all-pass filter is that which passes all frequency components of the input signal without attenuation
but provides predictable phase shifts for different frequencies of the input signals. The all-pass filters are
also called delay equalizers or phase correctors. An all-pass filter with the output lagging behind the
input is illustrated in figure.
The output voltage Vout of the filter circuit shown in fig. (a) can be obtained by using the superposition
theorem
Vout = -Vin +[ -jXC/R-jXC]2Vin
Substituting -jXC = [1/j2∏fc] in the above equation, we have
Vout = Vin [-1 +( 2/ j2∏Rfc)]
or Vout / Vin = 1- j2∏Rfc/1+ j2∏Rfc
where f is the frequency of the input signal in Hz.
From equations given above it is obvious that the amplitude of Vout / Vin is unity, that is |Vout | = |Vin|
throughout the useful frequency range and the phase shift between the input and output voltages is a
function of frequency.
By interchanging the positions of R and C in the circuit shown in fig. (a), the output can be made
leading the input.
These filters are most commonly used in communications. For instance, when signals are transmitted
over transmission lines (such as telephone wires) from one point to another point, they undergo change
in phase. To compensate for such phase changes, all-pass filters are employed.
 UNIT-IV
WAVEFORM GENERATORS
 SCHMITT TRIGGER USING OP-AMP

In some applications the input signal may be low frequency one (i.e. input may be a slowly changing
waveform). In such a case output voltage VOUT may not switch quickly from one saturation state to the
other. Because of the noise at the input terminals of the op-amp, there may be fluctuation in output
voltage between two saturation states (+Vsat and –Vsat voltages). Thus zero crossings may be
detected for noise voltages as well as input signal Vin. Both of these problems can be overcome, if we
use regenerative or positive feeding causing the output voltage Vout to change faster and eliminating the
false output transitions that may be caused due to noise at the input of the op-amp. This can be achieved
using a Schmitt Trigger Circuit.

A Schmitt trigger circuit is a fast-operating voltage-level detector. When the input voltage arrives at the
upper or lower trigger levels, the output changes rapidly. The circuit operates with almost any type of
input waveform, and it gives a pulse-type output.

The circuit of an op-amp Schmitt trigger circuit is shown in figure. The input voltage Vin is applied to
the inverting input terminal and the feedback voltage goes to the non-inverting terminal. This means the
circuit uses positive voltage feedback instead of negative feedback, that is, in this circuit feedback
voltage aids the input voltage rather than opposing it. For instance, assume the inverting input voltage to
be slightly positive. This will produce a negative output voltage. The voltage divider feeds back a
negative voltage to the non-inverting input, which results in a larger negative voltage. This feeds back
more negative voltage until the circuit is driven into negative saturation. If the input voltage is slightly
negative instead of positive, the circuit would be driven into the positive saturation. This is the reason
the circuit is also referred to as regenerative comparator.
When the circuit is positively saturated, a positive voltage is fed back to the non-inverting input. This
positive input holds the output in the high state. Similarly, when the output voltage is negatively
saturated, a negative voltage is fed back to the non-inverting input, holding the output in the low state. In
either case, the positive feedback reinforces the existing output state.
The feedback fraction (β) = R2/R1 + R2
When the output is positively saturated, the reference voltage applied to the non-inverting input is
Vref = + βVsat
When the output is negatively saturated, the reference voltage is
Vref = - βVsat
The output voltage will remain in a given state until the input voltage exceeds the reference voltage for
that state. For instance, if the output is positively saturated, the reference voltage is + βVsat. The input
voltage Vin must be increased slightly above + βVsat to switch the output voltage from positive to
negative, as shown in figure. Once the output is in the negative state, it will remain there indefinitely
until the input voltage becomes more negative than – βVsat. Then the output switches from negative to
positive. This can be explained from the input-output characteristics of the Schmitt trigger shown in
figure.

Characteristics of the Schmitt trigger:

Assume that input voltage Vin is greater than the +βVsat, and output voltage VOUT is at its negative
extreme (point 1). The voltage across R2 in the figure is a negative quantity.
As a result, Vin must be reduced to this negative voltage level (point 2 on the characteristics) before the
output switches positively (point 3). If the input voltage is made more negative than the –βVsat, the
output remains at +VOUT (points 3 to 4). For the output to go negative once again, Vin must be increased
to the +βVsat level (point 5 on the characteristics).
In figure, the trip points are defined as the two input voltages where the output changes states. The upper
trip point (abbreviated UTP) has a value
UTP = β Vsat
and the lower trip point has a value
LTP = – β Vsat
The difference between the trip points is the hysteresis H and is given as
H = + β Vsat – (-β Vsat) = 2 β Vsat
The hysteresis is caused due to positive feedback. If there were no positive feedback, β would equal zero
and the hysteresis would disappear, because the trip points would both equal zero.
Hysteresis is desirable in a Schmitt trigger because it prevents noise form causing false triggering.
To design a Schmitt trigger, potential divider current I2 is once again selected to be very much larger
than the op-amp input bias current. Then the resistor R2 is calculated from equation
R2 = UTP/I2
And R1 is determined from
R1 = (VOUT – UTP) / I2

ASTABLE OR FREE RUNNING MULTI VIBRATOR USING 741 OP-AMP

 The simple op-amp square wave generator is shown in the figure is also called a free running
oscillator the principle of generation of square wave output is to force an op-amp to operate
in the saturation region.
 In figure the feedback fraction (β) = R3/R2 + R3 of the output is fed back to the non-inverting
input terminal. Thus the reference voltage VRef is βVout and may take value as +βVout or -
βVout.
 The output is also fed back to the inverting input terminal after integrating by means of a
low pass RfC combination.
 Whenever input at the inverting input terminal just exceeds V Ref switching takes place
resulting in a square wave output.
 In Astable multi-vibrator both the states are quasi stable.
 Consider an instant of time when the output is at +Vout .
 The comparator now starts charging towards +Vout through resistance Rf as shown in the figure.
 The voltage at the non-inverting input terminal is held at +βVout by R2 and R3 combination, this
condition continues as the charge on C rises until it has just exceeds +βVout, the reference
voltage.
 When the voltage at the inverting input terminal becomes just grater than this reference voltage
the output is driven to –Vout . At this instant the voltage on the capacitor is +βVout. It begins to
discharge through Rf i.e charges towards –Vout.When the output voltage switches to –Vout the
capacitor charges more and more negatively until its voltage just exceeds –βVout. The output
switches back to +Vout. The cycle repeats itself.
 The frequency is determined by, the time taken by the capacitor to charge from –βVout to +βVsat
and vice versa.
The voltage across the capacitor as a function of time is given by
VC(t) =Vf + (Vi-Vf) e-t/RfC
Where Vf = Final Value = +Vout
Vi = Initial Value= - βVout
Therefore VC(t) =Vout + (-βVout-Vout) e-t/RfC
VC(t) =Vout - Vout (1+ β) e-t/RfC
At t=T/2 Voltage across the capacitor reaches +βVout and switching takes place.
Therefore VC (T/2) = βVout= Vout - Vout (1+ β) e-T/2RfC
Vout (1+ β) e-T/2RfC = Vout - βVout
Vout (1+ β) e-T/2RfC = Vout (1- β)
e-T/2RfC = (1- β) / (1+ β)
-T/2RfC = ln{(1- β) / (1+ β)}
T/2RfC = ln{(1+ β) / (1- β)}
T = 2RfC * ln{(1+ β) / (1- β)}
The output wave form is symmetrical
If R2=R3 then β=0.5 and T = 2RfC ln(3) and for R2=1.16R3 it can be seen that
T = 2RfC
Or f0=1/2RfC
The output swings from +Vout to -Vout
So Vo peak to peak = 2Vout

MONOSTABLE OR ONE SHOT MULTI VIBRATOR USING 741 OP-AMP

A mono-stable multi-vibrator (MMV) has one stable state and one quasi-stable state. The circuit
remains in its stable state till an external triggering pulse causes a transition to the quasi-stable state. The
circuit comes back to its stable state after a time period T. Thus it generates a single output pulse in
response to an input pulse and is referred to as a one-shot or single shot.
Mono-stable multi-vibrator circuit illustrated in figure is obtained by modifying the Astable multi-
vibrator circuit by connecting a diode D1 across capacitor C so as to clamp Vc at Vd during positive
excursion.
Under steady-state condition, this circuit will remain in its stable state with the output VOUT = +
VOUT or + Vz and the capacitor C is clamped at the voltage VD (on-voltage of diode VD = 0.7 V). The
voltage VD must be less than βVOUT for Vin < 0. The circuit can be switched to the other state by applying
a negative pulse with amplitude greater than βVOUT – VD to the non-inverting input terminal.
When a trigger pulse with amplitude greater than βVOUT – VD is applied, Vin goes positive causing a
transition in the state of the circuit to -Vout. The capacitor C now charges exponentially with a time
constant τ = RfC toward — VOUT (diode Dl being reverse-biased). When capacitor voltage Vc becomes
more negative than –βVOUT, Vin becomes negative and, therefore, output swings back to +VOUT (steady-
state output). The capacitor now charges towards +VOUT till Vc attain VD and capacitor C becomes
clamped at VD. The trigger pulse, capacitor voltage waveform and output voltage waveform are shown
in figures respectively.
The width of the trigger pulse T must be much smaller than the duration of the output pulse generated
i.e. TP« T. For reliable operation the circuit should not be triggered again before T.

The pulse width T of mono-stable multi-vibrator is calculated as follows.

The general solution for a single time constant low passes RC circuit with Vi and Vf as initial and final
values is

VC(t) =Vf + (Vi-Vf) e-t/RfC

Where Vf =– VOUT and Vi= VD

Vc = – VOUT + (VOUT + VD) e-t/τ

At instant t = T, Vc = – β VOUT and τ = RfC

So - β VOUT =- VOUT + (VOUT + VD) e-T/τ or

T = RfC loge (1 + VD/VOUT)/ 1- β

Usually VD << VOUT and if R2 = R3 so that if β = R3/(R2+R3) = ½

then,
T = RfC loge 2

T= 0.693 Rf C
TRIANGUALR WAVE FORM GENERATOR

 We know that the integrator output waveform will be triangular if the input to it is a
square-wave. It means that a triangular-wave generator can be formed by simply cascading an
integrator and a square-wave generator, as illustrated in figure.
 This circuit needs a dual op-amp, two capacitors, and at least five resistors. The rectangular-wave
output of the square-wave generator drives the integrator which produces a triangular output
waveform. The rectangular-wave swings between +Vsat and -Vsat .
 The triangular-waveform has the same period and frequency as the square-waveform. The
amplitude of the triangular wave form decrease with an increase in its frequency and vice versa.

 The input of integrator A2 is a square wave and its output is a triangular waveform, the output of
integrator will be triangular wave only when R4 C2 > T/ 2 where T is the period of square wave.
 As a general rule, R4C2 should be equal to T. It may also be necessary to shunt the capacitor
C2 with resistance R5 = 10 R4 and connect an offset volt compensating network at the non-
inverting input terminal of op-amp A2 so as to obtain a stable triangular wave. Since the
frequency of the triangular-wave generator like any other oscillator, is limited by the op-amp
slew-rate, a high slew rate op-amp, like LM 301, should be used for the generation of relatively
higher frequency waveforms.

MULTIVIBRATORS:

MONOSTABLE MULTIVIBRATOR:

The monostable multivibrator circuit using op-amp is shown in below

figure1.47(a).The diode D1 is clamping diode connected across C the diode clamps the
capacitor voltage to 0.7volts when the ouput is at +Vsat. A narrow –ve triggering pulse Vt is
applied to the non-inverting input terminal through diode D2.

To understand the operation of the circuit,let us assume that the output Vo is at +Vsat that is
in it‘s stable state. The diode D1 conducts and the voltage across the capacitor C that is Vc
gets clamped to 0.7V.The voltage at the non-inverting input terminal is controlled by
potentiometric divider of R1R2 to βVo that is +βVsat in the stable state.

Figure1.47 Monostable Multivibrator and input-output waveforms (a,b,c,d)

Now if Vt ,a –ve trigger of amplitude Vt is applied to the non-inverting terminal, so

that the effective voltage at this terminal is less than 0.7V than the output of th e op-amp
changes it‘s state from +Vsat to –Vsat.The diode is now reverse biased and the capacitor
starts charging exponentionally to –Vsat through the resistance R. The time constant of this
charging is г= RC.

INTRODUCTION TO 555 TIMER:

One of the most versatile linear integrated circuits is the 555 timer. A sample of these
applications includes mono-stable and astable multivibrators, dc-dc converters, digital logic
probes, waveform generators, analog frequency meters and tachometers, temperature
measurement and control, infrared transmitters, burglar and toxic gas alarms, voltage
regulators, electric eyes, and many others.The 555 is a monolithic timing circuit that can
produce accurate and highly stable time delays or oscillation. The timer basically operates in
one of the two modes: either as monostable (one-shot) multivibrator or as an astable (free
running) multivibrator. The device is available as an 8-pin metal can, an 8-pin mini DIP, or a
14-pin DIP.

The SE555 is designed for the operating temperature range from -55°Cto + 125°C, while the
NE555 operates over a temperature range of 0° to +70°C. The important features of the 555
timer are these: it operates on +5 to + 18 V supply voltage in both free-running (astable) and
one- shot (monostable) modes; it has an adjustable duty cycle; timing is from microseconds
through hours; it has a high current output; it can source or sink 200 mA; the output can drive
TTL and has a temperature stability of 50 parts per million (ppm) per degree Celsius change
in temperature, or equivalently 0.005%/°C.

Like general-purpose op-amps, the 555 timer is reliable, easy to us, and low cost.

Pin 1: Ground.

All voltages are measured with respect to this terminal.

Pin 2: Trigger.

The output of the timer depends on the amplitude of the external trigger pulse applied
to this pin. The output is low if the voltage at this pin is greater than 2/3 VCC. However,when
a negative-going pulse of amplitude larger than 1/3 VCC is applied to this pin, the
comparator 2 output goes low, which in turn switches the output of the timer high. The output
remains high as long as the trigger terminal is held at a low voltage. Pin 3: Output.

There are two ways a load can be connected to the output terminal: either between pin
3 and ground (pin 1) or between pin 3 and supply voltage + VCC (pin 8). When the output is
low, the load current flows through the load connected between pin 3 and + VCC into the
output terminal and is called the sink current.

However, the current through the grounded load is zero when the output is low. For
this reason, the load connected between pin 3 and + VCC is called the normally on load and
that connected between pin 3 and ground is called the normally off load.

On the other hand, when the output is high, the current through the load connected
between pin 3and + VCC (normally on load) is zero. However, the output terminal supplies
current to the normally off load. This current is called the source current. The maximum
value of sink or source current is 200 mA.
 Fig 2.1 Pin diagram of 555Timer

Pin 4: Reset.

The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When
the reset function is not in use, the reset terminal should be connected to + VCC to avoid any
possibility of false triggering.

Fig 2.1(a) Block Diagram

Pin 5: Control voltage.

An external voltage applied to this terminal changes the threshold as well as the
trigger voltage . In other words, by imposing a voltage on this pin or by connecting a pot
between this pin and ground, the pulse width of the output waveform can be varied. When
not used, the control pin should be bypassed to ground with a 0.01-μF capacitor to prevent
any noise problems.

Pin 6: Threshold. This is the non-inverting input terminal of comparator 1, which monitors
the voltage across the external capacitor. When the voltage at this pin is threshold voltage 2/3
V, the output of comparator 1 goes high, which in turn switches the output of the timer low.

Pin 7: Discharge. This pin is connected internally to the collector of transistor Q1, as shown
in Figure 2.1(b). When the output is high, Q1 is off and acts as an open circuit to the external
capacitor C connected across it. On the other hand, when the output is low, Q1 is saturated
and acts as a short circuit, shorting out the external capacitor C to ground.\Pin 8: + VCC.
The supply voltage of +5 V to +18 is applied to this pin with respect to ground (pin

1).

FUNCTIONAL BLOCK DIAGRAM OF 555 TIMER:

Fig 2.1(b) Block Diagram Of Imer The 555 As A Monostable

Multivibrator

A monostable multivibrator, often called a one-shot multivibrator, is a pulse-

generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer.

In a stable or standby state the output of the circuit is approximately zero or at logic-
low level. When an external trigger pulse is applied, the output is forced to go high ( ≈VCC).
The time the output remains high is determined by the external RC network connected to the

timer. At the end of the timing interval, the output automatically reverts back to its logic-low
stable state. The output stays low until the trigger pulse is again applied. Then the cycle
repeats.

The monostable circuit has only one stable state (output low), hence the name mono-stable.
Normally, the output of the mono- stable multivibrator is low. Fig 2.2 (a) shows the 555
configured for monostable operation. To better explain the circuit’s operation, the internal
block diagram is included in Fig 2.2(b).
 Figure 2.2(a) IC555 as monostable multivibrator

Mono-stable operation:

According to Fig 2.2(b), initially when the output is low, that is, the circuit is in a
stable state, transistor Q is on and capacitor C is shorted out to ground. However, upon
application of a negative trigger pulse to pin 2, transistor Q is turned off, which releases the
short circuit across the external capacitor C and drives the output high. The capacitor C now
starts charging up toward Vcc through RA.However, when the voltage across the capacitor
equals 2/3 Va., comparator I ‘s output switches from low to high, which in turn drives the
output to its low state via the output of the flip-flop. At the same time, the output of the flip-
flop turns transistor Q on, and hence capacitor C rapidly discharges through the transistor.
The output of the monostable remains low until a trigger pulse is again applied. Then the
cycle repeats. Figure 4-2(c) shows the trigger input, output voltage, and capacitor voltage
waveforms. As shown here, the pulse width of the trigger input must be smaller than the
expected pulse width of the output waveform. Also, the trigger pulse must be a negative-
going input signal with amplitude larger than 1/3 the time during which the output remains
high is given by where
Fig.2.2 (b) 555 connected as a Monostable Multivibrator (c) input and output waveforms
Where RA is in ohms and C is in farads. Figure 2.2(c) shows a graph of the various

combinations of RA and C necessary to produce desired time delays. Note that this graph can
only be used as a guideline and gives only the approximate value of RA and C for a given
time delay. Once triggered, the circuit’s output will remain in the high state until the set time
1, elapses. The output will not change its state even if an input trigger is applied again during
this time interval T. However, the circuit can be reset during the timing cycle by applying a
negative pulse to the reset terminal. The output will then remain in the low state until a
trigger is again applied.
 Often in practice a decoupling capacitor (10 F) is used between + (pin 8) and ground
(pin 1) to eliminate unwanted voltage spikes in the output waveform. Sometimes, to prevent

any possibility of mistriggering the monostable multivibrator on positive pulse edges, a wave
shapingcircuit consisting of R, C2, and diode D is connected between the trigger input pin 2
and pin 8, as shown in Figure 4-3. The values of R and C2 should be selected so that the time
constant RC2 is smaller than the output pulse width.

Fig.2.3 Monostable Multivibrator with wave shaping network to prevent +ve pulse edge
triggering

Monostable Multivibrator Applications

(a) Frequency divider: The monostable multivibrator of Figure 2.2(a) can be used as a
frequency divider by adjusting the length of the timing cycle tp, with respect to the tine
period T of the trigger input signal applied to pin 2. To use monostable multivibrator as a
divide-by-2 circuit, the timing interval tp must be slightly larger than the time period T of
the trigger input signal, as shown in Figure 2.4. By the same concept, to use the
monostable multivibrator as a divide-by-3 circuit, tp must be slightly larger than twice
the period of the input trigger signal, and so on. The frequency-divider application is
possible because the monostable multivibrator cannot be triggered during the timing
cycle.
Fig 2.4 input and output waveforms of a monostable multi vibrator as a divide-by-2 network

(b) Pulse stretcher: This application makes use of the fact that the output pulse width
(timing interval) of the rnonostable multivibrator is of longer duration than the negative pulse
width of the input trigger. As such, the output pulse width of the monostable multivibrator
can be viewed as a stretched version of the narrow input pulse, hence the name pulse
stretcher. Often, narrow-pulse- width signals are not suitable for driving an LED display,
mainly because of their very narrow pulse widths. In other words, the LED may be flashing
but is not visible to the eye because its on time is infinitesimally small compared to its off
time. The 555 pulse stretcher can be used to remedy this problem

Fig 2.5 Monostable multi vibrator as a Pulse stretcher

Figure 2.5 shows a basic monostable used as a pulse stretcher with an LED indicator
at the output. The LED will be on during the timing interval tp = 1.1RAC, which can be
varied by changing the value of RA and/or C.

THE 555 AS AN ASTABLE MULTIVIBRATOR:

 The 555 as an Astable Multivibrator, often called a free-running multivibrator, is a
rectangular- wave-generating circuit. Unlike the monostable multivibrator, this circuit does
not require an external trigger to change the state of the output, hence the name free running.
However, the time during which the output is either high or low is determined by the two
resistors and a capacitor, which are externally connected to the 555 timer. Fig 4-6(a) shows
the 555 timer connected as an astable multivibrator. Initially, when the output is high,
capacitor C starts charging toward V through RA and R8. However as soon as voltage across
the capacitor equals 2/3 Vcc, comparator I triggers the flip flop, and the output switches low.
Now capacitor C starts discharging through R8 and transistor Q. When the voltage across C
equals 1/3 comparator 2’s output triggers the flip-flop, and the output goes high. Then the
cycle repeats.

Fig 4-6 The 555 as a Astable Multivibrator (a)Circuit(b)Voltage across Capacitor and O/P
waveforms.

The output voltage and capacitor voltage waveforms are shown in Figure 2.6(b). As
shown in this figure, the capacitor is periodically charged and discharged between 2/3 Vcc
and 1/3 V, respectively. The time during which the capacitor charges from 1/3 V to 2/3 V. is
equal to the time the output is high and is given by
where RA and R3 are in ohms and C is in farads. Similarly, the time during which the
capacitor discharges from 2/3 V to 1/3 V is equal to the time the output is low and is given by

where RB is in ohms and C is in farads. Thus the total period of the output waveform is

This, in turn, gives the frequency of oscillation as

Above equation indicates that the frequency fo is independent of the supply voltage V. Often
the term duty cycle is used in conjunction with the astable multivibrator . The duty cycle is
the ratio of the time t during which the output is high to the total time period T. It is generally
expressed as a percentage. In equation form,

Astable Multivibrator Applications:

Square-wave oscillator: Without reducing RA = 0 , the astable multivibrator can be used to

produce a square wave output simply by connecting diode D across resistor RB, as shown in
Figure 4-7. The capacitor C charges through RA and diode D to approximately 2/3 Vcc and
discharges through RB and terminal 7 until the capacitor voltage equals approximately 1/3
Vcc; then the cycle repeats. To obtain a square wave output (50% duty cycle), RA must be a
combination of a fixed resistor and potentiometer so that the potentiorneter can be adjusted
for the exact square wave.
 Fig 2.7 Astable Multivibrator as a Square wave generator Free-running
ramp generator: The astable multivibrator can be used as a free-running ramp generator
when resistors RA and R3 are replaced by a current mirror. Figure 2.8(a) shows an astable
multivibrator configured to perform this function. The current mirror starts charging capacitor
C toward Vcc at a constant rate.

When voltage across C equals 2/3 Vcc, comparator 1 turns transistor Q on, and C
rapidly discharges through transistor Q. However, when the discharge voltage across C is
approximately equal to 1/3 Vcc, comparator 2 switches transistor Q off, and then capacitor C
starts charging up again. Thus the charge— discharge cycle keeps repeating. The discharging
time of the capacitor is relatively negligible compared to its charging time; hence, for all
practical purposes, the time period of the ramp waveform is equal to the charging time and is
approximately given by

Where I = (Vcc — VBE)/R = constant current in amperes and C is in farads. Therefore, the
free running frequency of the ramp generator is
Fig 2.8(a) Free Running ramp generator (b) Output waveform.
SCHMITT TRIGGER:

The below fig 2.9 shows the use of 555 timer as a Schmitt trigger:

Fig 2.9 Timer as Schmitt trigger

The input is given to the pin 2 and pin 6 which are tied together. Pins 4 and 8 are
connected to supply voltage +Vcc. The common point of two pins 2 and 6 are externally
biased at Vcc/2 through the resistance network R1 and R2.Generally R1=R2 to the gate
biasing of Vcc/2.The upper comparator will trip at 2/3Vccwhile lower comparator at
1/3Vcc.The bias provided by R1 and R2 is centered within these two thresholds. Thus when
sine wave of sufficient amplitude, greater than Vcc/6 is applied to the circuit as input, it
causes the internal flip flop to alternately set and reset. Due to this, the circuit produces the
square wave at the output.

PHASE-LOCKED LOOPS

The phase-locked loop principle has been used in applications such as FM (frequency
modulation) stereo decoders, motor speed controls, tracking filters, frequency synthesized
transmitters and receivers, FM demodulators, frequency shift keying (FSK) decoders, and a
generation of local oscillator frequencies in TV and in FM tuners.

Today the phase-locked loop is even available as a single package, typical examples
of which include the Signetics SE/NE 560 series (the 560, 561, 562, 564, 565, and 567).
However, for more economical operation, discrete ICs can be used to construct a phase-
locked loop.

Bloch Schematic and Operating Principle

Figure 2.10 shows the phase-locked loop (PLL) in its basic form. As illustrated in this
figure, the phase-locked loop consists of (1) a phase detector, (2) a low-pass filter, and, (3) a
voltage controlled oscillator

Fig 2.10 Block Diagram of Phase Locked Loop

The phase detectors or comparator compares the input frequency fIN with the
feedback frequency fOUT.. The output voltage of the phase detector is a dc voltage and

therefore is often referred to as the error voltage. The output of the phase is then applied to
the low-pass filter, which removes the high-frequency noise and produces a dc level.

This dc level, in turn, is the input to the voltage-controlled oscillator (VCO). The filter
also helps in establishing the dynamic characteristics of the PLL circuit. The output
frequency of the VCO is directly proportional to the input dc level. The VCO frequency is
compared with the input frequencies and adjusted until it is equal to the input frequencies. In
short, the phase-locked loop goes through three states: free- running, capture, and phase lock.
Before the input is applied, the phase-locked loop is in the free-running state. Once the input
frequency is applied, the VCO frequency starts to change and the phase-locked loop is said to
be in the capture mode. The VCO frequency continues to change until it equals the input
frequency, and the phase- locked loop is then in the phase-locked state. When phase locked,
the loop tracks any change in the input frequency through its repetitive action. Before
studying the specialized phase-locked-loop IC, we shall consider the discrete phase-locked
loop, which may be assembled by combining a phase detector, a low-pass filter, and a
voltage-controlled oscillator.
(a) Phase detector:

The phase detector compares the input frequency and the VCO frequency and
generates a dc voltage that is proportional to the phase difference between the two
frequencies. Depending on the analog or digital phase detector used, the PLL is either called
an analog or digital type, respectively. Even though most of the monolithic PLL integrated
circuits use analog phase detectors, the majority of discrete phase detectors in use are of the
digital type mainly because of its simplicity.

A double-balanced mixer is a classic example of an analog phase detector. On the

other hand,examples of digital phase detectors are these:

1. Exclusive-OR phase detector

2. Edge-triggered phase detector

3. Monolithic phase detector (such as type 4044)

The following fig 2.11 shows Exclusive-OR phase detector:

Fig 2.11 (a) Exclusive-OR phase detector: connection and logic diagram. (b) Input and
output waveforms. (c) Average output voltage versus phase difference between fIN and
fOUT curve.

(b) Low-pass filter.

The function of the low-pass filter is to remove the high-frequency components in the
output of the phase detector and to remove high-frequency noise.
 More important, the 1ow-pass filter controls the dynamic characteristics of the phase-
locked loop. These characteristics include capture and lock ranges, bandwidth, and transient
response. The lock range is defined as the range of frequencies over which the PLL system
follows the changes in the input frequency fIN. An equivalent term for lock range is tracking
range. On the other hand, the capture range is the frequency range in which the PLL acquires
phase lock. Obviously, the capture range is always smaller than the lock range.

(c) Voltage-controlled oscillator:

A third section of the PLL is the voltage-controlled oscillator. The VCO generates an
output frequency that is directly proportional to its input voltage. Typical example of VCO is
Signetics NE/SE 566 VCO, which provides simultaneous square wave and triangular wave
outputs as a function of input voltage. The block diagram of the VCO is shown in Fig 2.12.
The frequency of oscillations is determined by three external R1 and capacitor C1 and the
voltage VC applied to the control terminal 5.

The triangular wave is generated by alternatively charging the external capacitor C1

by one current source and then linearly discharging it by another. The charging and
discharging levels are determined by Schmitt trigger action. The schmitt trigger also provides
square wave output. Both the wave forms are buffered so that the output impedance of each is
50 ohms.

In this arrangement the R1C1 combination determines the free running frequency and
the control voltage VC at pin 5 is set by voltage divider formed with R2 and R3. The initial
voltage VC at pin 5 must be in the range

Where +V is the total supply voltage.The modulating signal is ac coupled with the capacitor
C and must be <3 VPP. The frequency of the output wave forms is approximated by

where R1should be in the range 2KΩ < R1< 20KΩ. For affixed VC and constant C1, the
frequency fO can be varied over a 10:1 frequency range by the choice of R1 between 2KΩ <
R1< 20KΩ.
 Fig 2.12: VCO Block Diagram

MONOLITHIC PHASE LOCK LOOPS IC 565:

Monolithic PLLs are introduced by signetics as SE/NE 560 series and by national
semiconductors LM 560 series.

Fig 2.13 Pin configuration of IC 565

Fig 2.14 Block Diagram of IC 565

 Fig 2.13 and 2.14 shows the pin diagram and block diagram of IC 565 PLL. It
consists of phase detector, amplifier, low pass filter and VCO.As shown in the block diagram
the phase locked feedback loop isnot internally connected. Therefore, it is necessary to
connect output of VCO to the phase comparator input, externally. In frequency multiplication
applications a digital frequency divider is inserted into the loop i.e., between pin 4 and pin 5.
The centre frequency of the PLL is determined by the free-running frequency of the VCO and
it is given by

Where R1 and C1 are an external resistor and capacitor connected to pins 8 and 9,
respectively. The values of R1 and C1 are adjusted such that the free running frequency will
be at the centre of the input frequency range. The values of R1 are restricted from 2 kΩ to 20
kΩ,but a capacitor can have any value. A capacitor C2 connected between pin 7 and the
positive supply forms a first order low pass filter with an internal resistance of 3.6 kΩ. The
value of filter capacitor C2 should be larger enough to eliminate possible demodulated output
voltage at pin 7 in order to stabilize the VCO frequency

The PLL can lock to and track an input signal over typically ±60% bandwidth w.r.t fo
as the center frequency. The lock range fL and the capture range fC of the PLL are given by
the following equations.

Where fo=free running frequency

V=(+V)-(-V)Volts

And

From above equation the lock range increases with an increase in input voltage but decrease
with increase in supply voltage. The two inputs to the phase detector allows direct coupling
of an input signal, provided that there is no dc voltage difference between the pins and the dc
resistances seen from pins 2 and 3 are eq
 UNIT-V

VOLTAGE REGULATORS

AND

DATA CONVERTERS

.
INTRODUCTION TO VOLTAGE REGULATORS:

An unregulated power supply consists of a transformer (step down), a rectifier and a

filter. These power supplies are not good for some applications where constant voltage is
required irrespective of external disturbances. The main disturbances are:

1. As the load current varies, the output voltage also varies because of its poor regulation.

2. The dc output voltage varies directly with ac input supply. The input voltage may vary
over a wide range thus dc voltage also changes.

3. The dc output voltage varies with the temperature if semiconductor devices are used.

An electronic voltage regulator is essentially a controller used along with unregulated

power supply to stabilize the output dc voltage against three major disturbances a. Load
current (IL)

b. Supply voltage (Vi)

c. Temperature (T)

Fig.1.48, shows the basic block diagram of voltage regulator.

where Vi = unregulated dc voltage.

Vo = regulated dc voltage.

Fig.1.48 Block Diagram of voltage regulator

Since the output dc voltage VLo depends on the input unregulated dc voltage Vi, load current
IL and the temperature t, then the change ΔVo in output voltage of a power supply can be
expressed as follows

VO = VO (Vi, IL, T)
Take partial derivative of VO, we get,

SV gives variation in output voltage only due to unregulated dc voltage. RO gives the
output voltage variation only due to load current. ST gives the variation in output voltage
only due to temperature.

The smaller the value of the three coefficients, the better the regulations of power
supply. The input voltage variation is either due to input supply fluctuations or presence of
ripples due to inadequate filtering. A voltage regulator is a device designed to maintain the
output voltage of power supply nearly constant. It can be regarded as a closed loop system
because it monitors the output voltage and generates the control signal to increase or decrease
the supply voltage as necessary to compensate for any change in the output voltage. Thus the
purpose of voltage regulator is to eliminate any output voltage variation that might occur
because of changes in load, changes in supply voltage or changes in temperature.

Zener Voltage Regulator:

The regulated power supply may use zener diode as the voltage controlling device as
shown in fig.1.49. The output voltage is determined by the reverse breakdown voltage of the
zener diode. This is nearly constant for a wide range of currents. The load voltage can
bemaintained constant by controlling the current through zener.

Fig.1.49 Circuit diagram of Zener voltage regulator

 The zener diode regulator has limitations of range. The load current range for which
regulation is maintained, is the difference between maximum allowable zener current and
minimum current required for the zener to operate in breakdown region. For example, if
zener diode requires a minimum current of 10 mA and is limited to a maximum of 1A (to
prevent excessive dissipation), the range is 1 - 0.01 = 0.99A. If the load current variation
exceeds 0.99A, regulation may be lost.

Emitter Follower Regulator:

To obtain better voltage regulation in shunt regulator, the zener diode can be connected to
the base circuit of a power transistor as shown in fig.1.50. This amplifies the zener current
range. It is also known as emitter follower regulation.

Fig. 1.50 Circuit diagram of Emitter follower voltage regulator

This configuration reduces the current flow in the diode. The power transistor used in

this configuration is known as pass transistor. The purpose of CL is to ensure that the

variations in one of the regulated power supply loads will not be fed to other loads. That is,

the capacitor effectively shorts out high-frequency variations. Because of the current

amplifying property of the transistor, the current in the zenor dioide is small. Hence there is

little voltage drop across the diode resistance, and the zener approximates an ideal constant

voltage source.

Operation of the circuit:

The current through resistor R is the sum of zener current IZ and the transistor base
current IB( = IL / β ).
IL = IZ + IB

The output voltage across RL resistance is given by VO = VZ - VBE

Where VBE =0.7 V

Therefore, VO= constant.

The emitter current is same as load current. The current IR is assumed to be constant
for a given supply voltage. Therefore, if IL increases, it needs more base currents, to increase
base current Iz decreases. The difference in this regulator with zener regulator is that in later
case the zener current decreases (increase) by same amount by which the load current
increases (decreases). Thus the current range is less, while in the shunt regulators, if IL
increases by ΔIL then IB should increase by ΔIL / β or IZ should decrease by ΔIL / β.
Therefore the current range control is more for the same rating zener.

IC package should be secured to a heat sink. When this is done, ILoad can increase to
about 1.5 A. We now focus our attention on the 78XX series of regulators. The last two digits
of the IC par number denote the output voltage of the device. Thus, for example, a 7808
ICpackage produces a 8V regulated output. These packages, although internally complex, are
inexpensive and easy to use.

There are a number of different voltages that can be obtained from the 78XX series
1C; they are 5, 6, 8, 8.5, 10, 12, 15, 18, and 24 V. In order to design a regulator around one of
these ICs, we need only select a transformer, diodes, and filter.

FEATURES OF IC 723:

1. Input and output short circuit protection provided.

2. Positive or negative supply operation

3. Good line and load regulation

4. Low temperature drift and high ripple rejection

5. Output voltage can be varied from 2V to 37V

Small in size and hence economic

DATA CONVERTER INTEGRATED CIRCUITS

Fig 2.15: Application of A/D and D/A converters

Fig 2.15 shows the application of A/D and D/A converters. The transducer circuit will
gives an analog signal. This signal is transmitted through the LPF circuit to avoid higher
components, and then the signal is sampled at twice the frequency of the signal to avoid the
overlapping. The output of the sampling circuit is applied to A/D converter where the
samples are converted into binary data i.e. 0’s and 1’s. Like this the analog data converted
into digital data.

The digital data is again reconverted back into analog by doing exact opposite
operation of first half of the diagram. Then the output of the D/A convertor is transmitted
through the smoothing filter to avoid the ripples.

BASIC DAC TECHNIQUES

The input of the block diagram is binary data i.e, 0 and 1,it contain ‘n’ number of
input bits designated as d1,d2,d3,…..dn .this input is combined with the reference voltage

called Vdd to give an analog output.

Where d1 is the MSB bit and dn is the LSB bit Vo=Vdd(d1*2-1+d2*2-

2+d3*2-3+…………………..+dn*2-n)
 Fig .2.16: Basic DAC diagram

Weighted Resistor:

Fig: 2.17 simple 4-bit weighted resistor

Fig. 2.17 shows a simplest circuit of weighted resistor. It uses a summing inverting
amplifier. It contains n- electronic switches (i.e. 4 switches) and these switches are controlled
by binary input bits d1, d2, d3, d4. If the binary input bit is 1 then the switch is connected to
reference voltage –VREF , if the binary input bit is 0 then the switch is connected to ground.
The output current equation is Io=I1+I2+ I3+I 4

Io= VREF (d1*2-1+d2*2-2+d3*2-3+d4*2-4 )

The transfer characteristics are shown below (fig 2.13) for a 3-bit weighted resistor

Fig 2.18 Transfer characteristics of 3-bit weighted resistor

Disadvantages of Weighted resistor D/A converter:

Wide range of resistor’s are required in this circuit and it is very difficult to fabricate
such a wide range of resistance values in monolithic IC. This difficulty can be eliminated
using R-2R ladder network.

R-2R LADDER DAC

Wide range of resistors required in binary weighted resistor type DAC. This can be
avoided by using R-2R ladder type DAC. The circuit of R-2R ladder network is shown in fig
2.19. The basic theory of the R-2R ladder network is that current flowing through any input
resistor (2R) encounters two possible paths at the far end. The effective resistances of both
paths are the same (also 2R), so the incoming current splits equally along both paths. The
half-current that flows back towards lower orders of magnitude does not reach the op amp,
and therefore has no effect on the output voltage. The half that takes the path towards the op
amp along the ladder can affect the output. The inverting input of the op-amp is at virtual
earth. Current flowing in the elements of the ladder network is therefore unaffected by switch
positions.

Fig 2.19: A 4-bit R-2R Ladder DAC

If we label the bits (or inputs) bit 1 to bit N the output voltage caused by connecting a
particular bit to Vr with all other bits grounded is:

Vout = Vr/2N

where N is the bit number. For bit 1, Vout =Vr/2, for bit 2, Vout = Vr/4 etc.

Since an R/2R ladder is a linear circuit, we can apply the principle of superposition to
calculate Vout. The expected output voltage is calculated by summing the effect of all bits
connected to Vr. For example, if bits 1 and 3 are connected to Vr with all other inputs
grounded, the output voltage is calculated by:

Vout = (Vr/2)+(Vr/8) which reduces to Vout = 5Vr/8.

An R/2R ladder of 4 bits would have a full-scale output voltage of 1/2 +1/4 + 1/8 +
1/16 = 15Vr/16 or 0.9375 volts (if Vr=1 volt) while a 10bit R/2R ladder would have a full-
scale output voltage of 0.99902 (if Vr=1 volt).
INVERTED R-2R LADDER DAC

In weighted resistor and R-2R ladder DAC the current flowing through the resistor is
always changed because of the changing input binary bits 0 and 1. More power dissipation
causes heating, which in turn cerates non-linearity in DAC. This problem can be avoided by
using INVERTED R-2R LADDER DAC (fig 2.20) In this MSB and LSB is interchanged.
Here each input binary word connects the corresponding switch either to ground or to the
inverting input terminal of op-amp which isalso at virtual ground. When the input binary in
logic 1 then it is connected to the virtual ground, when input binary is logic 0 then it is
connected to the ground i.e. the current flowing through the resistor is constant.

Fig 2.20: Inverted R-2R ladder

DIFFERENT TYPES OF ADC’S

It provides the function just opposite to that of a DAC. It accepts an analog input voltage Va
and produces an output binary word d1, d2, d3….dn. Where d1 is the most significant bit and

dn is the least significant bit.

ADCs are broadly classified into two groups according to their conversion techniques

1) Direct type

2) Integrating type

Direct type ADCs compares a given analog signal with the internally generated equivalent
signal. This group includes

i) Flash (Comparator) type converter

ii) Successive approximation type convertor

iii) Counter type

iv) Servo or Tracking type

Integrated type ADCs perform conversion in an indirect manner by first changing the analog
input signal to linear function of time or frequency and then to a digital code.

FLASH (COMPARATOR) TYPE CONVERTER:

A direct-conversion ADC or flash ADC has a bank of comparators sampling the input
signal in parallel, each firing for their decoded voltage range. The comparator bank feeds a
logic circuit that generates a code for each voltage range. Direct conversion is very fast,

capable of gigahertz sampling rates, but usually has only 8 bits of resolution or fewer, since
the number of comparators needed, 2N - 1, doubles with each additional bit, requiring a large,
expensive circuit. ADCs of this type have a large die size, a high input capacitance, high
power dissipation, and are prone to produce glitches at the output (by outputting an out-of-
sequence code). Scaling to newer sub-micrometre technologies does not help as the device
mismatch is the dominant design limitation. They are often used for video, wideband
communications or other fast signals in optical storage.

A Flash ADC (also known as a direct conversion ADC) is a type of analog-to-digital

converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to
compare the input voltage to successive reference voltages. Often these reference ladders are
constructed of many resistors; however modern implementations show that capacitive voltage
division is also possible. The output of these comparators is generally fed into a digital
encoder which converts the inputs into a binary value (the collected outputs from the
comparators can be thought of as a unary value).

Also called the parallel A/D converter, this circuit is the simplest to understand. It is
formed of a series of comparators, each one comparing the input signal to a unique reference
voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which
then produces a binary output.
 Fig 2.21: flash (parallel comparator) type ADC

R is a stable reference voltage provided by a precision voltage regulator as part of the

converter circuit, not shown in the schematic. As the analog input voltage exceeds the
reference voltage at each comparator, the comparator outputs will sequentially saturate to a
high state. The priority encoder generates a binary number based on the highest-order active
input, ignoring all other active inputs.

COUNTER TYPE A/D CONVERTER

In the fig 2.22 the counter is reset to zero count by reset pulse. After releasing the
reset pulse the clock pulses are counted by the binary counter. These pulses go through the
AND gate which is enabled by the voltage comparator high output. The number of pulses
counted increase with time.
 Fig 2.22: Countertype A/D converter

The binary word representing this count is used as the input of a D/A converter whose
output is a stair case. The analog output Vd of DAC is compared to the analog input input Va
by the comparator. If Va>Vd the output of the comparator becomes high and the AND gate is
enabled to allow the transmission of the clock pulses to the counter. When Va<Vd the output
of the comparator becomes low and the AND gate is disabled. This stops the counting we can
get the digital data.

SERVO TRACKING A/D CONVERTER :

An improved version of counting ADC is the tracking or servo converter shown in fig
2.23. The circuit consists of an up/down counter with the comparator controlling the direction
of the count.
Fig: 2.23 (a) A tracking A/D converter (b) waveforms associated with a tracking
A/D converter

The analog output of the DAC is Vd and is compared with the analog input
Va. If the input Va is greater than the DAC output signal, the output of the
comparator goes high and the counter is caused to count up. The DAC output
increases with each incoming clock pulse when it becomes more than Va the
counter reverses the direction and counts down.

SUCCESSIVE-APPROXIMATION ADC:

One method of addressing the digital ramp ADC's shortcomings is the so-
called successive- approximation ADC. The only change in this design as shown
in the fig 2.19 is a very special counter circuit known as a successive-
approximation register.

Instead of counting up in binary sequence, this register counts by trying

all values of bits starting with the most-significant bit and finishing at the least-
significant bit. Throughout the count process, the register monitors the
comparator's output to see if the binary count is less than or greater than the
analog signal input, adjusting the bit values accordingly. The way the register
counts is identical to the "trial-and-fit" method of decimal-to-binary conversion,
whereby different values of bits are tried from MSB to LSB to get a binary
number that equals the original decimal number. The advantage to this counting
strategy is much faster results: the DAC output converges on the analog signal
input in much larger steps than with the 0-to-full count sequence of a regular
counter.

Fig: 2.24: Successive approximation ADC circuits

The successive approximation analog to digital converter circuit typically consists

of four chief sub

 A sample and hold circuit to acquire the input voltage (Vin).

 An analog voltage comparator that compares Vin to the output of the

internal DAC and outputs the result of the comparison to the
successive approximation register (SAR).

 A successive approximation register sub circuit designed to supply an

approximate digital code of Vin to the internal DAC.

 An internal reference DAC that supplies the comparator with an analog

voltage equivalent of the digital code output of the SAR for
comparison with Vin.

The successive approximation register is initialized so that the most

significant bit (MSB) is equal to a digital 1. This code is fed into the DAC, which
then supplies the analog equivalent of this digital code (Vref/2) into the
comparator circuit for comparison with the sampled input voltage. If this analog
voltage exceeds Vin the comparator causes the SAR to reset this bit; otherwise,
the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing
this binary search until every bit in the SAR has been tested. The resulting code is
the digital approximation of the sampled input voltage and is finally output by the
DAC at the end of the conversion (EOC).

Mathematically, let Vin = xVref, so x in [-1, 1] is the normalized input voltage.

The objective is to approximately digitize x to an accuracy of 1/2n. The algorithm
proceeds as follows:

 Initial approximation x0 = 0.

 ith approximation xi = xi-1 - s(xi-1 - x)/2i.

where, s(x) is the signum-function(sgn(x)) (+1 for x ≥ 0, -1 for x < 0). It follows
using mathematical induction that |xn - x| ≤ 1/2n.

1. An input voltage source Vin.

2. A reference voltage source Vref to normalize the input.

3. A DAC to convert the ith approximation xi to a voltage.

4. A Comparator to perform the function s(xi - x) by comparing the DAC's

voltage with the input voltage.

5. A Register to store the output of the comparator and apply xi-1 - s(xi-1 - x)/2i.

A successive-approximation ADC uses a comparator to reject ranges of

voltages, eventually settling on a final voltage range. Successive approximation
works by constantly comparing the input voltage to the output of an internal
digital to analog converter (DAC, fed by the current value of the approximation)
until the best approximation is achieved. At each step in this process, a binary
value of the approximation is stored in a successive approximation register (SAR).
The SAR uses a reference voltage (which is the largest signal the ADC is to
convert) for comparisons.

For example if the input voltage is 60 V and the reference voltage is 100
V, in the 1st clock cycle, 60 V is compared to 50 V (the reference, divided by two.
This is the voltage at the output of the internal DAC when the input is a '1'
followed by zeros), and the voltage from the comparator is positive (or '1')
(because 60 V is greater than 50 V). At this point the first binary digit (MSB) is
set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V (being
halfway between 100 and 50 V: This is the output of the internal DAC when its
input is '11' followed by zeros) because 60 V is less than 75 V, the comparator
output is now negative (or '0'). The second binary digit is therefore set to a '0'. In
the 3rd clock cycle, the input voltage is compared with 62.5 V (halfway between
50 V and 75 V: This is the output of the internal DAC when its input is '101'
followed by zeros). The output of the comparator is negative or '0' (because 60 V
is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle
similarly results in the fourth digit being a '1' (60 V is greater than 56.25 V, the
DAC output for '1001' followed by zeros). The result of this would be in the
binary form 1001. This is also called bit-weighting conversion, and is similar to a
binary search.

The analogue value is rounded to the nearest binary value below, meaning
this converter type is mid-rise (see above). Because the approximations are
successive (not simultaneous), the conversion takes one clock-cycle for each bit of
resolution desired. The clock frequency must be equal to the sampling frequency
multiplied by the number of bits of resolution desired. For example, to sample
audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz
would be required. ADCs of this type have good resolutions and quite wide
ranges. They are more complex than some other designs.

DUAL-SLOPE ADC

Fig 2.25 (a): Functional diagram of dual slope ADC

 An integrating ADC (also dual-slope ADC) shown in fig 2.25 (a) applies
the unknown input voltage to the input of an integrator and allows the voltage to
ramp for a fixed time period (the run-up period). Then a known reference voltage
of opposite polarity is applied to the integrator and is allowed to ramp until the
integrator output returns to zero (the run-down period). The input voltage is
computed as a function of the reference voltage, the constant run-up time period,
and the measured run-down time period. The run-down time measurement is
usually made in units of the converter's clock, so longer integration times allow for
higher resolutions. Likewise, the speed of the converter can be improved by
sacrificing resolution. Converters of this type (or variations on the concept) are
used in most digital voltmeters for their linearity and flexibility.

Fig 2.25 (b) o/p waveform of dual slope ADC

In operation the integrator is first zeroed (close SW2), then attached to the
input (SW1 up) for a fixed time M counts of the clock (frequency 1/t). At the end
of that time it is attached to the reference voltage (SW1 down) and the number of
counts N which accumulate before the integrator reaches zero volts output and the
comparator output changes are determined. The waveform of dual slope ADC is
shown in fig 2.25 (b). The equations of operation are therefore:

And
For an integrator,

The voltage Vo will be equal to V1 at the instant t2 and can be written as

The voltage V1 is also given by

So,

Putting the values of and

, we get

Or,

SPECIFICATIONS FOR DAC/ADC

RESOLUTION: The Resolution of a converter is the smallest change in voltage

which may be produced at the output of the converter.

Resolution (in volts)=(VFS)/(2n-1)= 1 LSB increment

Ex: An 8-bit D/A converter have 28-1=255 equal intervals. Hence the smallest
change in output voltage is (1/255) of the full scale output range.

An 8-bit DAC is said to have: 8 bit resolution

1. a resolution of 0.392 of full scale

2. a resolution of 1 part in 255

Similarly the resolution of an A/D converter is defined as the smallest change in

analog input for a one bit change at the output.

Ex: the input range of 8-bit A/D converter is divided into 255 intervals. So the
resolution for a 10V input range is 39.22 mV = (10V/255)

6. LINEARITY: The linearity of an A/D or D/A converter is an important

measure of its accuracy and tells us how close the converter output is to its
ideal characteristics.

7. GLITCHES (PARTICULARLY DAC): In transition from one digital input to the

next, like

0111 to 1000, it may effectively go through 1111 or 0000, which produces

―unexpected‖ voltage briefly. If can cause problems elsewhere.

8. ACCURACY: Absolute accuracy is the maximum deviation between

the actual converter output and the ideal converter output.

9. MONOTONIC: A monotonic DAC is the one whose analog output

increases for an increase in digital input. It is essential in control
applications. If a DAC has to be monotonic, the error should de
lessthan ±(1/2) LSB at each output level.
 10. SETTLING TIME: The most important dynamic parameter is the
settling time. It represents the time it takes for the output to settle
within a specified band ± (1/2) LSB of its final value following a code
change at the input. It depends upon the switching time of the logic
circuitry due to internal parasitic capacitances and inductances. Its
ranges from 100ns to

10μs.

5. STABILITY: The performance of converter changes with temperature,

age and power supply variations. So the stability is required.

UNIT-V

PART-B

ANALOG TO DIGITAL CONVERTER & DIGITAL TO ANALOG CONVERTER

The parallel comparator or Flash ADC:

This is the simplest possible A/D converter .It is at the same time fastest and most expensive
technique.

The circuit consists of a resistive divider network, 8 Op-Amp comparators and a 8 -line to 3-
line encoder (3-bit parity encoder).The comparator and its truth table is as shown in the
table-1. At each node of the resistive divider a comparison voltage is available. Since all the
resistors are of equal value the voltage levels available at the nodes are equally divided
between the reference voltage VR and the ground. The purpose of the circuit is to compare the
analog input voltage Vi with each of the node voltages. The truth table for the flash type ADC
is as shown in the Table-2.The circuit has the advantage of high speed as the conversion
takes place simultaneously rather than sequentially. Typical conversion time is 100 ns or less.

This type of ADC has the advantage that the number of comparators required almost doubles
for each added bit. In general the number of comparators required are 2n-1 where n is the
desired number of bits.

Table-1:
Input Voltage Logic Output

Vi > V n W=1

Vi < V n W=0

Vi = V n W=Previous Value

Table-2:

Input Voltage(Vi) W7 W6 W5 W4 W3 W2 W1 W0 Y2 Y1 Y0

0 to VR/8 0 0 0 0 0 0 0 0 0 0
1

VR/8 to VR/4 0 0 0 0 0 0 1 0 0 1
1

VR/4 to 3VR/8 0 0 0 0 0 1 1 0 1 0
1

3VR/8 to VR/2 0 0 0 0 1 1 1 0 1 1
1
VR/2 to 5VR/8 0 0 0 1 1 1 1 1 0 0
1

5VR/8 to 3VR/4 0 0 1 1 1 1 1 1 1 0
1

3VR/4 to 7VR/8 0 1 1 1 1 1 1 1 1 1 0

7VR/8 to VR 1 1 1 1 1 1 1 1 1 1
1

The Counter type ADC:

The analog input signal (Vi) to be measured is provided at the non-inverting input terminal of
the comparator. After the counter is reset, using “clear” signal, a clock pulse is used to
increment the counter value. On the same time the counter value is served as input for the
DAC and it is converted into an analogue value. This analogue output value is increasing and
is compared at every step with the Vi; when VDAC > Vi, the comparator turns the output off
and the counter value is frozen. The digital output of the counter is exactly the binary
representation of the Vi analogue input which was required for conversion.
Servo Tracking ADC:

It is very similar to the previous model, but it has the advantage that when Vi >VDAC the
counter is incremented and when Vi <VDAC the counter is decremented. This ADC is faster,
since it keeps on tracking the analog signal. Drawback is that its output is not stable. The cost
and complexity are reduced because “clear” signal and the comparator are eliminated.
ual Slope ADC:

Using an analog integrator we can obtain the time integral of the Vi input value:

dVo/dt = Vi/RC
When the circuit is switched on, the output voltage of the integrator ramps up for a T1
period. When this voltage is bigger than Vref the logic will be reverted and the integrator
output will ramp down until 0 and will stop. The idea is to count the number of pulses on T1
ramp-up period and on T2 ramp-down period.

Parameters:

 T1/T2 = periods of ramp-up/down

 N1/N2 = number of pulses on these 2 periods

 Vref = reference voltage

 Vi = N2*(Vref/N1)

Successive Approximation Type Analog to Digital Converter:

A successive approximation A/D converter consists of a comparator, a successive
approximation register (SAR), output latches, and a D/A converter. The circuit diagram is
shown below.

The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A
converter. The analog output Va of the D/A converter is then compared to an analog signal
Vin by the comparator. The output of the comparator is a serial data input to the SAR. Till the
digital output (8 bits) of the SAR is equivalent to the analog input Vin, the SAR adjusts itself.
The 8-bit latch at the end of conversation holds onto the resultant digital data output.
Working
At the start of a conversion cycle, the SAR is reset by making the start signal (S) high. The
MSB of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is
introduced. The output is given to the D/A converter which produces an analog equivalent of
the MSB and is compared with the analog input Vin.
If comparator output is LOW, D/A output will be greater than Vin and the MSB will be
cleared by the SAR.
If comparator output is HIGH, D/A output will be less than Vin and the MSB will be set to
the next position (Q7 to Q6) by the SAR.
According to the comparator output, the SAR will either keep or reset the Q6 bit. This
process goes on until all the bits are tried. After Q0 is tried, the SAR makes the conversion
complete (CC) signal HIGH to show that the parallel output lines contain valid data. The CC
signal in turn enables the latch, and digital data appear at the output of the latch. As the SAR
determines each bit, digital data is also available serially. As shown in the figure above, the
CC signal is connected to the start conversion input in order to convert the cycle
continuously.
Digital to Analog Converters (D/A):

 A D/A Converter is used when the binary output from a digital system is to be
converted into its equivalent analog voltage or current.
 The binary output will be a sequence of 1′s and 0′s. Thus they may be difficult to
follow. But, a D/A converter help the user to interpret easily.
 Basically, a D/A converter have an op-amp. It can be classified into 2 types. They are

 Digital to Analog Converter using Binary-Weighted Resistors:

A D/A converter using binary-weighted resistors is shown in the figure below. In the circuit,
the op-amp is connected in the inverting mode. The op-amp can also be connected in the non-
inverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of
binary inputs is four.

We know that, a 4-bit converter will have 2 4 = 16 combinations of output. Thus, a

corresponding 16 outputs of analog will also be present for the binary inputs.

Four switches from b0 to b3 are available to simulate the binary inputs.

Working
The circuit is basically working as a current to voltage converter.
 If The switch b0 is closed .It will be connected directly to the +5V.
Thus, voltage across R = 5V
Current through R = 5V/10kohm = 0.5mA
Current through feedback resistor, Rf = 0.5mA (Since, Input bias current, IB is negligible)
Thus, output voltage = -(1kohm)*(0.5mA) = -0.5V
 If The switch b1 is closed, b0 is open
R/2 will be connected to the positive supply of the +5V.
Current through R will become twice the value of current (1mA) to flow through Rf.
Thus, output voltage also doubles.
 If b0 and b1 are closed
Current through Rf = 1.5mA
Output voltage = -(1kohm)*(1.5mA) = -1.5V
Thus, according to the position (ON/OFF) of the switches (bo-b3), the corresponding
“binary-weighted” currents will be obtained in the input resistor. The current through Rf will
be the sum of these currents. This overall current is then converted to its proportional output
voltage. Naturally, the output will be maximum if the switches (b0-b3) are closed
V0 = -Rf *([b0/R][b1/(R/2)][b2/(R/4)][b3/(R/8)]) – where each of the inputs b3, b2, b1, and
b0 may either be HIGH (+5V) or LOW (0V).
The graph with the analog outputs versus possible combinations of inputs is shown below.

The output is a negative going staircase waveform with 15 steps of -).5V each. In practice,
due to the variations in the logic HIGH voltage levels, all the steps will not have the same
size. The value of the feedback resistor Rf changes the size of the steps. Thus, a desired size
for a step can be obtained by connecting the appropriate feedback resistor. The only condition
to look out for is that the maximum output voltage should not exceed the saturation levels of
the op-amp. Metal-film resistors are more preferred for obtaining accurate outputs.
Disadvantages

If the number of inputs (>4) or combinations (>16) is more, the binary-weighted resistors
may not be readily available. This is why; R and 2R method is more preferred as it requires
only two sets of precision resistance values.

2. Digital to Analog Converter with R and 2R Resistors

A D/A converter with R and 2R resistors is shown in the figure below. As in the binary-
weighted resistors method, the binary inputs are simulated by the switches (b0-b3), and the
output is proportional to the binary inputs. Binary inputs can be either in the HIGH (+5V) or
LOW (0V) state. Let b3 be the most significant bit and thus is connected to the +5V and all
the other switches are connected to the ground.

Thus, according to Thevenin’s equivalent resistance, RTH,

RTH = [{[(2RII2R + R)} II2R] + R}II2R] + R = 2R = 20kOhms.

The resultant circuit is shown below.

Graph is given below.

In the figure shown above, the negative input is at virtual ground, therefore the current
through RTH=0.

Current through 2R connected to +5V = 5V/20kohm = 0.25 mA

The current will be the same as that in Rf.

Vo = -(20kohm)*(0.25mA) = -5V

Output voltage equation is given below.

V0 = -Rf (b3/2R+b2/4R+b1/8R+b0/16R)
Monolithic/Hybrid Digital to Analog Converters:

The above two digital to analog converters, both of them have been designed for four inputs.
But, if the number of inputs is more than four, the combination of output becomes more than
16. This makes the circuit more complex and the accuracy of the circuit reduces. Therefore,
in critical and complex applications, a monolithic/hybrid D/A converter IC must be used.
With the help of binary-weighted resistor, and R and 2R resistor methods, 8-bit,10-bit, 12-
bit, 14-bit, and 16-bit D/A converters can be designed with a current output, voltage output,
or both current and voltage outputs.

The most commonly used 8-bit D/A converter is MC 1408 which has a current output that
can be converted to a voltage type using a current to voltage converter op-amp. The design
along with the current to voltage converter is shown in the figure below.

V0 = Vref/Rref *(RF)*{D7/2 + D6/4 + D5/8 + D4/16 + D3/32 + D2/64 + D1/128 + D0/256}

SE/NE 5018 is a typical 8-bit D/A converter with voltage output. The figure is shown below.
 In the figure, the SE/NE 5018 circuit is configured for uni-polar output (0V
to 10V). For 12 bits of resolution as well as current and voltage outputs, hybrid D/A
converters such as DATEL DAC-H2 series is used.

For the correct selection of the D/A converter out of the lot, some important specifications of
the converter must be known. They are explained below.
Specifications
 Resolution – It is determined by the number of input bits of the D/A converter. That
is, an 8-bit converter has 28 possible output levels. Thus, its resolution is 1 part in 256. We
can also say that resolution is the value of the LSB.
 Non-linearity or Linearity Error – It is the difference between the actual output of
the DAC and its ideal straight line output. The error is normally expressed as a percentage
of the full-scale range.
 Gain error and Offset Error – The deviations in the feedback resistor of the current
to voltage resistor is the main reason for gain error, while, offset error implies that the
output of the DAC is not zero when the binary inputs are all zero. This error stems from
the input offsets (V and I) of the op-amp as well as of the DAC.
 Settling Time – The time needed for the DAC output to be within +/- 1/2LSB from
zero to full scale input value is called settling time.
Applications
 Microcomputer interfacing, CRT Graphics Generation, Programmable Power
Supplies, Digitally controlled gain circuits, Digital Filters.

ADDITIONAL TOPICS

Power supply design concepts using IC Regulators

 QUESTION BANK

Unit 1

Part A

1. Draw and explain the equivalent circuit of an operational amplifier. Give its features.
2. What is a level translator circuit? Why is it used with cascade differential amplifier
stages?
3. Compare ideal and practical OP-AMP parameters.
4. Define stew rate. Explain its significance and give its typical valve for 741 IC
5. For the circuit shown below compute the output. Assume the OP-AMP is ideal one.

6. List different types of ICs, and what are the three operating temperature rages
7. Explain why open loop configuration of op amp are not used in linear applications
8. Define CMRR and explain the significance of a relatively large value of CMRR
9. For a given opamp CMRR=105 and differential mode gain 105 then determine
common mode gain
10. Define slew rate and what is the significance in applications
11. Pin structure of 741 IC
12. Draw the different differential Amplifiers circuit using BJT
13. What are the features of IC 741?
14. Name the packages available for ICs
15. Draw the circuit diagram of level translator. Explain the operation with suitable
examples
16. Derive the expression for CMRR
17. Write the characteristics of the ideal Op-amp. Write the characteristics and draw the
pin diagram for 741Op-amp
18. Derive slew rate equation and discuss the effect of slew rate in applications of Op-
amp
 19. Design a non-inverting amplifier with a gain of 10. How non-inverting amplifier can
act as voltage follower
20. Draw and explain the equivalent circuit of an operational amplifier. Give its features
21. Define input offset voltage, total output offset voltage and also present the methods of
compensation
22. Explain the term thermal drift.
23. Explain why the frequency compensation is needed in Op-amp’s

Part B

1. Draw the circuit diagram of a dual input balanced output differential amplifier
configuration and perform the DC and AC analysis
2. What are the DC and AC characteristics of an operational amplifier? Explain any one
of them in each category.
3. Explain in detail about AC and DC analysis of dual input, balanced output differential
amplifier
4. What are the DC and AC characteristics of an operational amplifier? Explain any one of them in
each category
5. For an Op-amp PSRR = 60 dB (min), CMRR = 104 and the differential mode gain is 105, the
voltage changes by20 V in 4micro sec. Calculate,
(i) Numerical value of the PSRR
(ii) Common mode gain
(iii) Slew rate.

Unit II – OP Applications I

Part A

1. Discuss how Op-amp is used as comparator. What are the limitations of the Op-amp
as comparators
2. Design an inverting amplifier with the gain of -4.
3. Design a Op-amp free running multivibrator with ON period of 2 m sec and OFF
period of 3 m sec.
4. Draw the circuit of non-inverting amplifier and derive the expression for output
voltage
5. What are the limitations of an ideal integrator and differentiator? How these
limitations are can be overcome?
6. What is a monostable multivibrator
Part B

1. Explain how the op amp works as summer and subtractor

2. Derive the expression of the output voltage of an antilog amplifier using op-amp
3. Design a circuit using Op-amp to generate a output V0 = 0.1 V1 – V2 + 10 V3 where
V1, V2, V3 are input voltages
4. Explain the working of a transconductance amplifier with floating and grounded
loads. Is there any limitation on the size of the load when grounded.
5. Explain how the Op-amp is used as integrator with necessary equations and draw the
input and output waveforms by considering the square wave as input
6. Draw the circuit diagram of an instrumentation amplifier using op-amp with its
operation and derive the necessary expression.
7. Design a circuit using an Op-amp to generate a output V0 = – (0.2V1 + 10 V2 + V3),
where V1, V2, V3 are input Voltages
8. Describe the principle of operating of a precision half wave rectifier with waveforms
9. Draw the circuit and explain the working of
Voltage to current converter and Current to voltage converter.
10. What is an instrumentation amplifier? Explain and derive for output voltage of an
instrumentation amplifier. Mention any three applications of it.
11. Draw the circuit of logarithmic amplifier and mention some of its applications.
12. Explain how Op-amp is used as differentiator with necessary equations. Draw the
input and output waveforms by considering the sine wave as a input
13. What is the voltage at point A and B for the circuit shown in figure below if V1 = 5 V and V2 =
5.1 V?

14. Construct a half wave rectifier using Op-amps and explain the operation using relevant
waveforms
15. With the help of a neat circuit diagram explain the working of a logarithmic amplifier.
16. Draw the circuit of an anti-log amplifier and support with appropriate derivation
17. Draw a sample and hold circuit and explain its operation with necessary input and
output waveforms
18. Construct a full wave rectifier using Op-amp and explain the operation using the
equivalent circuits and waveforms for Vi > 0 and Vi < 0, where Vi is input voltage.
Unit III: OP- Amp Applications-II

Part A

1. Design a second order high pass filter at a cut -off frequency of 1 KHz and plot
the frequency response
2. What are the advantages of active filters over passive filters?
3. Design a first order low-pass butterworth filter with a cutoff frequency of 3 kHz
and passband gain of 3.
4. Design a first order high pass filter at a cut - off frequency of 400 Hz and a pass
band gain of 1 and plot the frequency response.
5. Design a second order active high pass filter with cut-off frequency of 5KHZ and
draw the circuit diagram.
6. What is meant by all-pass filter? Draw the circuit of it.
7. Briefly mention the disadvantages of using zero crossing detectors and how it is
overcome in Schmitt trigger
8. Design a wide band reject filter having fH = 200 Hz, fL = 1 kHz with pass band
gain of 2.
9. Design a second order low-pass butterworth filter at a high cut-off frequency of 2
kHz and write the expression
10. Design a first order high pass filter at cutoff frequency of 500 Hz. And pass band
gain of 5.
11. Distinguish between astable, bistable and monostable multivibrators
12. Explain about the zero crossing detector. How it is used as sine wave to square
converter?
13. Design a HPF at the cutoff frequency of 1 KHz and a pass band gain of 2.
14. Calculate the frequency of oscillation of an IC 566 VCO for external components
RT= 6.8 kΩ, CT = 470 pf. Assume other component values if necessary and draw
the circuit.

Part B

1. Draw and explain the second order low pass Butterworth active filter and also
derive its voltage gain equation.
2. Draw the circuit diagram of a second order low-pass butterworth filter and write
the design steps of such filter
3. Draw the first order low pass Butterworth filter and analyze the same by deriving
the gain and phase angle equation.
4. Describe the characteristics of a first order low-pass butterworth filter and write
the design steps of such filter
5. Draw the Schmitt trigger circuit using OP-AMP and explain its operation.
6. What is an all pass filter? Show that the magnitude response of the all pass filter is
1.
 7. What is hysteresis? Explain the basic operation of a comparator with hysteresis.

8. Explain the operation of regenerative comparator by op amp

9. Discuss about an astable multi - vibrator using an op - amp and derive an expression for
frequency of oscillations.
10. Design and draw the triangular waveform generator using op-amp and explain its
operation

Unit IV: 555 Timer, PLL

Part A

1. For 555 timer astable multivibrator has Ra=4kohm,Rb=8kohm,c=0.1microF .

determine frequency of output
2. What are the two basic modes in which the 555 timer operates, briefly explain the
differences b/w the two modes
3. Draw and explain the functional diagram of a IC 555 timer and explain the
function of “reset” pin.
4. Design a 1 kHz square wave generator using 555 timer for duty cycle, (i) 0.25 (ii)
0.5
5. Design a RAMP generatot using 555 timer having out put freq. 5kHz
6. Draw the pin diagram of IC 555
7. Internal structure of PLL
8. With neat functional block diagram explain the operation of IC 565.
9. Draw the functional block diagram of IC 8038 function generator and explain its
operation.

Part B

1. Draw the circuit of Schmitt trigger using 555 timer and explain its operation

2. Configure a 555 timer as a Schmitt trigger and explain

3. With the help of schematic diagram of 555 timer, explain how it can be used as monostable
multivibrator?
4. Explain the operation of Astable multivibrator using 555 timer.
5. Explain block schematic of PLL and list the applications of PLL.
6. Explain the operation of the PLL with the help of the block diagram
7. Explain how the PLL is used as frequency synthesizer
8. Draw the functional block diagram of IC565 and mention its important features With
the help of neat functional block diagram and waveforms.
9. Explain the operation of IC 555 timer as an astable multivibrator. Derive the
expression for its frequency of oscillation
10. Draw the block schematic of PLL and explain the operation of each block.
11. Explain the operation of monostable multi-vibrator using 555 timer. Derive the
expression of time delay of a monostable multi-vibrator using 555 timer
 12. What is the phase-locked loop? Briefly explain the roles of low-pass filter and VCO
in PLL. Define the terms:lock in range,capture range’ pull in time
13. Explain frequency translation using PLL.
14. Explain the role of a low pass filter in PLL
15. How the PLL is used as AM detector
16. Explain about the free running range, capture range and lock range in PLL with
necessary equations
17. Draw the block diagram of a 565 PLL and explain its salient features. Derive the
expression for lock range
18. Write notes on VCO
19. Explain the application of PLL as a frequency translator
20. Draw the block diagram of a 565 PLL and explain its salient features. Derive the
expression for capture range.
Unit V

Part A

1. Explain briefly about 723 voltage regulator.

2. Explain the current boosting concept in IC 723
3. Find the step size and analog output for 4-bit R-2R ladder DAC when the input is
1000 and 1111. Assume Vref = +5 V
4. If the maximum output voltage of a 7 bit D/A converter is 25.4 V. What is the
smallest change in the output as the binary count increases?
5. What is a priority encoder and explain the operation of 4 to 2 priority encoder with
truth table
6. Define following for ADC 1. Covertion time 2. Percentage resolution.
7. Why integrating type ADCs are preferably used for DC and slow varying signals
8. A 12 - bit D to A converter has a full scale range of 15 volts. Its maximum differential
linearity error is LSB
9. What is the percentage resolution?
10. Determine the resolution of 8 bit adc for max 10v input
11. An 8 bit dac has an output voltage range of 0-2.55v. find its resolution
12. Which is the fastest adc and what is the reason

Part B

1. With neat circuit diagram explain the working principle of IC 723 voltage regulator.
2. Design a voltage regulator to supply 6 volts at a load current of 200 mA using IC723
and explain the current limiting feature of this IC.
3. Explain the working of R-2R ladder type D/A converter
4. Explain the operation of weighted resistor DAC with neat circuit diagram and obtain
the expression for output voltage
 5. A dual slope ADC uses a 16-bit counter and a 4 MHz clock rate. The maximum input
voltage + 10 V. The maximum integrator output voltage should be – 8 V when the
counter has cycled through 2n counts. The capacitor used in the integrator is 0.1 micro
f. Find the value of the resistor R of the integrator. If the analog signal voltages is +
4.129 V, find the equivalent digital number
6. Explain the R-2R digital to analog converter with necessary sketches
7. Explain in detail about the dual - slope A/D converter
8. Compare R-2R ladder and binary weighted resistor type Digital to Analog converters
9. What are ic regulators
10. Explain the operation of series type regulator
11. Explain the working of successive approximation type converter and compare the
conversion times of tracking and successive approximation type ADCs
12. Draw and explain the circuit diagram of dual slope ADC
13. Draw and explain theIC 1408 DAC
14. Write short notes on the following:
a. Successive approximation ADC
b. Instrumentation Amplifier (c) Precision diode
15. The LSB of a 10-bit DAC is 20 m volts.
a. What is its percentage resolution?
b. What is its full-scale range?
(iv) What is the output voltage for an input, 10110 01101?
16. Draw the circuit diagram of a 6 bit inverted R-2R ladder DAC. For V(1) = 5 V, what is
the maximum output voltage. What is the minimum voltage that can be resolved?
17. LSB of 9-bit DAC is represented by 19.6 Volts. If an input of 9 zero bits is
represented by 0 volts,
a. Find the output of the DAC for an input of 10110 1101 and 01101 1011.
b. (ii ) What is the Full Scale Reading (FSR) of this DAC?
18. An 8 bit ADC is capable of accepting an input unipolar (positive values only) voltage 0 to 10 V.
a. What is the minimum value of 1 LSB?
b. What is the digital output code if the applied input voltage is 5.4 V?

Assignment I

1. Define slew rate, CMRR, AC and DC characteristics

2. Derive the gain equation for Inverting, Non Inverting and Difference Amplifiers?
3. Draw the IC 741 pin diagram and mention the features?
4. Draw the circuit diagram of a dual input balanced output differential amplifier
configuration and perform the DC and AC analysis
5. For an Op-amp PSRR = 60 dB (min), CMRR = 104 and the differential mode gain is
105, the voltage changes by20 V in 4micro sec. Calculate,
a. Numerical value of the PSRR
b. Common mode gain
c. Slew rate.
6. For the circuit shown below compute the output. Assume the OP-AMP is ideal one.
 7. Design a circuit using Op-amp to generate a output V0 = 0.1 V1 – V2 + 10 V3 where
V1, V2, V3 are input voltages
8. Explain the working of a transconductance amplifier with floating and grounded
loads. Is there any limitation on the size of the load when grounded?
9. Construct a half wave rectifier using Op-amps and explain the operation using
relevant waveforms
10. Draw a sample and hold circuit and explain its operation with necessary input and
output waveforms

Assignment II

1. What are the advantages of active filters over passive filters?

2. Design a first order low-pass butterworth filter with a cutoff frequency of 3 kHz and
passband gain of 3
3. Calculate the frequency of oscillation of an IC 566 VCO for external components
RT= 6.8 kΩ, CT = 470 pf. Assume other component values if necessary and draw the
circuit.
4. Draw and explain the second order low pass Butterworth active filter and also derive
its voltage gain equation?
5. Draw the Schmitt trigger circuit using OP-AMP and explain its operation.
6. Design and draw the triangular waveform generator using op-amp and explain its
operation
7. Draw the pin diagram of IC 555
8. Design a 1 kHz square wave generator using 555 timer for duty cycle, (i) 0.25 (ii) 0.5
9. For 555 timer astable multivibrator has Ra=4kohm,Rb=8kohm,c=0.1microF .
determine frequency of output
10. With the help of schematic diagram of 555 timer, explain how it can be used as
monostable multivibrator?
11. What is the phase-locked loop? Briefly explain the roles of low-pass filter and VCO
in PLL. Define the terms:lock in range,capture range’ pull in time
12. Explain how the PLL is used as frequency synthesizer
13. Explain the operation of IC 555 timer as an astable multivibrator. Derive the
expression for its frequency of oscillation
Assignment III

13. Explain briefly about 723 voltage regulator.

14. Explain the current boosting concept in IC 723
15. Find the step size and analog output for 4-bit R-2R ladder DAC when the input is
1000 and 1111. Assume Vref = +5 V
16. Define following for ADC 1. Covertion time 2. Percentage resolution.
17. An 8 bit dac has an output voltage range of 0-2.55v. find its resolution
18. Compare R-2R ladder and binary weighted resistor type Digital to Analog converters
19. Design a voltage regulator to supply 6 volts at a load current of 200 mA using IC723
and explain the current limiting feature of this IC.
20. A dual slope ADC uses a 16-bit counter and a 4 MHz clock rate. The maximum input
voltage + 10 V. The maximum integrator output voltage should be – 8 V when the
counter has cycled through 2n counts. The capacitor used in the integrator is 0.1 micro
f. Find the value of the resistor R of the integrator. If the analog signal voltages is +
4.129 V, find the equivalent digital number
21. Draw the circuit diagram of a 6 bit inverted R-2R ladder DAC. For V(1) = 5 V, what
is the maximum output voltage. What is the minimum voltage that can be resolved?
22. LSB of 9-bit DAC is represented by 19.6 Volts. If an input of 9 zero bits is
represented by 0 volts,
a. Find the output of the DAC for an input of 10110 1101 and 01101 1011.
b. (ii ) What is the Full Scale Reading (FSR) of this DAC?

SUGGESTED READING

1. David A. Bell, “Operational Amplifiers and Linear ICs,” 3/e, Oxford Publications, 2011.

2. Roy, Chowdhury D., & Jain, Shail B., “Linear Integrated Circuits,” 4/e, New Age
International Publishers, 2010.

3. Ramakant A. Gayakwad, “Op-Amps and Linear Integrated Circuits,” 4/e, PHI, 2010.

WEBSITES:

1. www.modernelectronics.org
2. www.electronicsforyou.com
3. www.npteliitm.ac.in

WEB SOURCE REFERENCES:

www.nptel.com

STUDENTS LIST
S. No Roll No Name
ECE-A SECTION
1 1608-16-735-001 AJAY KRISHNA
2 1608-16-735-002 MEERA
3 1608-16-735-003 ANIKETH REDDY
4 1608-16-735-004 NAVYA
5 1608-16-735-005 LAXMA REDDY
6 1608-16-735-006 VISHNU KOUNDINYA
7 1608-16-735-007 RAMYA
8 1608-16-735-008 JYOTHI PATNAIK
9 1608-16-735-009 VARUN
10 1608-16-735-010 AMULYA
11 1608-16-735-011 JAIHIND REDDY
12 1608-16-735-012 SWETHA
13 1608-16-735-013 CHARAN SUPRAJ
14 1608-16-735-014 HARSHAVARDHAN REDDY
15 1608-16-735-015 SINDHURA
16 1608-16-735-016 PRANAY KUMAR
17 1608-16-735-017 KARTHIK
18 1608-16-735-018 RAM PRANAV
19 1608-16-735-019 BHAVANI
20 1608-16-735-020 CHANDANA
21 1608-16-735-021 ZAID FARAAZ
22 1608-16-735-022 DEVEESWARA BABU
23 1608-16-735-023 ABHAY SINGH
24 1608-16-735-024 VENKATA MRIGANAINI
25 1608-16-735-025 SONIA
26 1608-16-735-026 VARUN KUMAR
27 1608-16-735-027 MANJU BHARGAVI
28 1608-16-735-028 VIVEK
29 1608-16-735-029 SRIVARSHINI
30 1608-16-735-030 ANIRUDH
31 1608-16-735-031 VINITHA
32 1608-16-735-032 SUSHMA
33 1608-16-735-033 HRUSHIKESH KOUNDINYA
34 1608-16-735-034 ANURADHA
35 1608-16-735-035 LINGESHWARI
36 1608-16-735-036 NIKITHA
37 1608-16-735-037 RUPA
38 1608-16-735-038 SAIKUMAR
39 1608-16-735-039 VARSHITH REDDY
40 1608-16-735-040 SONIKA
41 1608-16-735-041 SOLOMON ROHITH
42 1608-16-735-042 SRAVANI
43 1608-16-735-043 SUMANTH SOURAV
44 1608-16-735-044 HAINDAVI
45 1608-16-735-045 SAI KIRAN
46 1608-16-735-047 RAJITHA
47 1608-16-735-048 SAI KEERTHI
48 1608-16-735-049 NITHIN
49 1608-16-735-050 VINAY
50 1608-16-735-051 SRIRAM
51 1608-16-735-052 SAI GURUNADH
52 1608-16-735-053 RAHUL
53 1608-16-735-054 PHANISH
54 1608-16-735-055 SIDDHARTHA SHANKARA SARMA
55 1608-16-735-056 RENUKA
56 1608-16-735-057 SUDHAMSHU
57 1608-16-735-060 MADHU
58 1608-16-735-301 ANJANEYULU
59 1608-16-735-302 SUNITHA
60 1608-16-735-303 ABDUL RASHEED
61 1608-16-735-304 SHIVDAYAL
62 1608-16-735-305 VINEETH KUMAR
63 1608-16-735-306 ALEKHYA
64 1608-16-735-307 VAISHNAVI
65 1608-16-735-308 NAVYA
66 1608-16-735-309 MOUNIKA YADAV
67 1608-16-735-310 MANISREE
68 1608-16-735-311 NIKHITHA
69 1608-16-735-312 RAMYA
ECE-B SECTION
70 1608-16-735-061 KRITHI
71 1608-16-735-062 MOHAN KRISHNA
72 1608-16-735-063 AMAR SAI
73 1608-16-735-064 ROHITH
74 1608-16-735-065 PRANATHI SAI
75 1608-16-735-066 DUGGIRAJ KIRAN
76 1608-16-735-067 ROHIT SARMA
77 1608-16-735-068 SAI VIKAS
78 1608-16-735-069 SATHWIK
79 1608-16-735-070 ALEKHYA
80 1608-16-735-071 SOUJANYA
81 1608-16-735-072 SAI KISHORE
82 1608-16-735-073 RAKSHITHA
83 1608-16-735-074 SOWMYA
84 1608-16-735-075 SAI NIKHIL
85 1608-16-735-076 CHAKSHU
86 1608-16-735-077 PRAGNA
87 1608-16-735-078 SHIVANI
88 1608-16-735-079 KALYAN KUMAR
89 1608-16-735-080 SAI NIKHIL
90 1608-16-735-081 S N V RAGHU PRANEETH
91 1608-16-735-082 SAI SHRUTHI
92 1608-16-735-083 RAKESH KUMAR
93 1608-16-735-084 SHREYA REDDY
94 1608-16-735-085 SHAILENDRA
95 1608-16-735-086 SHIVANI
96 1608-16-735-087 RATHNA SREE KALKURA
97 1608-16-735-088 TEJASWINI
98 1608-16-735-089 RAJENDER
99 1608-16-735-090 GURU SAI SREE KOUSHIK
100 1608-16-735-091 ASHISH
101 1608-16-735-092 SWETHA
1608-16-735-093 SULEMAN
102 1608-16-735-094 VENKATESH
103 1608-16-735-095 ANIL KUMAR
104 1608-16-735-096 NIKHIL KRISHNA KUMAR
105 1608-16-735-097 ABDUL FAZAL
106 1608-16-735-098 KRISHNA
107 1608-16-735-099 N H SHIVANI
108 1608-16-735-100 MAHINDER NAIK
109 1608-16-735-101 MAHREEN
110 1608-16-735-102 SARIKA
111 1608-16-735-103 RANJITH KUMAR
112 1608-16-735-104 NEEHARIKA
113 1608-16-735-105 SHAKTIDHAR SHARMA
114 1608-16-735-106 SAIDEEP
115 1608-16-735-107 NARENDAR
116 1608-16-735-108 VEDHAS
117 1608-16-735-109 SWATHI
118 1608-16-735-110 CHATHURYA
119 1608-16-735-111 SAI CHAND
120 1608-16-735-112 MAHESHWARI
121 1608-16-735-113 SREE VIDYA
122 1608-16-735-114 NAGA SAI BHARAT
123 1608-16-735-115 ANUSHA
124 1608-16-735-116 NITHIN KUMAR
125 1608-16-735-117 PRAJOTH
126 1608-16-735-118 GAYATHRI
127 1608-16-735-119 RAGHAVENDRA REDDY
128 1608-16-735-313 LAKSHMI BHUVANA
129 1608-16-735-314 PAVAN KUMAR
130 1608-16-735-315 ALEKYA
131 1608-16-735-316 NARESH KUMAR
132 1608-16-735-317 RAMYA
133 1608-16-735-318 SRIKANTH
134 1608-16-735-319 HARSHA VARDHAN
135 1608-16-735-320 MADHURI
136 1608-16-735-321 AKHIL
137 1608-16-735-322 UDAYASRI
138 1608-16-735-323 JYOTSNA
139 1608-16-735-324 SHRAVANI
140 1608-16-735-325 BHANU TEJA

GROUP WISE STUDENT LIST

S. No Roll No Name
GROUP-1
1 1608-16-735-001 AJAY KRISHNA
2 1608-16-735-002 MEERA
3 1608-16-735-003 ANIKETH REDDY
4 1608-16-735-004 NAVYA
5 1608-16-735-005 LAXMA REDDY
6 1608-16-735-006 VISHNU KOUNDINYA
7 1608-16-735-007 RAMYA
8 1608-16-735-008 JYOTHI PATNAIK
GROUP-2
9 1608-16-735-009 VARUN
10 1608-16-735-010 AMULYA
11 1608-16-735-011 JAIHIND REDDY
12 1608-16-735-012 SWETHA
13 1608-16-735-013 CHARAN SUPRAJ
14 1608-16-735-014 HARSHAVARDHAN REDDY
15 1608-16-735-015 SINDHURA
16 1608-16-735-016 PRANAY KUMAR
GROUP-3
17 1608-16-735-017 KARTHIK
18 1608-16-735-018 RAM PRANAV
19 1608-16-735-019 BHAVANI
20 1608-16-735-020 CHANDANA
21 1608-16-735-021 ZAID FARAAZ
22 1608-16-735-022 DEVEESWARA BABU
23 1608-16-735-023 ABHAY SINGH
24 1608-16-735-024 VENKATA MRIGANAINI
GROUP-4
25 1608-16-735-025 SONIA
26 1608-16-735-026 VARUN KUMAR
27 1608-16-735-027 MANJU BHARGAVI
28 1608-16-735-028 VIVEK
29 1608-16-735-029 SRIVARSHINI
30 1608-16-735-030 ANIRUDH
31 1608-16-735-031 VINITHA
32 1608-16-735-032 SUSHMA
GROUP-5
33 1608-16-735-033 HRUSHIKESH KOUNDINYA
34 1608-16-735-034 ANURADHA
35 1608-16-735-035 LINGESHWARI
36 1608-16-735-036 NIKITHA
37 1608-16-735-037 RUPA
38 1608-16-735-038 SAIKUMAR
39 1608-16-735-039 VARSHITH REDDY
40 1608-16-735-040 SONIKA
GROUP-6
41 1608-16-735-041 SOLOMON ROHITH
42 1608-16-735-042 SRAVANI
43 1608-16-735-043 SUMANTH SOURAV
44 1608-16-735-044 HAINDAVI
45 1608-16-735-045 SAI KIRAN
46 1608-16-735-047 RAJITHA
47 1608-16-735-048 SAI KEERTHI
48 1608-16-735-049 NITHIN
49 1608-16-735-050 VINAY
50 1608-16-735-051 SRIRAM
GROUP-7
51 1608-16-735-052 SAI GURUNADH
52 1608-16-735-053 RAHUL
53 1608-16-735-054 PHANISH
54 1608-16-735-055 SIDDHARTHA SHANKARA SARMA
55 1608-16-735-056 RENUKA
56 1608-16-735-057 SUDHAMSHU
57 1608-16-735-060 MADHU
58 1608-16-735-301 ANJANEYULU
59 1608-16-735-302 SUNITHA
60 1608-16-735-303 ABDUL RASHEED
GROUP-8
61 1608-16-735-304 SHIVDAYAL
62 1608-16-735-305 VINEETH KUMAR
63 1608-16-735-306 ALEKHYA
64 1608-16-735-307 VAISHNAVI
65 1608-16-735-308 NAVYA
66 1608-16-735-309 MOUNIKA YADAV
67 1608-16-735-310 MANISREE
68 1608-16-735-311 NIKHITHA
69 1608-16-735-312 RAMYA
ECE –B SECTION
GROUP-1
70 1608-16-735-061 KRITHI
71 1608-16-735-062 MOHAN KRISHNA
72 1608-16-735-063 AMAR SAI
73 1608-16-735-064 ROHITH
74 1608-16-735-065 PRANATHI SAI
75 1608-16-735-066 DUGGIRAJ KIRAN
76 1608-16-735-067 ROHIT SARMA
77 1608-16-735-068 SAI VIKAS
78 1608-16-735-069 SATHWIK
GROUP-2
79 1608-16-735-070 ALEKHYA
80 1608-16-735-071 SOUJANYA
81 1608-16-735-072 SAI KISHORE
82 1608-16-735-073 RAKSHITHA
83 1608-16-735-074 SOWMYA
84 1608-16-735-075 SAI NIKHIL
85 1608-16-735-076 CHAKSHU
86 1608-16-735-077 PRAGNA
87 1608-16-735-078 SHIVANI
GROUP-3
88 1608-16-735-079 KALYAN KUMAR
89 1608-16-735-080 SAI NIKHIL
90 1608-16-735-081 S N V RAGHU PRANEETH
91 1608-16-735-082 SAI SHRUTHI
92 1608-16-735-083 RAKESH KUMAR
93 1608-16-735-084 SHREYA REDDY
94 1608-16-735-085 SHAILENDRA
95 1608-16-735-086 SHIVANI
96 1608-16-735-087 RATHNA SREE KALKURA
GROUP-4
97 1608-16-735-088 TEJASWINI
98 1608-16-735-089 RAJENDER
99 1608-16-735-090 GURU SAI SREE KOUSHIK
100 1608-16-735-091 ASHISH
101 1608-16-735-092 SWETHA
1608-16-735-093 SULEMAN
102 1608-16-735-094 VENKATESH
103 1608-16-735-095 ANIL KUMAR
104 1608-16-735-096 NIKHIL KRISHNA KUMAR
GROUP-5
105 1608-16-735-097 ABDUL FAZAL
106 1608-16-735-098 KRISHNA
107 1608-16-735-099 N H SHIVANI
108 1608-16-735-100 MAHINDER NAIK
109 1608-16-735-101 MAHREEN
110 1608-16-735-102 SARIKA
111 1608-16-735-103 RANJITH KUMAR
112 1608-16-735-104 NEEHARIKA
113 1608-16-735-105 SHAKTIDHAR SHARMA
GROUP-6
114 1608-16-735-106 SAIDEEP
115 1608-16-735-107 NARENDAR
116 1608-16-735-108 VEDHAS
117 1608-16-735-109 SWATHI
118 1608-16-735-110 CHATHURYA
119 1608-16-735-111 SAI CHAND
120 1608-16-735-112 MAHESHWARI
121 1608-16-735-113 SREE VIDYA
122 1608-16-735-114 NAGA SAI BHARAT
GROUP-7
123 1608-16-735-115 ANUSHA
124 1608-16-735-116 NITHIN KUMAR
125 1608-16-735-117 PRAJOTH
126 1608-16-735-118 GAYATHRI
127 1608-16-735-119 RAGHAVENDRA REDDY
128 1608-16-735-313 LAKSHMI BHUVANA
129 1608-16-735-314 PAVAN KUMAR
130 1608-16-735-315 ALEKYA
131 1608-16-735-316 NARESH KUMAR
GROUP-8
132 1608-16-735-317 RAMYA
133 1608-16-735-318 SRIKANTH
134 1608-16-735-319 HARSHA VARDHAN
135 1608-16-735-320 MADHURI
136 1608-16-735-321 AKHIL
137 1608-16-735-322 UDAYASRI
138 1608-16-735-323 JYOTSNA
139 1608-16-735-324 SHRAVANI
140 1608-16-735-325 BHANU TEJA