AKSHAYA INSTITUTE OF TECHNOLOGY

Approved by AICTE, New Delhi, Affiliated to VTU, Belgaum, Recognized by Govt. of Karnataka,

Obalapura Post, Lingapura, Koratagere Road, Tumkur - 572 106, Karnataka

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Module 1 Notes for

“VLSI Design and Testing”
[21EC63]

Prepared by:
Padmavathi N

Associate Professor

Department of ECE.

AKSHAYA INSTITUTE OF TECHNOLOGY

Tumakuru
 VLSI Design and Testing Semester 6
Course Code BEC602 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 4:0:0:0 SEE Marks 50
Total Hours of Pedagogy 50 Hours Total Marks 100
Credits 04 Exam Hours 3 Hours
Examination nature (SEE) Theory
Course objectives:
1.This course deals with analysis and design of digital CMOS integrated circuits.
2.The course emphasizes on basic theory of digital circuits, design principles and techniques for digital
design blocks implemented in CMOS technology.
3.This course will also cover switching characteristics of digital circuits along with delay and power
estimation.
4. Understanding the CMOS sequential circuits and memory design concepts.
5. Explore the knowledge of VLSI Design flow and Testing.

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course
outcomes.
1.Lecture method (L) does not mean only traditional lecture method, but different type of teaching
methods may be adopted to develop the outcomes.
2.Show Video/animation films to explain the different concepts of Digital Signal Processing
3.Encourage collaborative (Group) Learning in the class
4.Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical
thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking
skills such as the ability to evaluate, generalize, and analyse information rather than simply recall it.
6.Topics will be introduced in a multiple representation.
7.Show the different ways to solve the same problem and encourage the students to come up with
their own creative ways to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
9. Adopt Flipped class technique by sharing the materials / Sample Videos prior to the class and have
discussions on the that topic in the succeeding classes.

MODULE-1
Introduction to CMOS Circuits: Introduction, MOS Transistors, MOS Transistor switches, CMOS
Logic, Alternate Circuit representation, CMOS-nMOS comparison.
[Text 1: 1.1,1.2,1.3,1.4,1.5.1.6.]
Teaching-Learning Process: Chalk and talk method, YouTube videos, Power point
presentation RBT Level: L1, L2
MODULE-2
MOS Transistor Theory: n-MOS enhancement transistor, p-MOS transistor, Threshold Voltage,
Threshold voltage adjustment, Body effect, MOS device design equations, V-I characteristics, CMOS
inverter DC characteristics, Influence of βn / βp ratio on transfer characteristics, Noise margin,
Alternate CMOS inverters. Transmission gate DC characteristics. Latch-up in CMOS.
[Text 1: 2.1,2.2,2.3,2.4,2.5.2.6.]
MODULE-3
CMOS Process Technology: Silicon Semiconductor Technology, CMOS Technologies, Layout
Design Rules. [Text 1: 3.1,3.2,3.3.]
Circuit Characterization and Performance Estimation: Introduction, Resistance Estimation,
Capacitance Estimation, Switching Characteristics, CMOS gate transistor sizing, Determination of
conductor size, Power consumption, Charge sharing, Scaling of MOS transistor sizing, Yield.
[Text 1: 4.1,4.2,4.3,4.4,4.5.4.6.4.7,4.8,4.9,4.10]
Teaching-Learning Process:
Chalk and talk method/Power point presentation, YouTube Videos RBT Level: L1, L2, L3.

MODULE-4

CMOS Circuit and Logic Design: Introduction, CMOS Logic structures, CMOS Complementary
logic, Pseudo n-MOS logic, Dynamic CMOS logic, Clocked CMOS Logic, Cascade Voltage Switch
logic, Pass transistor Logic, Electrical and Physical design of Logic gates, The inverter, NAND and
NOR gates, Body effect, Physical Layout of Logic gates, Input output Pads.
[Text 1: 5.1,5.2,5.2.1, , 5.2.2, 5.2.3, 5.2.4, 5.2.6, 5.2.8, 5.3,5.3.1,5.3.2, 5.3.4 ,5.3.8,5.5]
Teaching-Learning Process:
Chalk and talk method, YouTube videos, Power point presentation RBT Level: L1, L2, L3.

MODULE-5
Sequential MOS Logic Circuits: Introduction, Behaviour of Bistable Elements (Excluding
Mathematical analysis) SR Latch Circuit, Clocked Latch and Flip-Flop Circuits, Clocked SR Latch,
Clocked JK Latch.[Text2: 8.1, 8.2, 8.3, 8.4]
Structured Design and Testing: Introduction, Design Styles, Testing[Text1: 6.1, 6.2. 6.5]
Teaching-Learning Process:
Chalk and talk method/Power point presentation RBT Level: L1, L2, L3
Text Books:
1. Principals of CMOS VLSI Design A System approach Neil H E Weste and Kamran
Eshraghain . Addition Wisley Publishing company.
2. “CMOS Digital Integrated Circuits: Analysis and Design”, Sung Mo Kang & Yosuf
Leblebici, Third Edition, Tata McGraw-Hill.
Reference Books:
1. “CMOS VLSI Design- A Circuits and Systems Perspective”, Neil H E Weste, and David
Money Harris 4th Edition, Pearson Education.
2. “Basic VLSI Design”, Douglas A Pucknell, Kamran Eshraghian, 3rd Edition, Prentice Hall of
India publication, 2005
 Course Outcomes: After completing the course, the students will be able to
CO1 Apply the fundamentals of semiconductor physics in MOS transistors and analyze the
geometrical effects of MOS transistors
CO2 Design and realize combinational, sequential digital circuits and memory cells in CMOS
logic.
CO3 Analyze the synchronous timing metrics for sequential designs and structured design basics.
CO4 Understand designing digital blocks with design constraints such as propagation delay
and dynamic power dissipation.
C05 Understand the concepts of Sequential circuits design and VLSI testing