Application Note: SY8370

High Efficiency Fast Response, 11A, 28V Input

Synchronous Step Down Regulator

General Description Features

The SY8370 develops a high efficiency synchronous  Low RDS(ON) for Internal Switches (Top/Bottom):
step-down DC/DC regulator capable of delivering 11A 17/7.5 mΩ
current. The device integrates main switch and  Wide Input Voltage Range: 4~24V
synchronous switch with very low RDS(ON) to minimize  Integrated Bypass Switch: 1.5Ω
the conduction loss. In addition, it operates at pseudo-  Instant PWM Architecture to Achieve Fast
constant frequency of 500kHz under heavy load Transient Responses
conditions to minimize the size of inductor and  Internal Soft-start Limits the Inrush Current
capacitor.  Pseudo-Constant Frequency: 500kHz
 Adjustable Output Voltage Application
Silergy’s proprietary Instant-PWM™ fast-response,
 11A Output Current Capability
constant-on-time (COT) PWM control method supports
 ±1% Internal Reference Voltage
high input/output voltage ratios (low duty cycles), and
fast transient response while maintaining a near  PFM/USM Selectable Light Load Operation
constant operating frequency over line, load and output Mode
voltage ranges. This control method provides stable  Power Good Indicator
operation without complex compensation and even  Output Discharge Function
with low ESR ceramic capacitors.  Cycle-by-cycle Valley and Peak Current Limit
Protection
The SY8370 operates over a wide input voltage range  Programmable Valley Current Limit Threshold
from 4V to 24V. Cycle-by-cycle current limit, input by ILMT Pin
under voltage lock-out, internal soft-start, output under  Latch-off Mode Output Under Voltage Protection
voltage protection, over voltage protection and thermal  Latch-off Mode Output Over Voltage Protection
shutdown provide safe operation in all operating  Latch-off Mode Over Temperature Protection
conditions.  Input UVLO
 RoHS Compliant and Halogen Free
Ordering Information  Compact Package: QFN3×4-13

SY8370 □(□□)□
Temperature Code
Applications
Package Code  LCD-TV/Net-TV/3DTV
Optional Spec Code  Set Top Box
 Notebook
Ordering Number Package type Note  High Power AP
SY8370TMC QFN3×4-13 --  Desk-top

Typical Applications
Efficiency vs. Output Current
(IOUT=0~11A, PFM, L=0.56μH/PCMB104T-R56MT)
100
CIN=10µF×2 CIN=0.1µF
VIN=4~24V IN PG PG (Open Drain Output) 90

80
GND BS
CBS=0.1µF
Efficiency (%)

70
L1=0.56µH VOUT=1.2V
TEST TEST LX 60
(Floating or pull to GND) COUT =22µF×4
SY8370 RFF=1k 50
ON/OFF EN 40 VIN =5V, VOUT=1.2V
CFF=2.2nF R1=100k VIN =12V, VOUT=1.2V
High/Floating/Low ILMT FB 30 VIN =19V, VOUT=1.2V
VIN =24V, VOUT=1.2V
3.3V External Voltage 20
(opt.)
BYP VCC R2=100k 10
0.001 0.01 0.1 1 11
CBYP=1.0µF CVCC=2.2µF
Output Current (A)

Figure1. Schematic Diagram Figure2. Efficiency vs. Output Current

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 SY8370
Pinout (top view)
BS LX GND VCC
13 12 11 10
9 BYP

8 FB

7 ILMT

6 TEST

5 EN
1 2 3 4
IN LX GND PG

(QFN3×4-13)
Top Mark: CURxyz (Device code: CUR, x=year code, y=week code, z= lot number code)

Pin Name Pin Number Pin Description

Input pin. Decouple this pin to the GND pin with at least a 20µF ceramic capacitor.
IN 1
A 0.1μF input ceramic capacitor is recommended to reduce the input noise.
LX 2, 12 Inductor pin. Connect this pin to the switching node of the inductor.
GND 3, 11 Ground pin.
Power good Indicator. Open drain output when the output voltage is within 90% to
PG 4
120% of the regulation point.
Enable control of the DC/DC regulator. Pull this pin high to turn on the regulator. Do
not leave this pin floating.
The pin is also used for controlling operation mode of the regulator under light load
EN 5
condition after the output of buck regulator is within the regulation range. When its
voltage is less than 1.6V, the Buck regulator works under ultra-sonic mode. When its
voltage is larger than 2.2V, the Buck regulator works under PFM mode.
TEST 6 For factory use only. Leave this pin floating or connect it to the GND in application.
ILMT 7 Valley current limit threshold selection pin.
FB 8 Output feedback pin. Connect to the center point of the resistor divider.
External 3.3V bypass power supply input. Decouple this pin to GND with a 1µF
BYP 9
ceramic capacitor. Leave this pin floating or connect it to GND if not used.
Internal 3.3V LDO output. Power supply for internal analog circuits and driving
VCC 10 circuit. This pin cannot support external power supply. Decouple this pin to GND
with a 2.2µF ceramic capacitor.
Boot-strap pin. Supply high side gate driver. Connect a 0.1μF ceramic capacitor
BS 13
between the BS pin and the LX pin.

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 SY8370
Block Diagram
IN

Input
UVLO

Current Sense
PG VCC

TEST Bootstrap
Charge

EN BS

ILMT
Internal
SST PWM LX
OTP Control &
Protection Current Sense
Logic VCC
OVP

UVP
0.6V

FB GND

IN
BYP 3.1V
3.3V LDO VCC

Figure3. Block Diagram

Absolute Maximum Ratings (Note 1)

Supply Input Voltage ------------------------------------------------------------------------------------------------- -0.3V to 28V
IN-LX, LX, PG, TEST, EN Voltage------------------------------------------------------------------------------- -0.3V to 26V
BS-LX, FB, VCC, BYP, ILMT Voltage---------------------------------------------------------------------------- -0.3V to 4V
Maximum Power Dissipation, PD,MAX, @ TA = 25°C QFN3×4-13 ------------------------------------------------------ 3.7W
Package Thermal Resistance (Note 2)
θ JA, QFN3×4-13 ------------------------------------------------------------------------------------------------ 27°C/W
θ JC, QFN3×4-13 ------------------------------------------------------------------------------------------------ 4.3°C/W
Junction Temperature Range ------------------------------------------------------------------------------------ -40°C to 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------------- -65°C to 150°C
Dynamic LX Voltage in 10ns Duration ---------------------------------------------------------------------------- -5V to 29V
Dynamic LX Voltage in 20ns Duration ---------------------------------------------------------------------------- -1V to 28V

Recommended Operating Conditions (Note 3)

Supply Input Voltage ---------------------------------------------------------------------------------------------------- 4V to 24V
Junction Temperature Range ------------------------------------------------------------------------------------ -40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- -40°C to 85°C

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 SY8370
Electrical Characteristics
(VIN= 12V, COUT= 100µF, TA= 25°C, IOUT= 1A unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Voltage Range VIN 4 24 V
Input UVLO Threshold VUVLO VIN rising 3.9 V
UVLO Hysteresis VHYS 0.5 V
IOUT=0A, VBYP=0V,
Quiescent Current IQ 140 µA
VOUT=VSET×105%
Shutdown Current ISHDN EN=0 4 9 µA
Feedback Reference Voltage VREF 0.594 0.600 0.606 V
FB Input Current IFB VFB=1V -50 50 nA
Top FET RDS(ON) RDS(ON)1 17 mΩ
Bottom FET RDS(ON) RDS(ON)2 7.5 mΩ
Output Discharge Current IDIS VOUT=1.2V 40 mA
Top FET Current Limit ILMT,TOP 24 A
ILMT=Low 12.5 A
Bottom FET Current Limit ILMT,BOT ILMT=Floating 15 A
ILMT=High 18 A
Bottom FET Reverse Current Limit ILMT,RVS USM Mode 4 6 A
VOUT from 0% to
Soft-start Time tSS 600 µs
100%VSET
EN Input Voltage High VEN,H 1 V
EN Input Voltage Low VEN,L 0.4 V
EN Voltage for Ultra-sonic Mode VEN,USM 1 1.6 V
EN Voltage for PFM Mode VEN,PFM 2.2 VIN V
ILMT Input Voltage High VILMT,H 2.5 V
ILMT Input Voltage Low VILMT,L 0.5 V
Switching Frequency fSW VOUT=1.2V, CCM 425 500 575 kHz
Ultra-sonic Mode Frequency fUSM USM mode, IOUT=0A 27 kHz
Min ON Time tON,MIN VIN=VIN,MAX 50 ns
Min OFF Time tOFF,MIN 200 ns
VCC Output Voltage VCC VCC adds 1mA load 3.1 3.3 3.5 V
Output Over Voltage Threshold VOVP VFB rising 117 120 123 %VREF
Output Over Voltage Hysteresis VOVP,HYS 5 %VREF
Output OVP Delay tOVP,DLY (Note 4) 30 µs
Output Under Voltage Protection
VUVP 55 60 65 %VREF
Threshold
Output UVP Delay tUVP,DLY (Note 4) 200 µs
Power Good Threshold VPG VFB falling(not good) 80 83 86 %VREF
Power Good Hysteresis VPG,HYS VFB rising (good) 7 %VREF
tPG,R Low to high (Note 4) 200 µs
Power Good Delay
tPG,F High to low (Note 4) 20 µs
Power Good Low Voltage VPG,LOW VFB=0V, IPG=5mA 0.45 V
Bypass Switch RDS(ON) RDS(ON),BYP 1.5 Ω
Bypass Switch Turn-on Voltage VBYP 2.97 3.1 V
Bypass Switch Switchover Hysteresis VBYP,HYS 0.2 V
Bypass Switch OVP Threshold VBYP,OVP 120 %VLDO
Thermal Shutdown Temperature TOTP TJ rising (Note 4) 150 °C
Thermal Shutdown Hysteresis TOTP,HYS (Note 4) 15 °C

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Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note 2: Package thermal resistance is measured in the natural convection at T A = 25°C on a 8.5cm×8.5cm size,
four-layer Silergy Evaluation Board with 2-oz copper.

Note 3: The device is not guaranteed to function outside its operating conditions.

Note 4: Guaranteed by design.

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 SY8370
Typical Performance Characteristics
(TA=25℃, VIN=12V, VOUT=1.2V, L=0.56μH, COUT=88μF, unless otherwise noted)
Efficiency vs. Output Current Efficiency vs. Output Current
(IOUT=0~11A, PFM, L=0.47μH/PCMB104T-R47MS) (IOUT=0~11A, USM, L=0.47μH/PCMB104T-R47MS)
100 100

90 90

80 80
Efficiency (%)

Efficiency (%)
70 70

60 60

50 50

40 VIN =5V, VOUT=1.05V 40 VIN =5V, VOUT=1.05V

VIN =12V, VOUT=1.05V VIN =12V, VOUT=1.05V
30 VIN =19V, VOUT=1.05V 30 VIN =19V, VOUT=1.05V
VIN =24V, VOUT=1.05V VIN =24V, VOUT=1.05V
20 20

10 10
0.001 0.01 0.1 1 11 0.001 0.01 0.1 1 11

Output Current (A) Output Current (A)

Efficiency vs. Output Current Efficiency vs. Output Current

(IOUT=0~11A, PFM, L=0.56μH/PCMB104T-R56MT) (IOUT=0~11A, USM, L=0.56μH/PCMB104T-R56MT)
100 100

90 90

80 80
Efficiency (%)

Efficiency (%)

70 70

60 60

50 50

40 VIN =5V, VOUT=1.2V 40 VIN =5V, VOUT=1.2V

VIN =12V, VOUT=1.2V VIN =12V, VOUT=1.2V
30 VIN =19V, VOUT=1.2V 30 VIN =19V, VOUT=1.2V
VIN =24V, VOUT=1.2V VIN =24V, VOUT=1.2V
20 20

10 10
0.001 0.01 0.1 1 11 0.001 0.01 0.1 1 11

Output Current (A) Output Current (A)

Efficiency vs. Output Current Efficiency vs. Output Current

(IOUT=0~11A, PFM, L=0.68μH/PCMB104T-R68MT) (IOUT=0~11A, USM, L=0.68μH/PCMB104T-R68MT)
100 100

90 90

80 80
Efficiency (%)

Efficiency (%)

70 70

60 60

50 50

40 VIN =5V, VOUT=1.8V 40 VIN =5V, VOUT=1.8V

VIN =12V, VOUT=1.8V VIN =12V, VOUT=1.8V
30 VIN =19V, VOUT=1.8V 30 VIN =19V, VOUT=1.8V
VIN =24V, VOUT=1.8V VIN =24V, VOUT=1.8V
20 20

10 10
0.001 0.01 0.1 1 11 0.001 0.01 0.1 1 11

Output Current (A) Output Current (A)

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 SY8370
Efficiency vs. Output Current Efficiency vs. Output Current
(IOUT=0~11A, PFM, L=1.0μH/PCMB104T-1R0MT) (IOUT=0~11A, USM, L=1.0μH/PCMB104T-1R0MT)
100 100

90 90

80 80
Efficiency (%)

Efficiency (%)
70 70

60 60

50 50

40 VIN =5V, VOUT=2.5V 40 VIN =5V, VOUT=2.5V

VIN =12V, VOUT=2.5V VIN =12V, VOUT=2.5V
30 VIN =19V, VOUT=2.5V 30 VIN =19V, VOUT=2.5V
VIN =24V, VOUT=2.5V VIN =24V, VOUT=2.5V
20 20

10 10
0.001 0.01 0.1 1 11 0.001 0.01 0.1 1 11

Output Current (A) Output Current (A)

Output Ripple Output Ripple

(VIN =12V, VOUT=1.2V, IOUT=0A, PFM) (VIN =12V, VOUT=1.2V, IOUT=0A, USM)

VOUT 20mV/div
VOUT 20mV/div

VLX 10V/div

VLX 10V/div

IL 5A/div
IL 5A/div

Time (4μs/div) Time (20μs/div)

Output Ripple Load Transient

(VIN =12V, VOUT=1.2V, IOUT=11A) (VIN =12V, VOUT=1.2V, IOUT=1.1~11A)

VOUT 20mV/div VOUT 200mV/div

VLX 10V/div

IL 10A/div
IL 10A/div

Time (4μs/div) Time (200µs/div)

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Startup from VIN Shutdown from VIN
(VIN =12V, VOUT=1.2V, IOUT=11A) (VIN =12V, VOUT=1.2V, IOUT=11A)

VIN 10V/div VIN 10V/div

VOUT 1V/div VOUT 1V/div

VLX 10V/div VLX 10V/div

IL 10A/div IL 10A/div

Time (2ms/div) Time (20ms/div)

Startup from EN Shutdown from EN

(VIN =12V, VOUT=1.2V, IOUT=11A) (VIN =12V, VOUT=1.2V, IOUT=11A)

EN 5V/div EN 5V/div

VOUT 1V/div VOUT 1V/div

VLX 10V/div VLX 10V/div

IL 10A/div IL 10A/div

Time (800µs/div) Time (800µs/div)

Short Circuit Protection Short Circuit Protection

(VIN =12V, VOUT=1.2V, IOUT=0A~Short, ILMT=Low) (VIN =12V, VOUT=1.2V, IOUT=11A~Short, ILMT=Low)

VOUT 1V/div VOUT 1V/div

IL 10A/div

IL 10A/div

Time (200µs/div) Time (200µs/div)

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 SY8370
Short Circuit Protection Short Circuit Protection
(VIN =12V, VOUT=1.2V, IOUT=0A~Short, ILMT=Floating) (VIN =12V, VOUT=1.2V, IOUT=11A~Short, ILMT=Floating)

VOUT 1V/div VOUT 1V/div

IL 10A/div

IL 10A/div

Time (200µs/div) Time (200µs/div)

Short Circuit Protection Short Circuit Protection

(VIN =12V, VOUT=1.2V, IOUT=0A~Short, ILMT=High) (VIN =12V, VOUT=1.2V, IOUT=11A~Short, ILMT=High)

VOUT 1V/div VOUT 1V/div

IL 10A/div

IL 10A/div

Time (200µs/div) Time (200µs/div)

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 SY8370
The device can support up to 2.5V maximum output
Detailed Description voltage operation with 60% maximum duty cycle
General Features capability over full temperature range.
Constant-on-time Architecture
Fundamental to any constant-on-time (COT) Instant-PWM Operation
architecture is the one-shot circuit or on-time VIN
L1
VOUT
generator, which determines how long to turn on the
high-side power switch. Each on-time (tON) is a R1
“fixed” period internally calculated to operate the
CIN COUT
step down regulator at the desired switching
frequency considering the input and output voltage R2
ration,
VOUT
t ON  Ramp VRAMP
fSW  VIN
Generator
For example, considering that a hypothetical VFB
converter targets 1.2V output from a 12V input at S
500kHz, the target on-time is Q
PWM R
1.2V
t ON   200ns signal VREF
500kHz 12V tON
Each tON pulse is triggered by the feedback Generator
comparator when the output voltage as measured at Silergy’s instant-PWM control method adds several
FF drops below the target value. After one tON period, proprietary improvements to the traditional COT
a minimum off-time (tOFF,MIN) is imposed before any architecture. Whereas most legacy based on COT
further switching is initiated, even if the output implementations require a dedicated connection to
voltage is less than the target. This approach avoids the output voltage terminal to calculate the tON
the making any switching decisions during the noisy duration, instant-PWM control method derives this
periods just after switching events and while the signal internally. Another improvement optimizes
switching node (LX) is rapidly rising or falling. operation with low ESR ceramic output capacitors. In
many applications it is desirable to utilize very low
In a COT architecture, there is no fixed clock, so the ESR ceramic output capacitors, but legacy COT
high-side power switch can turn on almost regulators may become unstable in these cases
immediately after a load transient and subsequent because the beneficial ramp signal that results from
switching pulses can be quickly initiated, ramping the the inductor current flowing into the output capacitor
inductor current up to meet load requirements with maybe become too small to maintain smooth
minimal delays. Traditional current mode or voltage operation. For this reason, instant-PWM synthesizes
mode control methods must simultaneously monitor a virtual replica of this signal internally. This internal
the feedback voltage, current feedback and internal virtual ramp and the feedback voltage are combined
ramps and compensation signals to determine when and compared to the reference voltage. When the sum
to turn off the high-side power switch and turn on the is lower than the reference voltage, the tON pulse is
low-side synchronous rectifier. Considering these triggered as long as the minimum tOFF has been
small signals in a switching environment are difficult satisfied and the inductor current as measured in the
to be noise-free after switching large currents, low-side synchronous rectifier is lower than the
making those architectures difficult to apply in noisy bottom FET current limit. As the t ON pulse is
environments and at low duty cycles. triggered, the low-side synchronous rectifier turns off
and the high-side power switch turns on. Then the
Minimum Duty Cycle and Maximum Duty Cycle inductor current ramps up linearly during the tON
In the COT architecture, there is no limitation for period. At the conclusion of the tON period, the high-
small duty cycle, since at very low duty cycle side power switch turns off, the low-side
operation, once the on-time is close to the minimum synchronous rectifier turns on and the inductor
on time, the switching frequency can be reduced as current ramps down linearly. This action also initiates
needed to always ensure a proper operation. the minimum tOFF timer to ensure sufficient time for
stabilizing any transient conditions and settling the
feedback comparator before the next cycle is
initiated. This minimum tOFF is relatively short so that

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 SY8370
during high speed load transient tON can be flow and transients during startup. The startup and
retriggered with minimal delay, allowing the inductor shutdown sequence is shown below.
current to ramp quickly to provide sufficient energy
to the load side. VUVLO
VIN

In order to avoid shoot-through, a dead time (tDEAD) is

EN
generated internally between the high-side power tDLY1
switch off and the low-side synchronous rectifier on VCC 50µs
tDLY2
period or the low-side synchronous rectifier off and 120µs
the high-side power switch on period. VREF
VSS(internal signal)

Input Under Voltage Lock-out (UVLO)

VPG+VPG,HYS VPG
To prevent operation before all internal circuitry is VFB VUVP
ready and to ensure that the power and synchronous tSS

rectifier switches can be sufficiently enhanced, the

instant-PWM incorporates one input under-voltage VOUT
tPG,R
tPG,F
lockout protections. The device remains in a low
current state and all switching actions are inhibited PG
until VIN exceeds their own UVLO (rising) threshold.
At that time, if EN is enabled, the device will start-up
by initiating a soft-start ramp. If VIN falls below After the input voltage exceeds its own UVLO
VUVLO less than the input UVLO hysteresis, (rising) threshold, VCC is turned on after EN is
switching actions will again be suppressed. enabled for one delay time tDLY1, the buck regulator
is turned on after another delay time tDLY2 after VCC
If the input UVLO threshold is low for some high voltage is set up. When the output voltage is 90% of
input UVLO threshold requirement applications, use the regulation point, PG becomes high-impedance
EN to adjust the input UVLO by adopting two after one delay time tPG,R.
external divided resistors.
VIN
If the output is pre-biased to a certain voltage before
IN
start-up, the device disables the switching of both the
RH high-side power switch and the low-side synchronous
EN rectifier until the voltage on the internal soft start
RL circuit voltage VSS exceeds the sensed output voltage
GND at the FB node.

Enable Control Light Load Operation Mode Selection

The EN input is a high-voltage capable input with PFM or USM light load operation is selected by EN
logic-compatible threshold. When EN is driven above pin. EN is not only Buck enable pin but also mode
1V normal device operation will be enabled. When selection pin to control operation mode of the
driven < 0.4V the device will be shut down, reducing regulator under light load condition after the output
input current to < 10µA. of Buck regulator is within the regulation range. If
the voltage on this pin is lower than 1.6V and higher
It is not recommended to connect EN and IN directly. than its rising threshold, the Buck regulator works
A resistor in a range of 1kΩ to 1MΩ should be used under ultra-sonic mode (USM). If the voltage on this
if EN is pulled high by IN. pin is greater than 2.2V, the Buck regulator works
under pulse-frequency modulation mode (PFM).
Startup and Shutdown
The SY8370 incorporates an internal soft-start circuit If PFM light load operation is selected, under light
to smoothly ramp the output to the desired voltage load conditions, typically IOUT < 1/2×ΔIL, the current
whenever the device is enabled. Internally, the soft- through the low-side synchronous rectifier will ramp
start circuit clamps the output at a low voltage and to near zero before the next tON time. When this
then allows the output to rise to the desired voltage occurs, the low-side synchronous rectifier turns off,
over approximately 0.4ms, which avoids high current preventing recirculation current that can seriously
reduce efficiency under these light load conditions.
As load current is further reduced, and the combined

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 SY8370
feedback and ramp signals remain much greater than PG should be connected to VIN or another voltage
the reference voltage, the instant-PWM control loop source through a resistor (e.g. 100kΩ). After V IN
will not trigger another tON until needed, so the exceeds its own UVLO (rising) threshold, the PG
apparent operating switching frequency will FET is turned on so that PG is pulled to GND before
correspondingly drop, further enhancing efficiency. output voltage is ready. After feedback voltage V FB
The switching frequency can be lower than audible reaches VPG+VPG,HYS, PG is pulled high (after one
frequency area under deep light load or null load delay time typical 200µs). When VFB drops to VPG, or
conditions. Continuous conduction mode (CCM) rises to VOVP for one OVP delay time, PG is pulled
resumes smoothly as soon as the load current low (after one delay time typical 20µs).
increases sufficiently for the inductor current to
remain above zero at the time of the next tON cycle. External Bootstrap Capacitor Connection
The device enters CCM once the load current This device integrates a floating power supply for the
exceeds the critical level. After that, the switching gate driver that operates the high-side power switch.
frequency stays fairly constant over the output Proper operation requires a 0.1µF low ESR ceramic
current range. The critical level of the load current is capacitor to be connected between BS and LX. This
determined with bootstrap capacitor provides the gate driver supply
IL VOUT  (1  D) voltage for the high-side N-channel MOSFET power
IOUT_CTL  
2 2  fSW  L1 switch.
BS

If USM light load operation is selected, it keeps the CBS

0.1µF
switching frequency above an audible frequency area
even under deep light load or null load conditions. LX
Once the device detects that both the high-side power
switch and the low-side synchronous rectifier turn off
for more than one certain time, it forces the low-side
synchronous rectifier turn on in advance of one tON VCC Linear Regulator
cycle and discharge the output capacitor electric SY8370 integrates one high performance, low drop-
quantity so that the switching frequency is out of out linear regulator 3.3V VCC, which can power the
audio range. There is also one feedback loop to internal gate drivers, PWM logic, analog circuitry
match the low-side synchronous rectifier forced turn and other blocks. VCC is supplied by IN voltage.
on time with the error amplifier output voltage to Connect a 2.2µF low ESR ceramic capacitor from
avoid output voltage becoming too high. VCC to GND. VCC can not support external power
supply because of its current limit.
Output Discharge VCC
SY8370 discharges the output voltage when the CVCC
converter shuts down from VIN or EN, or thermal 2.2µF
shutdown, so that output voltage can be discharged in
a minimal time, even load current is zero. The
discharge FET in parallel with the low-side BYP Input
synchronous rectifier turns on after the low-side The control and drive circuit can also be powered by
synchronous rectifier turns off when shut down logic external 3.3V power supply. When a 3.3V external
is triggered. The output discharge current is typically power supply is connected to the BYP pin, the VCC
40mA. Note that the discharge FET is not active LDO is turned off and the switch between BYP and
beyond these shutdown conditions. VCC is turned on. The overall efficiency may be
improved by connecting the BYP pin to external
Buck Output Power Good Indicator 3.3V switching power supply. Connect a 1.0µF low
The Buck power good indicator is an open drain ESR ceramic capacitor from BYP pin to GND when
output controlled by a window comparator connected BYP is supplied by 3.3V external power. Make one
to the feedback signal. If VFB is greater than good RC filter circuit between the supply source and
VPG+VPG,HYS and less than VOVP for at least the power the BYP pin if the power supply is not one ideal DC
good delay time (low to high), PG will be high- source. Leave this pin floating or connect it to GND
impedance. if not used.

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 SY8370
Fault Protection Modes the monitored current exceeds the top FET current
Output Current Limit limit, the high-side power switch is turned off, the
Instant-PWM incorporates a cycle-by-cycle low-side synchronous rectifier is turned on and then
“valley” current limit. Inductor current is measured tON is inhibited. tON can be not inhibited any more
in the low-side synchronous rectifier when it turns once low-side synchronous rectifier current is lower
on and as the inductor current ramps down. If the than the bottom FET current limit value.
current exceeds the bottom FET current limit
threshold, tON is inhibited until the current returns
back to the limit threshold or lower. Output Under Voltage Protection (UVP)
Bottom FET current limit If VFB < ~60% of the reference voltage for
approximately 200µs occurring when the output short
IL
circuit or the load current is heavier than the
VFB
maximum current capacity, the output under voltage
protection (UVP) will be triggered, and the device
VREF
will latch off. Recycling EN input to re-enable the
device.
VLX
Output Short Circuit

tON is inhibited until IL is

VFB<VREF VUVP
lower than I LMT,BOT VFB

The device supports programmable valley current Bottom FET

current limit
limit threshold. Pull ILMT pin low, floating or high
for 3 gears successively increasing valley current IL
limit threshold. When the valley current limit occurs,
the output current limit value is
Vss(internal signal)
I
ILMT,OUT  ILMT,BOT  L
2 UVP delay time
VOUT  (VIN  VOUT )
Here, IL 
VIN  fSW  L1
Output Over Voltage Protection (OVP)
This device includes Buck output over voltage
Table1: Programmable Valley Current Limit
protection (OVP). If the output voltage rises above
ILMT Gears ILMT,BOT Recommended Table the feedback regulation level, the high-side power
Pull ILMT to GND by
ILMT=Low ≥12.5A switch naturally remains off and different actions are
≤10kΩ Resistor adopted in different operation mode.
ILMT=Floating ≥15A ILMT pin floating
Pull ILMT to VCC by When operating in PFM light load mode, if the
ILMT=High ≥18A
≤10kΩ Resistor output voltage remains high, the low-side
synchronous rectifier remains on until the inductor
The over current limit protection limits the inductor current reaches zero and the switching actions are
current but the OCP itself is one non-latch protection. suppressed. If the output voltage doesn’t exceed over
When the load current is higher than the bottom FET voltage protection threshold, the switching actions
current limit threshold by one half of the peak-to- will be recovered once the combined feedback and
peak inductor ripple current, the output voltage starts ramp signals become lower than the reference
to drop. Once the feedback voltage falls lower than voltage. If the feedback voltage exceeds over voltage
the under voltage protection (UVP) threshold and protection threshold and lingers for one OVP delay
continues for one UVP delay time, the device will time, the output over voltage protection (OVP) will
UVP latch off. On the other hand, over temperature be triggered, and the device will latch off. Recycling
protection may also be triggered under an over EN input to re-enable the device.
current condition and the device will OTP latch off.
When operating in USM light load mode, if the
The device also features cycle-by-cycle “peak” output voltage remains high, the low-side
current limit (top FET current limit). During tON time, synchronous rectifier forced turn on time will be
the high-side power switch current is monitored. If longer and inductor current average value becomes

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 SY8370
more and more negative until the reverse current drawn from the input supply and to reduce potential
limit is triggered, trying to make output voltage EMI. When selecting an input capacitor, be sure to
lower. If the output voltage continues to rise and select a voltage rating at least 20% greater than the
feedback voltage exceeds the output over voltage maximum voltage of the input supply and a
threshold for more than OVP delay time, the output temperature rating above the system requirements.
over voltage protection (OVP) will be triggered, and X5R series ceramic capacitors are most often selected
the device will latch off. Recycling EN input to re- due to their small size, low cost, surge current
enable the device. False OVP may happen under capability and high RMS current ratings over a wide
USM light load condition if the inductance is chosen temperature and voltage range. However, systems
too small and reverse current limit is triggered. that are powered by a wall adapter or other long and
therefore inductive cabling may be susceptible to
Over Temperature Protection (OTP) significant inductive ringing at the input to the
Instant-PWM includes Buck over temperature device. In these cases, consider adding some bulk
protection (OTP) circuitry to prevent overheating due capacitance like electrolytic, tantalum or polymer
to excessive power dissipation. When the Buck type capacitors. Using a combination of bulk
thermal sensor detects the Buck junction temperature capacitors (to reduce overshoot or ringing) in parallel
exceeds 150°C, the over temperature protection with ceramic capacitors (to meet the RMS current
(OTP) will be triggered, and the device will latch off requirements) is helpful in these cases.
(LDO output voltage is still alive). Recycling EN
input to re-enable the device after the junction Consider the RMS current rating of the input
temperature cools down about 15°C. capacitor, paralleling additional capacitors if required
TOTP to meet the calculated RMS ripple current,
ICIN_RMS =IOUT  D （1  D）
TOTP-TOTP,HYS

TJ
The worst-case condition occurs at D = 0.5, then
IOUT
EN
ICIN_RMS,MAX =
2
Vss(internal signal) For simplification, choose an input capacitor with an
VREF
RMS current rating greater than half of the maximum
VOUT
load current.

On the other hand, the input capacitor value

Design Procedure determines the input voltage ripple of the converter.
Feedback Resistor Selection If there is an input voltage ripple requirement in the
Choose R1 and R2 to program the proper output system, choose an appropriate input capacitor that
voltage. To minimize the power consumption under meets the specification.
light loads, it is desirable to choose large resistance Given the very low ESR and ESL of ceramic
values for both R1 and R2. A value of between 10kΩ capacitors, the input voltage ripple can be estimated
and 1MΩ is strongly recommended for both resistors. by
If VSET is 1.2V, R1=100kΩ is chosen, then using the IOUT
VCIN_RIPPLE,CAP =  D  (1-D)
following equation, R2 can be calculated to be 100kΩ. fSW  CIN
The worst-case condition occurs at D = 0.5, then
0.6V
R2 =  R1 VCIN_RIPPLE,CAP,MAX =
IOUT
VSET -0.6V 4  fSW  CIN
VOUT The capacitance value is less important than the RMS
R1 current rating. In most applications two 10µF X5R
FB
capacitors are sufficient. Take care to locate the
R2 ceramic input capacitor as close to the device IN and
GND GND pin as possible.

Buck Inductor Selection

The inductor is necessary to supply constant current
Buck Input Capacitor Selection to the output load while being driven by the switched
Input filter capacitors are needed to reduce the ripple input voltage.
voltage on the input, to filter the switched current

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 SY8370
Instant-PWM operates well over a wide range of 1.2V  (12V  1.2V)
I L   3.86A
inductor values. This flexibility allows for 12V  500kHz  0.56H
optimization to find the best trade-off of efficiency, 3.86A
cost and size for a particular application. Selecting a IL,PEAK  11A   12.93A
2
low inductor value will help reduce size and cost and The resulting 3.86A ripple current is 3.86A/11A is
enhance transient response, but will increase peak 35.1%, well within the 20% ~ 50% target.
inductor ripple current, reducing efficiency and 3.86A
increasing output voltage ripple. The low DC IL,PEAK,RVS   1.93A  ILMT,RVS
2
resistance (DCR) of these low value inductors may
help reduce DC losses and increase efficiency. On the Finally, select an available inductor with a saturation
other hand, higher inductor values tend to have current higher than the resulting I L,PEAK of 12.93A.
higher DCR and will slow transient response.
Buck Output Capacitor Selection
A reasonable compromise between size, efficiency, Instant-PWM provides excellent performance with a
and transient response can be determined by selecting wide variety of output capacitor types. Ceramic and
a ripple current (ΔIL) about 20% ~ 50% of the desired POS types are most often selected due to their small
full output load current. Start calculating the size and low cost. Total capacitance is determined by
approximate inductor value by selecting the input and the transient response and output voltage ripple
output voltages, the operating frequency (fSW), the requirements of the system.
maximum output current (IOUT,MAX ) and estimating a
ΔIL as some percentage of that current. Buck Output Ripple
V  (VIN  VOUT ) Output voltage ripple at the switching frequency is
L1  OUT
VIN  fSW  IL caused by the inductor current ripple (ΔI L) on the
output capacitors ESR (ESR ripple) as well as the
Use this inductance value to determine the actual stored charge (capacitive ripple). When
inductor ripple current (ΔIL) and required peak considering total ripple, both should be considered.
current inductor current IL,PEAK. VRIPPLE,ESR  IL  ESR
V  (VIN  VOUT ) IL
IL  OUT VRIPPLE,CAP 
VIN  fSW  L1 8  COUT  fSW
IL
IL,PEAK  IOUT,MAX 
2 Consider a typical application with ΔIL = 3.86A using
Select an inductor with a saturation current and four 22μF ceramic capacitors, each with an ESR of
thermal rating in excess of IL,PEAK. ~6mΩ for parallel total of 88μF and 1.5mΩ ESR.
VRIPPLE,ESR  3.86A 1.5m  5.79mV
If USM light load operation is selected, make sure
3.86A
the inductor value is high enough to avoid reverse VRIPPLE,CAP   10.97mV
current limit is been triggered just under steady state 8  88F  500kHz
if the load current is zero. Total ripple = 16.76mV. The actual capacitive ripple
may be higher than calculated value because the
For highest efficiency, select an inductor with a low capacitance decreases with the voltage on the
DCR that meets the inductance, size and cost targets. capacitor.
Low loss ferrite materials should be considered.
Using a 150μF 40mΩ POS cap, the above result is
Buck Inductor Design Example VRIPPLE,ESR  3.86A  40m  154.40mV
Consider a typical design for a device providing 3.86A
1.2VOUT at 11A from 12VIN, operating at 500kHz and VRIPPLE,CAP   6.43mV
8 150F  500kHz
using target inductor ripple current (ΔI L) of 40% or
4.4A. Determine the approximate inductance value at Total ripple = 160.83mV
first:
1.2V  (12V  1.2V) Buck Output Transient Undershoot/Overshoot
L1   0.49H
12V  500kHz  4.4A If very fast load transient must be supported, consider
the effect of the output capacitor on the output
Next, select the nearest standard inductance value transient undershoot and overshoot. Instant-PWM
0.56μH in this case, and calculate the resulting responds quickly to changing load conditions,
inductor ripple current (ΔIL): however, some considerations must be needed,

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 SY8370
especially when using small ceramic capacitors 0.56H  (5.5A)2
VOVERSHOOT,CAP   47.06mV
which have low capacitance at low output voltages 2 150F 1.2V
which results in insufficient stored energy for load
transient. Output transient undershoot and overshoot Combine the ESR and capacitive undershoot and
have two causes: voltage changes caused by the ESR overshoot to calculate the total overshoot and
of the output capacitor and voltage changes caused undershoot for a given application.
by the output capacitance and inductor current slew
rate. Load Transient Considerations:
The SY8370 adopts the instant PWM architecture to
ESR undershoot or overshoot may be calculated as achieve good stability and fast transient responses. In
VESR = ΔIOUT×ESR. Using the ceramic capacitor applications with high step load current, adding an
example above and a fast load transient of ± 5.5A, RC network RFF and CFF between the OUT node and
VESR = ±5.5A × 1.5mΩ = ± 8.25mV. The POS the FB pin may further speed up the load transient
capacitor result with the same load transient, VESR = responses. RFF = 1kΩ and CFF = 220pF have been
±5.5A × 40mΩ = ±220.00mV. shown to perform well in most applications. Increase
CFF will speed up the load transient response if there
Capacitive undershoot (load increasing) is a function of is no stability issue.
the output capacitance, the load step, the inductor
value and the input-output voltage difference and the Note that when COUT > 500µF and minimum load
maximum duty factor. During a fast load transient, current is low, set feed-forward values as RFF = 1kΩ
the maximum duty factor of instant-PWM is a and CFF = 4.7nF to provide sufficient ripple to FB for
function of tON and the minimum tOFF as the control small output ripple and good transient behavior.
scheme is designed to rapidly ramp the inductor L1
current by grouping together many tON pulses in this LX VOUT
case. The maximum duty factor DMAX may be
RFF R1
calculated by (opt.)
t ON
DMAX  COUT
t ON +t OFF,MIN
CFF R2
Given this, the capacitive undershoot may be FB
calculated by
L1  IOUT
2
VUNDERSHOOT,CAP   Thermal Design Considerations
2  COUT  (VIN,MIN  D MAX  VOUT )
Maximum power dissipation depends on the thermal
resistance of the IC package, the PCB layout, the
Consider a 5.5A load increase using the ceramic surrounding airflow, and the difference between the
capacitor case when VIN = 12V. At VOUT = 1.2V, the junction and ambient temperatures. The maximum
result is tON = 200ns, tOFF,MIN = 200ns, DMAX = 200 / power dissipation may be calculated by:
(200+ 200) = 0.5 and PD,MAX = (TJ,MAX− TA) / θJA
0.56H  (5.5A) 2
VUNDERSHOOT,CAP    20.05mV
2  88F  (12V  0.5  1.2V)
Where, TJ,MAX is the maximum junction temperature,
Using the POS capacitor case, the above result is TA is the ambient temperature, and θJA is the junction
0.56H  (5.5A) 2
VUNDERSHOOT,CAP    11.76mV to ambient thermal resistance.
2 150F  (12V  0.5  1.2V)

To comply with the recommended operating conditions,

Capacitive overshoot (load decreasing) is a function
the maximum junction temperature is 125 ℃ . The
of the output capacitance, the inductor value and the
junction to ambient thermal resistance θJA is layout
output voltage.
dependent. For the QFN3×4-13 package the thermal
L1  IOUT
2
VOVERSHOOT,CAP  resistance θJA is 27 ℃ /W when measured on a
2  COUT  VOUT
standard Silergy 8.5cm×8.5cm size four-layer
Consider a 5.5A load decrease using the ceramic
thermal test board. These standard thermal test
capacitor case above. At VOUT = 1.2V the result is
layouts have a very large area with long 2-oz. copper
0.56H  (5.5A)2
VOVERSHOOT,CAP   80.21mV traces connected to each IC pin and very large,
2  88F 1.2V
unbroken 1-oz. internal power and ground planes.
Using the POS capacitor case, the above result is

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 SY8370
Meeting the performance of the standard thermal test VCC Capacitor: Place the VCC capacitor close to
board in a typical tiny evaluation board area requires VCC using short, direct copper trace to one nearest
wide copper traces well-connected to the IC's device GND pin (pin 11).
backside pads leading to exposed copper areas on the
component side of the board as well as good thermal BYP Capacitor: Place the BYP capacitor close to
via from the exposed pad connecting to a wide BYP using short, direct copper trace to one nearest
middle-layer ground plane and, perhaps, to an device GND pin (pin 11) if bypass function is used.
exposed copper area on the board's solder side.
Feedback Network: Place the feedback components
The maximum power dissipation at T A=25℃ may be (R1, R2, RFF and CFF) as close to FB pin as possible.
calculated by the following formula: Avoid routing the feedback line near LX, BS or other
PD,MAX = (125℃ − 25℃) / (27℃/W) = 3.7W high frequency signal as it is noise sensitive. Make
The maximum power dissipation depends on the feedback sampling point Kelvin connect with
operating ambient temperature for fixed T J,MAX and COUT rather than the inductor output terminal.
thermal resistance θJA. Use the derating curve in
figure below to calculate the effect of rising ambient LX Connection: Keep LX area small to prevent
temperature on the maximum power dissipation. excessive EMI, while providing wide copper traces to
Maximum Power Derating Curve
minimize parasitic resistance and inductance. Wide
4 LX copper trace between pin 2 and pin 12 should be
Maximum Power Dissipation (W)

3.7
3.5 adopted to improve efficiency.
3

2.5
BS Capacitor: Place the BS capacitor on the same
2
layer as the device, keep the BS voltage path (BS, LX
1.5

1
and CBS) as short as possible.
0.5

0
Control Signals: It is not recommended to connect
0 25 50 75 100 125
control signals and IN directly. A resistor in a range
Ambient Temperature (℃)
of 1kΩ to 1MΩ should be used if they are pulled high
by IN.
Layout Design
Follow these PCB layout guidelines for optimal GND Vias: Place adequate number of vias on the
performance and thermal dissipation. GND layer around the device for better thermal
performance. The exposed GND pad should be
Input Capacitors: Place the input capacitor very connected by a larger copper area than its size, place
near IN and GND, minimizing the loop formed by four GND vias on it for heat dissipation.
these connections. And the input capacitor should be
connected to the IN and GND by wide copper plane. PCB Board: A four-layer layout with 2-oz copper is
A 0.1μF input ceramic capacitor is recommended to strongly recommended to achieve better thermal
reduce the input noise. performance. The top layer and bottom layer should
place power IN and GND copper plane as wide as
Output Capacitors: Guarantee the COUT negative possible. Middle1 layer should place all GND layer
sides are connected with GND pin by wide copper for conducting heat and shielding middle2 layer
traces instead of vias, in order to achieve better signal line from top layer crosstalk. Place signal lines
accuracy and stability of output voltage. on middle2 layer instead of the other layers, so that
the other layers’ GND plane not be cut apart by these
signal lines.

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 SY8370

VIN L
IN Vias
CBS

CIN CIN
CIN
IN

13 BS

LX 2 12 LX COUT
GND 3 11 GND

PG 4 10 VCC

COUT
5

9
ILMT
TEST

BYP
FB
EN
CVCC
GND Vias
R2 COUT
CBYP
Output line
R1
GND COUT

CFF RFF

VBYP GND VOUT

Middle1 Layer
Top Layer
(GND Layer, not shown)

Middle2 Layer Bottom Layer

Figure4. PCB Layout Suggestion

AN_SY8370 Rev. 0.9C Silergy Corp. Confidential- Prepared for Customer Use Only 18
© 2020 Silergy Corp. All Rights Reserved.
 SY8370
QFN3×4-13 Package Outline Drawing

Top View Bottom View

Front View Recommended PCB layout

(Reference only)
Notes: 1, All dimension in millimeter and exclude mold flash & metal burr;
2, center line on drawing refers to the chip body center

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 SY8370
Taping & Reel Specification

1. QFN3×4-13 taping orientation

Feeding direction
2. Carrier Tape & Reel specification for packages

Reel
Size

Package Tape width Pocket Reel size Trailer Leader length Qty per
types (mm) pitch(mm) (Inch) length(mm) (mm) reel

QFN3×4 12 8 13" 400 400 5000

3. Others: NA

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© 2020 Silergy Corp. All Rights Reserved.
 SY8370
Revision History
The revision history provided is for informational purpose only and is believed to be accurate, however, not
warranted. Please make sure that you have the latest revision.
Date Revision Change
Feb.05, 2021 Revision 0.9C Update Recommended PCB layout in POD (page 19)
Jan.22, 2021 Revision 0.9B 1. Add (IN-LX) voltage in Absolute Maximum Ratings;
2. Add “A 0.1μF input ceramic capacitor is recommended to reduce the input
noise.” in the pin description and the layout design.
3. Add Table1: Programmable Valley Current Limit in page 13.
Oct.22, 2020 Revision 0.9A ILMT voltage changes from 26V to 4V in Absolute Maximum Ratings (page3)
Jul.15, 2020 Revision 0.9 Initial Release

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© 2020 Silergy Corp. All Rights Reserved.
 SY8370
IMPORTANT NOTICE
1. Right to make changes. Silergy and its subsidiaries (hereafter Silergy) reserve the right to change any information
published in this document, including but not limited to circuitry, specification and/or product design, manufacturing or
descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the
publication hereof. Buyers should obtain the latest relevant information before placing orders and should verify that such
information is current and complete. All semiconductor products are sold subject to Silergy’s standard terms and conditions of
sale.
2. Applications. Application examples that are described herein for any of these products are for illustrative purposes only.
Silergy makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification. Buyers are responsible for the design and operation of their applications and products using Silergy products.
Silergy or its subsidiaries assume no liability for any application assistance or designs of customer products. It is customer’s sole
responsibility to determine whether the Silergy product is suitable and fit for the customer’s applications and products planned.
To minimize the risks associated with customer’s products and applications, customer should provide adequate design and
operating safeguards. Customer represents and agrees that it has all the necessary expertise to create and implement safeguards
which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures
that might cause harm and take appropriate remedial actions. Silergy assumes no liability related to any default, damage, costs or
problem in the customer’s applications or products, or the application or use by customer’s third-party buyers. Customer will
fully indemnify Silergy, its subsidiaries, and their representatives against any damages arising out of the use of any Silergy
components in safety-critical applications. It is also buyers’ sole responsibility to warrant and guarantee that any intellectual
property rights of a third party are not infringed upon when integrating Silergy products into any application. Silergy assumes no
responsibility for any said applications or for any use of any circuitry other than circuitry entirely embodied in a Silergy product.
3. Limited warranty and liability. Information furnished by Silergy in this document is believed to be accurate and reliable.
However, Silergy makes no representation or warranty, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such information. In no event shall Silergy be liable for
any indirect, incidental, punitive, special or consequential damages, including but not limited to lost profits, lost savings, business
interruption, costs related to the removal or replacement of any products or rework charges, whether or not such damages are
based on tort or negligence, warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer
might incur for any reason whatsoever, Silergy’ aggregate and cumulative liability towards customer for the products described
herein shall be limited in accordance with the Standard Terms and Conditions of Sale of Silergy.
4. Suitability for use. Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory
and safety-related requirements concerning its products, and any use of Silergy components in its applications, notwithstanding
any applications-related information or support that may be provided by Silergy. Silergy products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where
failure or malfunction of an Silergy product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. Silergy assumes no liability for inclusion and/or use of Silergy products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own risk.
5. Terms and conditions of commercial sale. Silergy products are sold subject to the standard terms and conditions of
commercial sale, as published at http://www.silergy.com/stdterms, unless otherwise agreed in a valid written individual
agreement specifically agreed to in writing by an authorized officer of Silergy. In case an individual agreement is concluded only
the terms and conditions of the respective agreement shall apply. Silergy hereby expressly objects to and denies the application
of any customer’s general terms and conditions with regard to the purchase of Silergy products by the customer.
6. No offer to sell or license. Nothing in this document may be interpreted or construed as an offer to sell products that is
open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or
intellectual property rights. Silergy makes no representation or warranty that any license, either express or implied, is granted
under any patent right, copyright, mask work right, or other intellectual property right. Information published by Silergy
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endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from Silergy under the patents or other intellectual property of Silergy.
For more information, please visit: www.silergy.com
© 2020 Silergy Corp. All Rights Reserved.

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