STM32L100RC

Ultra-low-power 32b MCU ARM®-based Cortex®-M3, 256KB Flash,

16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC, memory I/F
Datasheet −production data

Features
• Ultra-low-power platform LQFP64 (10 × 10 mm)
– 1.65 V to 3.6 V power supply
– -40 °C to 105 °C temperature range
– 0.29 µA Standby mode (3 wakeup pins) • Memories
– 1.15 µA Standby mode + RTC – 256 Kbytes of Flash memory with ECC
– 0.44 µA Stop mode (16 wakeup lines) – 16 Kbytes of RAM
– 1.4 µA Stop mode + RTC – 4 Kbytes of true EEPROM with ECC
– 8.6 µA Low-power run mode – 20-byte backup register
– 185 µA/MHz Run mode
• LCD Driver for up to 8x28 segments
– 10 nA ultra-low I/O leakage
• Analog peripherals
– 8 µs wakeup time
– 12-bit ADC 1Msps up to 20 channels
• Core: ARM® Cortex®-M3 32-bit CPU
– 12-bit DACs 2 channels with output buffers
– From 32 kHz up to 32 MHz max
– 2x ultra-low-power-comparators
– 1.25 DMIPS/MHz (Dhrystone 2.1) (window mode and wakeup capability)
– Memory protection unit
• DMA controller 12x channels
• Reset and supply management
• 9x peripheral communication interfaces
– Low-power, ultrasafe BOR (brownout reset)
– 1x USB 2.0 (internal 48 MHz PLL)
with 5 selectable thresholds
– 3x USARTs
– Ultra-low-power POR/PDR
– Up to 8x SPIs (2x I2Ss, 3x 16 Mbits/s)
– Programmable voltage detector (PVD)
– 2xI2Cs (SMBus/PMBus)
• Clock sources
• 10x timers: 6x 16-bit with up to 4 IC/OC/PWM
– 1 to 24 MHz crystal oscillator
channels, 2x 16-bit basic timers, 2x watchdog
– 32 kHz oscillator for RTC with calibration timers (independent and window)
– High Speed Internal 16 MHz
• CRC calculation unit
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz
– PLL for CPU clock and USB (48 MHz)
• Pre-programmed bootloader
– USB and USART supported
• Development support
– Serial wire debug supported
– JTAG supported
• 51 fast I/Os (42 I/Os 5V tolerant), all mappable
on 16 external interrupt vectors

August 2017 DocID024995 Rev 5 1/106

This is information on a product in full production. www.st.com
Contents STM32L100RC

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22
3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.1 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 25
3.13 System configuration controller and routing interface . . . . . . . . . . . . . . . 25
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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3.14.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 27
3.15.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 28
3.17 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 46
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.20 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.21 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.1 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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List of tables

Table 1. Ultra-low-power STM32L100RC device features and peripheral counts . . . . . . . . . . . . . . 10

Table 2. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14
Table 3. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. STM32L100RC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 11. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 13. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 14. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 15. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 16. Current consumption in Run mode, code with data processing running from Flash. . . . . . 50
Table 17. Current consumption in Run mode, code with data processing running from RAM . . . . . . 51
Table 18. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 19. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 20. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 21. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 22. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 57
Table 23. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 24. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 25. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 26. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 27. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 28. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 29. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 30. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 31. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 32. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 33. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 34. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 35. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 70
Table 36. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 37. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 38. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 39. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 40. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 41. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 42. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 43. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 44. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 45. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 46. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 47. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 80

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Table 48. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 49. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 50. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 51. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 52. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 53. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 55. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 56. Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 57. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 58. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 59. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 60. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 61. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 62. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . . 99
Table 63. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 64. STM32L100RC ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 65. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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List of figures

Figure 1. Ultra-low-power STM32L100RC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. STM32L100RC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 7. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 8. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 10. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 12. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 14. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 15. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 16. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 17. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 18. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 19. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 20. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 21. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 22. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 23. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 25. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 26. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 98
Figure 28. LQFP64 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 29. LQFP64 device marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 30. Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 31. Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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7
Introduction STM32L100RC

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32L100RC ultra-low-power ARM® Cortex®-M3 based microcontroller product line.
The ultra-low-power STM32L100RC device is a microcontroller of 256 Kbytes in a 64-pin
package, the description below gives an overview of the complete range of peripherals
proposed in this device.
These features make the ultra-low-power STM32L100RC microcontroller suitable for a wide
range of applications:
• Medical and handheld equipment
• Application control and user interface
• PC peripherals, gaming, GPS and sport equipment
• Alarm systems, wired and wireless sensors, video intercom
• Utility metering
This STM32L100RC datasheet should be read in conjunction with the STM32L1xxxx
reference manual (RM0038). The application note “Getting started with STM32L1xxxx
hardware development” (AN3216) gives a hardware implementation overview. Both
documents are available from the STMicroelectronics website www.st.com.
For information on the ARM® Cortex®-M3 core please refer to the ARM® Cortex®-M3
technical reference manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device.

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2 Description

The ultra-low-power STM32L100RC device incorporates the connectivity power of the

universal serial bus (USB) with the high-performance ARM® Cortex®-M3 32-bit RISC core
operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), high-
speed embedded memories (Flash memory up to 256 Kbytes and RAM up to 16 Kbytes)
and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
The STM32L100RC device offers one 12-bit ADC, two DACs, two ultra-low-power
comparators, six general-purpose 16-bit timers and two basic timers, which can be used as
time bases.
Moreover, the STM32L100RC device contains standard and advanced communication
interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, and an USB.
It also includes a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller has a built-in LCD voltage generator that allows to
drive up to 8 multiplexed LCDs with the contrast independent of the supply voltage.
The ultra-low-power STM32L100RC device operates from a 1.8 to 3.6 V power supply
(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without
BOR option. It is available in the -40 to +85 °C and -40 to +105 °C temperature ranges. A
comprehensive set of power-saving modes allows the design of low-power applications.

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40
Description STM32L100RC

2.1 Device overview

Table 1. Ultra-low-power STM32L100RC device features and peripheral counts
Peripheral STM32L100RC

Flash (Kbytes) 256

Data EEPROM (Kbytes) 4

RAM (Kbytes) 16

General-
6
16-bit purpose
Timers
Basic 2

SPI 8(3)(1)

I2S 2
Communica
tion I2C 2
interfaces
USART 3

USB 1

GPIOs 51

12-bit synchronized ADC 1

Number of channels 20

12-bit DAC 2
Number total of channels 2

LCD
4x32 or 8x28
COM x SEG

Comparators 2

Max. CPU frequency 32 MHz

Operating voltage 1.8 V to 3.6 V

Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C

Operating temperatures
Junction temperature: –40 to + 110 °C

Package LQFP64

1. 5 SPIs are USART configured in synchronous mode emulating SPI master.

2.2 Ultra-low-power device continuum

The ultra-low-power family offers a large choice of cores and features. From proprietary 8-
bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank

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STM32L100RC

memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow to build very cost-optimized applications by reducing BOM.
Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.

2.2.1 Performance
All the families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

2.2.2 Shared peripherals

STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
• Analog peripherals: ADC, DAC and comparators
• Digital peripherals: RTC and some communication interfaces

2.2.3 Common system strategy.

To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
• Same power supply range from 1.65 V to 3.6 V
• Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
• Fast startup strategy from low-power modes
• Flexible system clock
• Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector

2.2.4 Features
ST ultra-low-power continuum also lies in feature compatibility:
• More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
• Memory density ranging from 2 to 512 Kbytes

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40
Functional overview STM32L100RC

3 Functional overview

Figure 1. Ultra-low-power STM32L100RC block diagram

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STM32L100RC

3.1 Low-power modes

The ultra-low-power STM32L100RC device supports dynamic voltage scaling to optimize its
power consumption in run mode. The voltage from the internal low-drop regulator that
supplies the logic can be adjusted according to the system’s maximum operating frequency
and the external voltage supply.
There are three power consumption ranges:
• Range 1 (VDD range limited to 2.0 V - 3.6 V), with the CPU running at up to 32 MHz
• Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
• Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
• Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI
range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or
Flash memory, and internal regulator in low-power mode to minimize the regulator's
operating current. In low-power run mode, the clock frequency and the number of
enabled peripherals are both limited.
• Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
• Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.

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40
Functional overview STM32L100RC

• Stop mode without RTC

Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
• Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
• Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.

Table 2. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply range(1)

Operating power DAC and ADC

USB Dynamic voltage scaling range
supply range operation

Conversion time Range 2 or

VDD = 1.8 to 2.0 V Not functional
up to 500 Ksps range 3

Conversion time
VDD = 2.0 to 2.4 V up to Functional(2) Range 1, range 2 or range 3
500 Ksps
Conversion time
VDD = 2.4 to 3.6 V up to Functional(2) Range 1, range 2 or range 3
1 Msps
1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 43: I/O AC
characteristics for more information about I/O speed.
2. To be USB compliant from the IO voltage standpoint, the minimum VDD is 3.0 V.

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Table 3. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

Range 1
32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

Range 2
32 kHz to 8 MHz (0ws)

2.1MHz to 4.2 MHz (1ws)

Range 3
32 kHz to 2.1 MHz (0ws)

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40
Functional overview STM32L100RC

Table 4. Functionalities depending on the working mode (from Run/active down to

standby)
Stop Standby
Low- Low-
Ips Run/Active Sleep power power
Wakeup Wakeup
Run Sleep
capability capability

CPU Y -- Y -- -- -- -- --
Flash Y Y Y Y -- -- -- --
RAM Y Y Y Y Y -- -- --
Backup Registers Y Y Y Y Y -- Y --
EEPROM Y Y Y Y Y -- -- --
Brown-out rest
Y Y Y Y Y Y Y --
(BOR)
DMA Y Y Y Y -- -- -- --
Programmable
Voltage Detector Y Y Y Y Y Y Y --
(PVD)
Power On Reset
Y Y Y Y Y Y Y --
(POR)
Power Down Rest
Y Y Y Y Y -- Y --
(PDR)
High Speed
Y Y -- -- -- -- -- --
Internal (HSI)
High Speed
Y Y -- -- -- -- -- --
External (HSE)
Low Speed Internal
Y Y Y Y Y -- Y --
(LSI)
Low Speed
Y Y Y Y Y -- Y --
External (LSE)
Multi-Speed
Y Y Y Y -- -- -- --
Internal (MSI)
Inter-Connect
Y Y Y Y -- -- -- --
Controller
RTC Y Y Y Y Y Y Y --
RTC Tamper Y Y Y Y Y Y Y Y
Auto WakeUp
Y Y Y Y Y Y Y Y
(AWU)
LCD Y Y Y Y Y -- -- --
USB Y Y -- -- -- Y -- --
(1)
USART Y Y Y Y Y -- --
SPI Y Y Y Y -- -- -- --
(1)
I2C Y Y -- -- -- -- --

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Table 4. Functionalities depending on the working mode (from Run/active down to

standby) (continued)
Stop Standby
Low- Low-
Ips Run/Active Sleep power power
Wakeup Wakeup
Run Sleep
capability capability

ADC Y Y -- -- -- -- -- --
DAC Y Y Y Y Y -- -- --
Tempsensor Y Y Y Y Y -- -- --
OP amp Y Y Y Y Y -- -- --
Comparators Y Y Y Y Y Y -- --
16-bit and 32-bit
Y Y Y Y -- -- -- --
Timers
IWDG Y Y Y Y Y Y Y Y
WWDG Y Y Y Y -- -- -- --
Touch sensing Y Y -- -- -- -- -- --
Systic Timer Y Y Y Y -- -- --
GPIOs Y Y Y Y Y Y -- 3 pins
Wakeup time to
0 µs 0.4 µs 3 µs 46 µs < 8 µs 58 µs
Run mode
0.43 µA 0.29 µA
(no RTC) (no RTC)
VDD=1.8V VDD=1.8V
1.15 µA 0.9 µA
(with RTC) (with RTC)
Consumption Down to 185 Down to 34.5 VDD=1.8V VDD=1.8V
Down to Down to
VDD=1.8 to 3.6 V µA/MHz (from µA/MHz (from
8.6 µA 4.4 µA 0.44 µA 0.29 µA
(Typ) Flash) Flash)
(no RTC) (no RTC)
VDD=3.0V VDD=3.0V
1.4 µA 1.15 µA
(with RTC) (with RTC)
VDD=3.0V VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.

3.2 ARM® Cortex®-M3 core with MPU

The ARM® Cortex®-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit device.

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Functional overview STM32L100RC

The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L100RC device is compatible with all ARM
tools and software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L100RC device embeds a nested vectored interrupt controller
able to handle up to 52 maskable interrupt channels (not including the 16 interrupt lines of
ARM® Cortex®-M3) and 16 priority levels.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support for tail-chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

3.3 Reset and supply management

3.3.1 Power supply schemes

• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
• VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.

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STM32L100RC

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for a device with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR) and power down.
• MR is used in Run mode (nominal regulation)
• LPR is used in the Low-power run, Low-power sleep and Stop modes
• Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).

3.3.4 Boot modes

At startup, boot pins are used to select one of three boot options:
• Boot from Flash memory
• Boot from System memory
• Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1 and USART2. See Application note “STM32 microcontroller system memory
boot mode” (AN2606) for details.

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40
Functional overview STM32L100RC

3.4 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
• RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
• USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
• Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
• Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.

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Figure 2. Clock tree

3TANDBY SUPPLIED VOLTAGE DOMAIN

ENABLE
7ATCHDOG 7ATCHDOG
,3) 2# ,3) TEMPO ,3

24# ENABLE
24#
,3% /3# ,3% TEMPO

2ADIO 3LEEP 4IMER

2ADIO 3LEEP 4IMER ENABLE

,3 ,3 ,3 ,3

6$$#/2%
#+?,#$
 -(Z ,#$ ENABLE

6
#+?!$#
-3) 2# CK?LSI !$# ENABLE
CK?LSE
LEVEL SHIFTERS
6$$#/2% -#/
     
NOT DEEPSLEEP
    
6 #+?072
NOT DEEPSLEEP
(3) 2#
#+?&#,+
LEVEL SHIFTERS NOT SLEEP OR
DEEPSLEEP
6$$#/2%
#+?#05
3YSTEM NOT SLEEP OR
6 CLOCK DEEPSLEEP
(3% CK?MSI #+?4)-393
/3# CK?HSI 
!("
LEVEL SHIFTERS CK?HSE PRESCALER
6$$#/2%    
6 CK?PLL
0,, !0" !0"
CK?PLLIN 8     
PRESCALER PRESCALER
,3                
6
  
 -(Z CLOCK
DETECTOR LEVEL SHIFTERS
#LOCK
6$$#/2% SOURCE
(3% PRESENT OR NOT
,3 CONTROL

USBEN AND NOT DEEPSLEEP

#+?53"
CK?USB  6CO   6CO MUST BE ATZ -(

TIMEREN AND NOT DEEPSLEEP

#+?4)-4'/
IF !0" PRESC   X
ELSE X
APB PERIPHEN AND NOT DEEPSLEEP
#+?!0"

APB PERIPHEN AND NOT DEEPSLEEP

#+?!0"

-36

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40
Functional overview STM32L100RC

3.5 Low-power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are twenty 32-bit backup registers provided to store 80 bytes of user application data.
They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.

3.6 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.

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3.7 Memories
The STM32L100RC device has the following features:
• 16 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
• The non-volatile memory is divided into three arrays:
– 128 Kbytes of embedded Flash program memory
– 4 Kbytes of data EEPROM
– Options bytes
The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8 DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.

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Functional overview STM32L100RC

3.9 LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 32 segment terminals to drive up to 320224
pixels.
• Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Up to 8 pixels can be programmed to blink
• Unneeded segments and common pins can be used as general I/O pins
• LCD RAM can be updated at any time owing to a double-buffer
• The LCD controller can operate in Stop mode

3.10 ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L100RC device with up to 20
external channels, performing conversions in single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs with up to 20
external channels in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.

3.10.1 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in read-
only mode. See Table 14: Embedded internal reference voltage calibration values.

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3.11 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
• Two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channels, independent or simultaneous conversions
• DMA capability for each channel (including the underrun interrupt)
• External triggers for conversion
• Input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L100RC device. The DAC channels are
triggered through the timer update outputs that are also connected to different DMA
channels.

3.12 Ultra-low-power comparators and reference voltage

The STM32L100RC device embeds two comparators sharing the same current bias and
reference voltage. The reference voltage can be internal or external (coming from an I/O).
• One comparator with fixed threshold
• One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
– DAC output
– External I/O
– Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4)
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).

3.13 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
VREFINT.

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Functional overview STM32L100RC

3.14 Timers and watchdogs

The ultra-low-power STM32L100RC device includes seven general-purpose timers, two
basic timers, and two watchdog timers.
Table 5 compares the features of the general-purpose and basic timers.

Table 5. Timer feature comparison

DMA
Counter Capture/compare Complementary
Timer Counter type Prescaler factor request
resolution channels outputs
generation

TIM2,
Up, down, Any integer between
TIM3, 16-bit Yes 4 No
up/down 1 and 65536
TIM4
Up, down, Any integer between
TIM9 16-bit No 2 No
up/down 1 and 65536
TIM10, Any integer between
16-bit Up No 1 No
TIM11 1 and 65536
TIM6, Any integer between
16-bit Up Yes 0 No
TIM7 1 and 65536

3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and

TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L100RC
device (see Table 5 for differences).

TIM2, TIM3, TIM4

TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. They include a 16-bit
prescaler. They feature four independent channels each for input capture/output compare,
PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs
on the largest packages.
TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11 and
TIM9 general-purpose timers via the Timer Link feature for synchronization or event
chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers
can be used to generate PWM outputs.
TIM2, TIM3, TIM4 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4 full-featured general-purpose timers.

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They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.

3.14.2 Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.

3.14.3 SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.

3.14.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.

3.14.5 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.15 Communication interfaces

3.15.1 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.

3.15.2 Universal synchronous/asynchronous receiver transmitter (USART)

The three USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They
support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide
hardware management of the CTS and RTS signals and are ISO 7816 compliant.
All USART interfaces can be served by the DMA controller.

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40
Functional overview STM32L100RC

3.15.3 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.

3.15.4 Universal serial bus (USB)

The STM32L100RC device embeds a USB device peripheral compatible with the USB full-
speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It
has software-configurable endpoint setting and supports suspend/resume. The dedicated
48 MHz clock is generated from the internal main PLL (the clock source must use a HSE
crystal oscillator).

3.16 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

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3.17 Development support

3.17.1 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.

3.17.2 Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L100RC devices through a small number of ETM pins to an external hardware trace
port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet,
or any other high-speed channel. Real-time instruction and data flow activity can be
recorded and then formatted for display on the host computer running debugger software.
TPA hardware is commercially available from common development tool vendors. It
operates with third party debugger software tools.

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40
Pin descriptions STM32L100RC

4 Pin descriptions

Figure 3. STM32L100RC LQFP64 pinout

"//4
6$$?
633?

0#
0#
0#
0!
0!
0$
0"
0"

0"
0"
0"
0"
0"
               
6,#$   6$$?
0# 7+50   633? 
0# /3#?).   0!
0# /3#?/54   0!
0( /3#?).   0!
0( /3#?/54   0!
.234   0!
0#   0!
0#  ,1&0  0#
0#   0#
0#   0#
633!   0#
6$$!   0"
0! 7+50   0"
0!   0"
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0!
633?

0!
0!
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0"
0"
0"
0"
0"
633?
0#
0#

AIC

1. This figure shows the package top view.

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Table 6. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function
Pin name
during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TC Standard 3.3 V I/O
I/O structure
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
Notes
and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions

Table 7. STM32L100RC pin definitions

Pins Pin functions
I / O Level(2)

Main
Type(1)
LQFP64

Pin name function

(after reset) Alternate functions Additional functions

1 VLCD S - VLCD - -
WKUP2/RTC_TAMP1/
2 PC13-WKUP2 I/O FT PC13 -
RTC_TS/RTC_OUT
PC14-
3 I/O - PC14 - OSC32_IN
OSC32_IN(3)
PC15-
4 I/O - PC15 - OSC32_OUT
OSC32_OUT(3)
5 PH0-OSC_IN(4) I - PH0 - OSC_IN
PH1-
6 O - PH1 - OSC_OUT
OSC_OUT(4)
7 NRST I/O NRST - -
8 PC0 I/O FT PC0 LCD_SEG18 ADC_IN10/COMP1_INP
9 PC1 I/O FT PC1 LCD_SEG19 ADC_IN11/COMP1_INP

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40
Pin descriptions STM32L100RC

Table 7. STM32L100RC pin definitions (continued)

Pins Pin functions

I / O Level(2)
Main

Type(1)
LQFP64

Pin name function

(after reset) Alternate functions Additional functions

10 PC2 I/O FT PC2 LCD_SEG20 ADC_IN12/COMP1_INP

11 PC3 I/O - PC3 LCD_SEG21 ADC_IN13/COMP1_INP
12 VSSA S - VSSA - -
13 VDDA S - VDDA - -
TIM2_CH1_ETR/ WKUP1/RTC_TAMP2/
14 PA0-WKUP1 I/O FT PA0
USART2_CTS ADC_IN0/COMP1_INP
TIM2_CH2/USART2_RTS/ ADC_IN1/COMP1_INP/
15 PA1 I/O FT PA1
LCD_SEG0 OPAMP1_VINP
TIM2_CH3/TIM9_CH1/ ADC_IN2/
16 PA2 I/O FT PA2
USART2_TX/LCD_SEG1 COMP1_INP/ OPAMP1_VINM
TIM2_CH4/TIM9_CH2 ADC_IN3/
17 PA3 I/O - PA3
/USART2_RX/LCD_SEG2 COMP1_INP/OPAMP1_VOUT
18 VSS_4 S - VSS_4 - -
19 VDD_4 S - VDD_4 - -
SPI1_NSS/SPI3_NSS/ ADC_IN4/DAC_OUT1/
20 PA4 I/O - PA4
I2S3_WS/USART2_CK COMP1_INP
ADC_IN5/
21 PA5 I/O - PA5 TIM2_CH1_ETR/SPI1_SCK
DAC_OUT2/COMP1_INP
TIM3_CH1/TIM10_CH1/ ADC_IN6/COMP1_INP/
22 PA6 I/O FT PA6
SPI1_MISO/LCD_SEG3 OPAMP2_VINP
TIM3_CH2/TIM11_CH1/ ADC_IN7/COMP1_INP
23 PA7 I/O FT PA7
SPI1_MOSI/LCD_SEG4 /OPAMP2_VINM
24 PC4 I/O FT PC4 LCD_SEG22 ADC_IN14/COMP1_INP
25 PC5 I/O FT PC5 LCD_SEG23 ADC_IN15/COMP1_INP
ADC_IN8/COMP1_INP/
26 PB0 I/O - PB0 TIM3_CH3/LCD_SEG5
OPAMP2_VOUT/VREF_OUT
ADC_IN9/
27 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6
COMP1_INP/VREF_OUT
28 PB2 I/O FT PB2/BOOT1 BOOT1 COMP1_INP
TIM2_CH3/I2C2_SCL/
29 PB10 I/O FT PB10 -
USART3_TX/LCD_SEG10
TIM2_CH4/I2C2_SDA/
30 PB11 I/O FT PB11 -
USART3_RX/LCD_SEG11

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Table 7. STM32L100RC pin definitions (continued)

Pins Pin functions

I / O Level(2)
Main

Type(1)
LQFP64

Pin name function

(after reset) Alternate functions Additional functions

31 VSS_1 S - VSS_1 - -
32 VDD_1 S - VDD_1 - -
TIM10_CH1/I2C2_SMBA/
33 PB12 I/O FT PB12 SPI2_NSS/I2S2_WS/ ADC_IN18/COMP1_INP
USART3_CK/LCD_SEG12
TIM9_CH1/SPI2_SCK/
34 PB13 I/O FT PB13 I2S2_CK/ USART3_CTS/ ADC_IN19/COMP1_INP
LCD_SEG13
TIM9_CH2/SPI2_MISO/ ADC_IN20/COMP1_INP
35 PB14 I/O FT PB14
USART3_RTS/LCD_SEG14

TIM11_CH1/SPI2_MOSI/ ADC_IN21/COMP1_INP/
36 PB15 I/O FT PB15
I2S2_SD/LCD_SEG15 RTC_REFIN
TIM3_CH1/I2S2_MCK/
37 PC6 I/O FT PC6 -
LCD_SEG24
TIM3_CH2/I2S3_MCK/
38 PC7 I/O FT PC7 -
LCD_SEG25
39 PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 -
40 PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 -
USART1_CK/MCO/
41 PA8 I/O FT PA8 -
LCD_COM0
42 PA9 I/O FT PA9 USART1_TX/LCD_COM1 -
43 PA10 I/O FT PA10 USART1_RX/LCD_COM2 -
44 PA11 I/O FT PA11 USART1_CTS/SPI1_MISO USB_DM
45 PA12 I/O FT PA12 USART1_RTS/SPI1_MOSI USB_DP
JTMS-
46 PA13 I/O FT JTMS-SWDIO -
SWDIO
47 VSS_2 S VSS_2 - -
48 VDD_2 S VDD_2 - -
JTCK-
49 PA14 I/O FT JTCK-SWCLK -
SWCLK
TIM2_CH1_ETR/SPI1_NSS/
50 PA15 I/O FT JTDI SPI3_NSS/ -
I2S3_WS/LCD_SEG17/JTDI

DocID024995 Rev 5 33/106

40
Pin descriptions STM32L100RC

Table 7. STM32L100RC pin definitions (continued)

Pins Pin functions

I / O Level(2)
Main

Type(1)
LQFP64

Pin name function

(after reset) Alternate functions Additional functions

SPI3_SCK/I2S3_CK/
51 PC10 I/O FT PC10 USART3_TX/LCD_SEG28/ -
LCD_SEG40/LCD_COM4
SPI3_MISO/USART3_RX/
52 PC11 I/O FT PC11 LCD_SEG29 -
/LCD_SEG41/LCD_COM5
SPI3_MOSI/I2S3_SD/
53 PC12 I/O FT PC12 USART3_CK/LCD_SEG30/ -
LCD_SEG42/LCD_COM6
TIM3_ETR/LCD_SEG31/
54 PD2 I/O FT PD2 -
LCD_SEG43/LCD_COM7
TIM2_CH2/SPI1_SCK/
55 PB3 I/O FT JTDO SPI3_SCK/I2S3_CK/ COMP2_INM
LCD_SEG7/JTDO
TIM3_CH1/SPI1_MISO/
56 PB4 I/O FT NJTRST SPI3_MISO/LCD_SEG8/ COMP2_INP
NJTRST
TIM3_CH2/I2C1_SMBA/
57 PB5 I/O FT PB5 SPI1_MOSI/SPI3_MOSI/ COMP2_INP
I2S3_SD/LCD_SEG9
TIM4_CH1/I2C1_SCL/
58 PB6 I/O FT PB6 COMP2_INP
USART1_TX

TIM4_CH2/I2C1_SDA/ COMP2_INP/PVD_IN
59 PB7 I/O FT PB7
USART1_RX

60 BOOT0 I - BOOT0 - -
TIM4_CH3/TIM10_CH1/
61 PB8 I/O FT PB8 -
I2C1_SCL/LCD_SEG16
TIM4_CH4/TIM11_CH1/
62 PB9 I/O FT PB9 -
I2C1_SDA/LCD_COM3
63 VSS_3 S - VSS_3 - -
64 VDD_3 S - VDD_3 - -
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).

34/106 DocID024995 Rev 5

STM32L100RC

4. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.

DocID024995 Rev 5 35/106

40
 Alternate functions
36/106

Pin descriptions
Table 8. Alternate function input/output
Digital alternate function number

. .
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO11 AFIO14 AFIO15
. .
Port name
Alternate function

TIM9/
SYSTEM TIM2 TIM3/4 I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD CPRI SYSTEM
10/11

EVENT
BOOT0 BOOT0 - - - - - - - - -
OUT

NRST NRST - - - - - - - - - -

EVENT
PA0-WKUP1 - TIM2_CH1_ ETR - - - - - USART2_CTS - TIMx_IC1
OUT
DocID024995 Rev 5

EVENT
PA1 - TIM2_CH2 - - - - - USART2_RTS SEG0 TIMx_IC2
OUT

EVENT
PA2 - TIM2_CH3 - TIM9_CH1 - - - USART2_TX SEG1 TIMx_IC3
OUT

EVENT
PA3 - TIM2_CH4 - TIM9_CH2 - - - USART2_RX SEG2 TIMx_IC4
OUT

SPI3_NSS EVENT
PA4 - - - - - SPI1_NSS USART2_CK - TIMx_IC1
I2S3_WS OUT

EVENT
PA5 - TIM2_CH1_ETR - - - SPI1_SCK - - - TIMx_IC2
OUT

EVENT
PA6 - - TIM3_CH1 TIM10_ CH1 - SPI1_MISO - - SEG3 TIMx_IC3
OUT

EVENT
PA7 - - TIM3_CH2 TIM11_ CH1 - SPI1_MOSI - - SEG4 TIMx_IC4
OUT

EVENT
PA8 MCO - - - - - - USART1_CK COM0 TIMx_IC1
OUT

EVENT
PA9 - - - - - - - USART1_TX COM1 TIMx_IC2

STM32L100RC
OUT

EVENT
PA10 - - - - - - - USART1_RX COM2 TIMx_IC3
OUT

EVENT
PA11 - - - - - SPI1_MISO - USART1_CTS - TIMx_IC4
OUT
 Table 8. Alternate function input/output (continued)

STM32L100RC
Digital alternate function number

. .
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO11 AFIO14 AFIO15
. .
Port name
Alternate function

TIM9/
SYSTEM TIM2 TIM3/4 I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD CPRI SYSTEM
10/11

EVENT
PA12 - - - - - SPI1_MOSI - USART1_RTS - TIMx_IC1
OUT

EVENT
PA13 JTMS-SWDIO - - - - - - - - TIMx_IC2
OUT

EVEN
PA14 JTCK-SWCLK - - - - - - - - TIMx_IC3
TOUT

SPI3_NSS EVEN
PA15 JTDI TIM2_CH1_ETR - - - SPI1_NSS - SEG17 TIMx_IC4
I2S3_WS TOUT
DocID024995 Rev 5

EVEN
PB0 - - TIM3_CH3 - - - - - SEG5 -
TOUT

EVENT
PB1 - - TIM3_CH4 - - - - - SEG6 -
OUT

EVENT
PB2 BOOT1 - - - - - - - - -
OUT

SPI3_SCK EVENT
PB3 JTDO TIM2_CH2 - - - SPI1_SCK - SEG7 -
I2S3_CK OUT

EVENT
PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO - SEG8 -
OUT

I2C1_ SPI3_MOSI EVENT

PB5 - - TIM3_CH2 - SPI1_MOSI - SEG9 -
SMBA I2S3_SD OUT

EVENT
PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - -
OUT

EVENT
PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - -
OUT

EVENT
PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - SEG16 -
OUT

EVENT
PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA - - - COM3 -
OUT

EVENT
PB10 - TIM2_CH3 - - I2C2_SCL - - USART3_TX SEG10 -
37/106

OUT
 Table 8. Alternate function input/output (continued)
38/106

Pin descriptions
Digital alternate function number

. .
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO11 AFIO14 AFIO15
. .
Port name
Alternate function

TIM9/
SYSTEM TIM2 TIM3/4 I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD CPRI SYSTEM
10/11

EVENT
PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX SEG11 -
OUT

SPI2_NSS EVENT
PB12 - - - TIM10_CH1 I2C2_SMBA - USART3_CK SEG12 -
I2S2_WS OUT

SPI2_SCK EVENT
PB13 - - - TIM9_CH1 - - USART3_CTS SEG13 -
I2S2_CK OUT

EVENT
PB14 - - - TIM9_CH2 - SPI2_MISO - USART3_RTS SEG14 -
OUT
DocID024995 Rev 5

SPI2_MOSI EVENT
PB15 - - - TIM11_CH1 - - - SEG15 -
I2S2_SD OUT

EVENT
PC0 - - - - - - - - SEG18 TIMx_IC1
OUT

EVENT
PC1 - - - - - - - - SEG19 TIMx_IC2
OUT

EVENT
PC2 - - - - - - - - SEG20 TIMx_IC3
OUT

EVENT
PC3 - - - - - - - - SEG21 TIMx_IC4
OUT

EVENT
PC4 - - - - - - - - SEG22 TIMx_IC1
OUT

EVENT
PC5 - - - - - - - - SEG23 TIMx_IC2
OUT

EVENT
PC6 - - TIM3_CH1 - - I2S2_MCK - - SEG24 TIMx_IC3
OUT

EVENT
PC7 - - TIM3_CH2 - - - I2S3_MCK - SEG25 TIMx_IC4
OUT

STM32L100RC
EVENT
PC8 - - TIM3_CH3 - - - - - SEG26 TIMx_IC1
OUT

EVENT
PC9 - - TIM3_CH4 - - - - - SEG27 TIMx_IC2
OUT
 Table 8. Alternate function input/output (continued)

STM32L100RC
Digital alternate function number

. .
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO11 AFIO14 AFIO15
. .
Port name
Alternate function

TIM9/
SYSTEM TIM2 TIM3/4 I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD CPRI SYSTEM
10/11

COM4/
SPI3_SCK EVENT
PC10 - - - - - - USART3_TX SEG28/ TIMx_IC3
I2S3_CK OUT
SEG40

COM5/
EVENT
PC11 - - - - - - SPI3_MISO USART3_RX SEG29 TIMx_IC4
OUT
/SEG41

COM6/
SPI3_MOSI EVENT
PC12 - - - - - - USART3_CK SEG30/ TIMx_IC1
I2S3_SD OUT
SEG42
DocID024995 Rev 5

EVENT
PC13-WKUP2 - - - - - - - - - TIMx_IC2
OUT

PC14 EVENT
- - - - - - - - - TIMx_IC3
OSC32_IN OUT

PC15 EVENT
- - - - - - - - - TIMx_IC4
OSC32_OUT OUT

COM7/
EVENT
PD2 - - TIM3_ETR - - - - - SEG31/ TIMx_IC3
OUT
SEG43

PH0OSC_IN - - - - - - - - - - -

PH1OSC_OUT - - - - - - - - - - -
39/106
Memory mapping STM32L100RC

5 Memory mapping

Figure 4. Memory map

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X%  X 
0ORT (
X 
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X #
X  0ORT #
X  0ORT "
X# 
X  0ORT !
X # RESERVED
X  53!24
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X 
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X 
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X&&  53" 2EGISTERS
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06Y9

40/106 DocID024995 Rev 5

STM32L100RC

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the device with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the device have an
error less than or equal to the value indicated (mean ±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

Figure 5. Pin loading conditions Figure 6. Pin input voltage

0&8SLQ 0&8SLQ
& S)
9,1

DLF DLG

DocID024995 Rev 5 41/106

97
Electrical characteristics STM32L100RC

6.1.6 Power supply scheme

Figure 7. Power supply scheme

6WDQGE\SRZHUFLUFXLWU\
/6(57&:DNHXS
ORJLF57&EDFNXS
UHJLVWHUV

/HYHOVKLIWHU
287
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9''
5HJXODWRU
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Q) $QDORJ
—) Q) $'& 26&3//&203
95() '$& «
—)

966$

1±QXPEHURI
9''966SDLUV
069

42/106 DocID024995 Rev 5

STM32L100RC

6.1.7 Optional LCD power supply scheme

Figure 8. Optional LCD power supply scheme

9'' 96(/
9''1 6WHSXS
1[Q)
&RQYHUWHU
[—)

2SWLRQ 9/&'

Q) /&'
9/&'

2SWLRQ
&(;7
9661

069

1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.

6.1.8 Current consumption measurement

Figure 9. Current consumption measurement scheme

$ 1[9''
1[Q)
 [—)

1[966

9/&'
9''$
Q) 95()
—)
95()
966$

069

DocID024995 Rev 5 43/106

97
Electrical characteristics STM32L100RC

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics,
Table 10: Current characteristics, and Table 11: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Table 9. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage

VDD–VSS –0.3 4.0
(including VDDA and VDD)(1)
V
Input voltage on five-volt tolerant pin VSS −0.3 VDD+4.0
VIN(2)
Input voltage on any other pin VSS − 0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX − VSS| Variations between all different ground pins(3) - 50
VREF+ –VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V
Electrostatic discharge voltage
VESD(HBM) see Section 6.3.11
(human body model)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. VIN maximum must always be respected. Refer to Table 10 for maximum allowed injected current values.
3. Include VREF- pin.

Table 10. Current characteristics

Symbol Ratings Max. Unit

IVDD(Σ) Total current into sum of all VDD_x power lines (source)(1) 100
(2)
IVSS(Σ) Total current out of sum of all VSS_x ground lines (sink)(1) 100
IVDD(PIN) Maximum current into each VDD_x power pin (source)(1) 70
IVSS(PIN) Maximum current out of each VSS_x ground pin (sink)(1) -70
Output current sunk by any I/O and control pin 25
IIO
Output current sourced by any I/O and control pin - 25 mA
Total output current sunk by sum of all IOs and control pins(2) 60
ΣIIO(PIN)
(2)
Total output current sourced by sum of all IOs and control pins -60
Injected current on five-volt tolerant I/O(4), RST and B pins -5/+0
IINJ(PIN) (3)
Injected current on any other pin (5)
±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.

44/106 DocID024995 Rev 5

STM32L100RC

4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 9 for maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 9: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).

Table 11. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

6.3 Operating conditions

6.3.1 General operating conditions

Table 12. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 32

fPCLK1 Internal APB1 clock frequency - 0 32 MHz
fPCLK2 Internal APB2 clock frequency - 0 32
BOR detector disabled 1.65 3.6
BOR detector enabled, at
1.8 3.6
VDD Standard operating voltage power on V
BOR detector disabled, after
1.65 3.6
power on
Analog operating voltage
1.65 3.6
(ADC and DAC not used) Must be the same voltage as
(1)
VDDA V
Analog operating voltage VDD(2)
1.8 3.6
(ADC or DAC used)
FT pins; 2.0 V ≤VDD -0.3 5.5(3)
FT pins; VDD < 2.0 V -0.3 5.25(3)
VIN I/O input voltage V
BOOT0 pin 0 5.5
Any other pin -0.3 VDD+0.3
Power dissipation at
PD TA = 85 °C for suffix 6 or TA=105°C for LQFP64 package - 444 mW
suffix 7(4)
Ambient temperature for 6 suffix version Maximum power dissipation(5) –40 85
TA °C
Ambient temperature for 7 suffix version Maximum power dissipation –40 105
6 suffix version –40 105
TJ Junction temperature range °C
7 suffix version –40 110

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97
Electrical characteristics STM32L100RC

1. When the ADC is used, refer to Table 54: ADC characteristics.

2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up .
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 63: Thermal characteristics
on page 101).
5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ
max (see Table 63: Thermal characteristics on page 101).

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the
conditions summarized in Table 12.

Table 13. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

BOR detector enabled 0 - ∞

VDD rise time rate
BOR detector disabled 0 - 1000
tVDD(1) µs/V
BOR detector enabled 20 - ∞
VDD fall time rate
BOR detector disabled 0 - 1000
VDD rising, BOR enabled - 2 3.3
TRSTTEMPO(1) Reset temporization ms
VDD rising, BOR disabled(2) 0.4 0.7 1.6

Power on/power down reset Falling edge 1 1.5 1.65

VPOR/PDR
threshold Rising edge 1.3 1.5 1.65
Falling edge 1.67 1.7 1.74
VBOR0 Brown-out reset threshold 0
Rising edge 1.69 1.76 1.8
V
Falling edge 1.87 1.93 1.97
VBOR1 Brown-out reset threshold 1
Rising edge 1.96 2.03 2.07
Falling edge 2.22 2.30 2.35
VBOR2 Brown-out reset threshold 2
Rising edge 2.31 2.41 2.44

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STM32L100RC

Table 13. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

Falling edge 2.45 2.55 2.6

VBOR3 Brown-out reset threshold 3
Rising edge 2.54 2.66 2.7
Falling edge 2.68 2.8 2.85
VBOR4 Brown-out reset threshold 4
Rising edge 2.78 2.9 2.95

Programmable voltage detector Falling edge 1.8 1.85 1.88

VPVD0
threshold 0 Rising edge 1.88 1.94 1.99
Falling edge 1.98 2.04 2.09
VPVD1 PVD threshold 1
Rising edge 2.08 2.14 2.18
Falling edge 2.20 2.24 2.28
VPVD2 PVD threshold 2 V
Rising edge 2.28 2.34 2.38
Falling edge 2.39 2.44 2.48
VPVD3 PVD threshold 3
Rising edge 2.47 2.54 2.58
Falling edge 2.57 2.64 2.69
VPVD4 PVD threshold 4
Rising edge 2.68 2.74 2.79
Falling edge 2.77 2.83 2.88
VPVD5 PVD threshold 5
Rising edge 2.87 2.94 2.99
Falling edge 2.97 3.05 3.09
VPVD6 PVD threshold 6
Rising edge 3.08 3.15 3.20
BOR0 threshold - 40 -
Vhyst Hysteresis voltage All BOR and PVD mV
- 100 -
thresholds excepting BOR0
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option “D” in Ordering information scheme for more details.

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97
Electrical characteristics STM32L100RC

6.3.3 Embedded internal reference voltage

The parameters given in Table 15 are based on characterization results, unless otherwise
specified.

Table 14. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

Raw data acquired at

VREFINT_CAL temperature of 30 °C ±5 °C 0x1FF8 00F8 - 0x1FF8 00F9
VDDA= 3 V ±10 mV

Table 15. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT out (1)

Internal reference voltage – 40 °C < TJ < +110 °C 1.202 1.224 1.242 V
Internal reference current
IREFINT - - 1.4 2.3 µA
consumption
TVREFINT Internal reference startup time - - 2 3 ms
VDDA and VREF+ voltage during
VVREF_MEAS - 2.99 3 3.01 V
VREFINT factory measure
Including uncertainties
Accuracy of factory-measured VREF
AVREF_MEAS (2) due to ADC and - - ±5 mV
value
VDDA/VREF+ values
TCoeff(3) Temperature coefficient –40 °C < TJ < +110 °C - 25 100 ppm/°C
ACoeff(3) Long-term stability 1000 hours, T= 25 °C - - 1000 ppm
VDDCoeff(3) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V
ADC sampling time when reading
TS_vrefint(3) - 4 - - µs
the internal reference voltage
Startup time of reference voltage
TADC_BUF(3) - - - 10 µs
buffer for ADC
Consumption of reference voltage
IBUF_ADC(3) - - 13.5 25 µA
buffer for ADC
IVREF_OUT(3) VREF_OUT output current (4) - - - 1 µA
CVREF_OUT(3) VREF_OUT output load - - - 50 pF
Consumption of reference voltage
ILPBUF(3) - - 730 1200 nA
buffer for VREF_OUT and COMP
VREFINT_DIV1(3) 1/4 reference voltage - 24 25 26
%
VREFINT_DIV2(3) 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3(3) 3/4 reference voltage - 74 75 76
1. Guaranteed by test in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by characterization results.
4. To guarantee less than 1% VREF_OUT deviation.

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6.3.4 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 9: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature TA = 25 °C and VDD supply voltage conditions summarized in
Table 12: General operating conditions, unless otherwise specified.
The MCU is placed under the following conditions:
• All I/O pins are configured in analog input mode
• All peripherals are disabled except when explicitly mentioned.
• The Flash memory access time, 64-bit access and prefetch is adjusted depending on
fHCLK frequency and voltage range to provide the best CPU performance.
• When the peripherals are enabled fAPB1 = fAPB2 = fAHB.
• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
• The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 25: High-speed external user clock characteristics.
• For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins.
• For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise.

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Table 16. Current consumption in Run mode, code with data processing running from Flash
Symbol Parameter Conditions fHCLK Typ Max(1) Unit

1 MHz 215 400

Range 3, VCORE=1.2 V
2 MHz 400 600 µA
VOS[1:0] = 11
4 MHz 725 960
fHSE = fHCLK up to 16 4 MHz 0.915 1.1
MHz included, fHSE = Range 2, VCORE=1.5 V
8 MHz 1.75 2.1
fHCLK/2 above 16 MHz VOS[1:0] = 10
(PLL ON)(2) 16 MHz 3.4 3.9
Supply
IDD current in 8 MHz 2.1 2.8
(Run Run mode, Range 1, VCORE=1.8 V
16 MHz 4.2 4.9 mA
from code VOS[1:0] = 01
Flash) executed 32 MHz 8.25 9.4
from Flash Range 2, VCORE=1.5 V
16 MHz 3.5 4
HSI clock source (16 VOS[1:0] = 10
MHz) Range 1, VCORE=1.8 V
32 MHz 8.2 9.6
VOS[1:0] = 01
MSI clock, 65 kHz 65 kHz 40.5 110
Range 3, VCORE=1.2 V
MSI clock, 524 kHz 524 kHz 125 190 µA
VOS[1:0] = 11
MSI clock, 4.2 MHz 4.2 MHz 775 900
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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Table 17. Current consumption in Run mode, code with data processing running from RAM
Symbol Parameter Conditions fHCLK Typ Max(1) Unit

1 MHz 185 240

Range 3,
VCORE=1.2 V VOS[1:0] 2 MHz 345 410 µA
= 11 (3)
4 MHz 645 880
fHSE = fHCLK
up to 16 MHz, 4 MHz 0.755 1.4
Range 2,
included
VCORE=1.5 V VOS[1:0] 8 MHz 1.5 2.1
fHSE = fHCLK/2 above
= 10
16 MHz 16 MHz 3 3.5
(PLL ON)(2)
8 MHz 1.8 2.8
Supply current in Range 1,
IDD (Run Run mode, code VCORE=1.8 V 16 MHz 3.6 4.1
from executed from VOS[1:0] = 01 mA
32 MHz 7.15 8.3
RAM) RAM, Flash
switched off Range 2,
VCORE=1.5 V VOS[1:0] 16 MHz 2.95 3.5
HSI clock source (16 = 10
MHz) Range 1,
VCORE=1.8 V VOS[1:0] 32 MHz 7.15 8.4
= 01
MSI clock, 65 kHz 65 kHz 38.5 85
Range 3,
MSI clock, 524 kHz VCORE=1.2 V VOS[1:0] 524 kHz 110 160 µA
= 11
MSI clock, 4.2 MHz 4.2 MHz 690 810
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. Guaranteed by test in production.

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Table 18. Current consumption in Sleep mode

Symbol Parameter Conditions fHCLK Typ Max(1) Unit

1 MHz 50 130
Range 3,
VCORE=1.2 V 2 MHz 78.5 195
VOS[1:0] = 11
4 MHz 140 310
fHSE = fHCLK up to
4 MHz 165 310
16 MHz included, Range 2,
fHSE = fHCLK/2 VCORE=1.5 V 8 MHz 310 440
above 16 MHz (PLL VOS[1:0] = 10
16 MHz 590 830
ON)(2)
8 MHz 350 550
Range 1,
Supply current VCORE=1.8 V 16 MHz 680 990
in Sleep VOS[1:0] = 01
mode, Flash 32 MHz 1600 2100
OFF Range 2,
VCORE=1.5 V 16 MHz 640 890
HSI clock source VOS[1:0] = 10
(16 MHz) Range 1,
VCORE=1.8 V 32 MHz 1600 2200
VOS[1:0] = 01
MSI clock, 65 kHz 65 kHz 19 60
Range 3,
MSI clock, 524 kHz VCORE=1.2 V 524 kHz 33 99
VOS[1:0] = 11
MSI clock, 4.2 MHz 4.2 MHz 145 210
IDD (Sleep) µA
1 MHz 60.5 130
Range 3,
VCORE=1.2 V 2 MHz 89.5 190
VOS[1:0] = 11
4 MHz 150 320
fHSE = fHCLK up to
4 MHz 180 320
16 MHz included, Range 2,
fHSE = fHCLK/2 VCORE=1.5 V 8 MHz 320 460
above 16 MHz (PLL VOS[1:0] = 10
16 MHz 605 840
Supply current ON)(2)
in Sleep 8 MHz 380 540
Range 1,
mode, Flash
VCORE=1.8 V 16 MHz 695 1000
ON
VOS[1:0] = 01
32 MHz 1600 2100
Range 2,
VCORE=1.5 V 16 MHz 650 910
HSI clock source VOS[1:0] = 10
(16 MHz) Range 1,
VCORE=1.8 V 32 MHz 1600 2200
VOS[1:0] = 01
Supply current MSI clock, 65 kHz 65 kHz 30 90
Range 3,
in Sleep
MSI clock, 524 kHz VCORE=1.2V 524 kHz 44 96
mode, Flash
VOS[1:0] = 11
ON MSI clock, 4.2 MHz 4.2 MHz 155 220
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

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Table 19. Current consumption in Low-power run mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = -40 °C to 25 °C 8.6 12
MSI clock, 65 kHz
TA = 85 °C 19 25
fHCLK = 32 kHz
All
peripherals TA = 105 °C 35 47
OFF, code TA =-40 °C to 25 °C 14 16
executed MSI clock, 65 kHz
from RAM, TA = 85 °C 24 29
fHCLK = 65 kHz
Flash TA = 105 °C 40 51
switched
OFF, VDD TA = -40 °C to 25 °C 26 29
from 1.65 V TA = 55 °C 28 31
to 3.6 V MSI clock, 131 kHz
fHCLK = 131 kHz TA = 85 °C 36 42
Supply
IDD (LP current in TA = 105 °C 52 64
Run) Low-power TA = -40 °C to 25 °C 20 24
run mode MSI clock, 65 kHz
TA = 85 °C 32 37 µA
fHCLK = 32 kHz
All TA = 105 °C 49 61
peripherals TA = -40 °C to 25 °C 26 30
OFF, code MSI clock, 65 kHz
executed TA = 85 °C 38 44
fHCLK = 65 kHz
from Flash, TA = 105 °C 55 67
VDD from
1.65 V to TA = -40 °C to 25 °C 41 46
3.6 V TA = 55 °C 44 50
MSI clock, 131 kHz
fHCLK = 131 kHz TA = 85 °C 56 87
TA = 105 °C 73 110
Max allowed
VDD from
IDD max current in
1.65 V to - - - 200
(LP Run) Low-power
3.6 V
run mode
1. Guaranteed by characterization results, unless otherwise specified.

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Table 20. Current consumption in Low-power sleep mode

Symbol Parameter Conditions Typ Max(1) Unit

MSI clock, 65 kHz

fHCLK = 32 kHz TA = -40 °C to 25 °C 4.4 -
Flash OFF
TA = -40 °C to 25 °C 14 16
MSI clock, 65 kHz
fHCLK = 32 kHz TA = 85 °C 19 23
Flash ON
TA = 105 °C 27 33
All peripherals
TA = -40 °C to 25 °C 15 17
OFF, VDD from MSI clock, 65 kHz
1.65 V to 3.6 V fHCLK = 65 kHz, TA = 85 °C 20 23
Flash ON
TA = 105 °C 28 33
TA = -40 °C to 25 °C 17 19
MSI clock, 131 kHz T = 55 °C 18 21
A
Supply fHCLK = 131 kHz,
IDD current in Flash ON TA = 85 °C 22 25
(LP Sleep) Low-power
TA = 105 °C 30 35
sleep mode
TA = -40 °C to 25 °C 14 16 µA
MSI clock, 65 kHz
TA = 85 °C 19 22
fHCLK = 32 kHz
TA = 105 °C 27 32

TIM9 and TA = -40 °C to 25 °C 15 17

USART1 MSI clock, 65 kHz
TA = 85 °C 20 23
enabled, Flash fHCLK = 65 kHz
ON, VDD from TA = 105 °C 28 33
1.65 V to 3.6 V TA = -40 °C to 25 °C 17 19

MSI clock, 131 kHz TA = 55 °C 18 21

fHCLK = 131 kHz TA = 85 °C 22 25
TA = 105 °C 30 36
Max
allowed
IDD max VDD from 1.65 V
current in - - - 200
(LP Sleep) to 3.6 V
Low-power
sleep mode
1. Guaranteed by characterization results, unless otherwise specified.

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Table 21. Typical and maximum current consumptions in Stop mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = -40°C to 25°C
1.15 -
VDD = 1.8 V
TA = -40°C to 25°C 1.4 -
LCD
OFF TA = 55°C 2 -
TA= 85°C 3.4 10
RTC clocked by LSI TA = 105°C 6.35 23
or LSE external clock
(32.768kHz), TA = -40°C to 25°C 1.55 6
regulator in LP mode, LCD
ON TA = 55°C 2.15 7
HSI and HSE OFF
(no independent (static T = 85°C 3.55 12
A
watchdog) duty)(2)
TA = 105°C 6.3 27
TA = -40°C to 25°C 3.9 10
LCD TA = 55°C 4.65 11
ON (1/8
duty)(3) TA= 85°C 6.25 16
TA = 105°C 9.1 44
TA = -40°C to 25°C 1.5 -
Supply current in
IDD (Stop TA = 55°C 2.15 -
Stop mode with RTC LCD µA
with RTC)
enabled OFF TA= 85°C 3.7 -
TA = 105°C 6.75 -
TA = -40°C to 25°C 1.6 -
LCD
ON TA = 55°C 2.3 -
RTC clocked by LSE (static T = 85°C 3.8 -
A
external quartz duty)(2)
TA = 105°C 6.85 -
(32.768kHz),
regulator in LP mode, TA = -40°C to 25°C 4 -
HSI and HSE OFF LCD
(no independent TA = 55°C 4.85 -
ON (1/8
watchdog(4) duty)(3) TA= 85°C 6.5 -
TA = 105°C 9.1 -
TA = -40°C to 25°C
1.2 -
VDD = 1.8V
LCD TA = -40°C to 25°C
1.5 -
OFF VDD = 3.0V
TA = -40°C to 25°C
1.75 -
VDD = 3.6V

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Table 21. Typical and maximum current consumptions in Stop mode (continued)
Symbol Parameter Conditions Typ Max(1) Unit

Regulator in LP mode, HSI and

HSE OFF, independent TA = -40°C to 25°C 1.8 2.2
watchdog and LSI enabled
Supply current in
TA = -40°C to 25°C 0.435 1
IDD (Stop) Stop mode (RTC µA
disabled) Regulator in LP mode, LSI, HSI T = 55°C 0.99 3
A
and HSE OFF (no independent
watchdog) TA= 85°C 2.4 9
TA = 105°C 5.5 22(5)
MSI = 4.2 MHz 2 -
IDD Supply current during
(WU from wakeup from Stop MSI = 1.05 MHz TA = -40°C to 25°C 1.45 - mA
Stop) mode
MSI = 65 kHz(6) 1.45 -
1. Guaranteed by characterization results, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. Guaranteed by test in production.
6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.

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Table 22. Typical and maximum current consumptions in Standby mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = -40 °C to 25 °C
0.905 -
VDD = 1.8 V
T = -40 °C to 25 °C 1.15 1.9
RTC clocked by LSI (no A
independent watchdog) TA = 55 °C 1.5 2.2
TA= 85 °C 1.75 4
IDD Supply current in TA = 105 °C 2.1 8.3(2)
(Standby Standby mode with RTC
with RTC) enabled TA = -40 °C to 25 °C
0.98 -
VDD = 1.8 V
RTC clocked by LSE
TA = -40 °C to 25 °C 1.3 -
external quartz (no
µA
independent TA = 55 °C 1.7 -
watchdog)(3)
TA= 85 °C 2.05 -
TA = 105 °C 2.45 -
Independent watchdog
TA = -40 °C to 25 °C 1 1.7
and LSI enabled
Supply current in TA = -40 °C to 25 °C 0.29 0.6
IDD
Standby mode (RTC
(Standby) Independent watchdog TA = 55 °C 0.345 0.9
disabled)
and LSI OFF TA = 85 °C 0.575 2.75
TA = 105 °C 1.45 7(2)
IDD Supply current during
(WU from wakeup time from - TA = -40 °C to 25 °C 1 - mA
Standby) Standby mode
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
• all I/O pins are in input mode with a static value at VDD or VSS (no load)
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on

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Table 23. Peripheral current consumption(1)

Typical consumption, VDD = 3.0 V, TA = 25 °C

Range 1, Range 2, Range 3,

Peripheral VCORE= VCORE= VCORE= Low-power Unit
1.8 V 1.5 V 1.2 V sleep and
VOS[1:0] = VOS[1:0] = VOS[1:0] = run
01 10 11

TIM2 11.2 8.9 7.0 8.9

TIM3 11.2 9.0 7.1 9.0
TIM4 12.9 10.4 8.2 10.4
TIM5 14.4 11.5 9.0 11.5
TIM6 4.0 3.1 2.4 3.1
TIM7 3.8 3.0 2.3 3.0
LCD 5.8 4.6 3.6 4.6
WWDG 2.9 2.3 1.8 2.3
SPI2 6.5 5.2 4.1 5.2 µA/MHz
APB1
SPI3 5.9 4.6 3.6 4.6 (fHCLK)

USART2 8.8 7.0 5.5 7.0

USART3 8.4 6.8 5.3 6.8
I2C1 7.3 5.8 4.6 5.8
I2C2 7.9 6.3 5.0 6.3
USB 13.3 10.6 8.3 10.6
PWR 2.8 2.2 1.8 2.2
DAC 6.1 4.9 3.9 4.9
COMP 4.8 3.8 3.0 3.8

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Table 23. Peripheral current consumption(1) (continued)

Typical consumption, VDD = 3.0 V, TA = 25 °C

Range 1, Range 2, Range 3,

Peripheral VCORE= VCORE= VCORE= Low-power Unit
1.8 V 1.5 V 1.2 V sleep and
VOS[1:0] = VOS[1:0] = VOS[1:0] = run
01 10 11

SYSCFG &
2.6 2.0 1.6 2.0
RI
TIM9 7.9 6.4 5.0 6.4
TIM10 5.9 4.7 3.8 4.7
APB2
TIM11 5.9 4.6 3.7 4.6
(2)
ADC 10.5 8.3 6.6 8.3
SPI1 4.3 3.4 2.8 3.4
USART1 8.8 7.1 5.6 7.1
GPIOA 4.3 3.3 2.6 3.3
GPIOB 4.3 3.5 2.8 3.5 µA/MHz
(fHCLK)
GPIOC 4.0 3.2 2.5 3.2
GPIOD 4.1 3.3 2.5 3.3
GPIOE 4.2 3.4 2.7 3.4
AHB
GPIOH 3.7 3.0 2.3 3.0
CRC 0.8 0.6 0.5 0.6
FLASH 11.1 9.4 8 -(3)
DMA1 15.6 12.7 10 12.7
DMA2 16.3 13.4 10.5 13.4
All enabled 187 154 120 144.6
IDD (RTC) 0.4
IDD (LCD) 3.1
IDD (ADC)(4) 1450
IDD (DAC)(5) 340
IDD (COMP1) 0.16 µA
Slow mode 2
IDD (COMP2)
Fast mode 5
IDD (PVD / BOR)(6) 2.6
IDD (IWDG) 0.25
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling.
2. HSI oscillator is OFF for this measure.

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3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.

6.3.5 Wakeup time from low-power mode

The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
• Sleep mode: the clock source is the clock that was set before entering Sleep mode
• Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under the conditions summarized in Table 12.

Table 24. Low-power mode wakeup timings

Symbol Parameter Conditions Typ Max(1) Unit

tWUSLEEP Wakeup from Sleep mode fHCLK = 32 MHz 0.4 -

fHCLK = 262 kHz
46 -
Wakeup from Low-power sleep Flash enabled
tWUSLEEP_LP
mode, fHCLK = 262 kHz fHCLK = 262 kHz
46 -
Flash switched OFF
Wakeup from Stop mode,
regulator in Run mode fHCLK = fMSI = 4.2 MHz 8.2 -
ULP bit = 1 and FWU bit = 1
fHCLK = fMSI = 4.2 MHz
7.7 8.9
Voltage range 1 and 2
fHCLK = fMSI = 4.2 MHz µs
8.2 13.1
Voltage range 3
tWUSTOP
Wakeup from Stop mode, fHCLK = fMSI = 2.1 MHz 10.2 13.4
regulator in low-power mode fHCLK = fMSI = 1.05 MHz 16 20
ULP bit = 1 and FWU bit = 1
fHCLK = fMSI = 524 kHz 31 37
fHCLK = fMSI = 262 kHz 57 66
fHCLK = fMSI = 131 kHz 112 123
fHCLK = MSI = 65 kHz 221 236
Wakeup from Standby mode
fHCLK = MSI = 2.1 MHz 58 104
ULP bit = 1 and FWU bit = 1
tWUSTDBY
Wakeup from Standby mode
fHCLK = MSI = 2.1 MHz 2.6 3.25 ms
FWU bit = 0
1. Guaranteed by characterization, unless otherwise specified

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6.3.6 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 10.

Table 25. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

CSS is on or
1 8 32 MHz
User external clock source PLL is used
fHSE_ext
frequency CSS is off, PLL
0 8 32 MHz
not used
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
tw(HSEH)
OSC_IN high or low time 12 - -
tw(HSEL) -
ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
Cin(HSE) OSC_IN input capacitance - 2.6 - pF
1. Guaranteed by design.

Figure 10. High-speed external clock source AC timing diagram

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9+6(+


9+6(/

WU +6( W
WI +6( WZ +6(/
7+6(

069

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Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under the conditions summarized in Table 12.

Table 26. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext 1 32.768 1000 kHz
frequency
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL - VSS - 0.3VDD
voltage
tw(LSEH)
OSC32_IN high or low time 465 - -
tw(LSEL)
ns
tr(LSE)
OSC32_IN rise or fall time - - 10
tf(LSE)
CIN(LSE) OSC32_IN input capacitance - - 0.6 - pF
1. Guaranteed by design.

Figure 11. Low-speed external clock source AC timing diagram

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9/6(+


9/6(/

WU /6( W
WI /6( WZ /6(/
7/6(

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 27. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

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Table 27. HSE oscillator characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency - 1 24 MHz

RF Feedback resistor - - 200 - kΩ
Recommended load
capacitance versus
C equivalent serial RS = 30 Ω - 20 - pF
resistance of the crystal
(RS)(3)
VDD= 3.3 V,
IHSE HSE driving current VIN = VSS with 30 pF - - 3 mA
load
C = 20 pF 2.5 (startup)
- -
HSE oscillator power fOSC = 16 MHz 0.7 (stabilized)
IDD(HSE) mA
consumption C = 10 pF 2.5 (startup)
- -
fOSC = 16 MHz 0.46 (stabilized)
Oscillator
gm Startup 3.5 - - mA /V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 1 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 12). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.

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Figure 12. HSE oscillator circuit diagram

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Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 28. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 28. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions Min Typ Max Unit

Low speed external oscillator

fLSE - - 32.768 - kHz
frequency
RF Feedback resistor - - 1.2 - MΩ
Recommended load capacitance
C(2) versus equivalent serial RS = 30 kΩ - 8 - pF
resistance of the crystal (RS)(3)
ILSE LSE driving current VDD = 3.3 V, VIN = VSS - - 1.1 µA
VDD = 1.8 V - 450 -
LSE oscillator current
IDD (LSE) VDD = 3.0 V - 600 - nA
consumption
VDD = 3.6V - 750 -
gm Oscillator transconductance - 3 - - µA/V
tSU(LSE) (4) Startup time VDD is stabilized - 1 - s
1. Guaranteed by characterization results.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.

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Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 13).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if the user chooses a resonator with a load capacitance of CL = 6 pF and
Cstray = 2 pF, then CL1 = CL2 = 8 pF.

Figure 13. Typical application with a 32.768 kHz crystal

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6.3.7 Internal clock source characteristics

The parameters given in Table 29 are derived from tests performed under the conditions
summarized in Table 12.

High-speed internal (HSI) RC oscillator

Table 29. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency VDD = 3.0 V - 16 - MHz

HSI user-trimmed Trimming code is not a multiple of 16 - ± 0.4 0.7 %

(1)(2)
TRIM resolution Trimming code is a multiple of 16 - - ± 1.5 %
VDDA = 3.0 V, TA = 25 °C -1(3) - 1(3) %
VDDA = 3.0 V, TA = 0 to 55 °C -1.5 - 1.5 %

Accuracy of the VDDA = 3.0 V, TA = -10 to 70 °C -2 - 2 %

ACCHSI(2) factory-calibrated VDDA = 3.0 V, TA = -10 to 85 °C -2.5 - 2 %
HSI oscillator
VDDA = 3.0 V, TA = -10 to 105 °C -4 - 2 %
VDDA = 1.65 V to 3.6 V
-4 - 3 %
TA = -40 to 105 °C
HSI oscillator
tSU(HSI)(2) - - 3.7 6 µs
startup time
HSI oscillator
IDD(HSI)(2) - - 100 140 µA
power consumption
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.

Low-speed internal (LSI) RC oscillator

Table 30. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

fLSI(1) LSI frequency 26 38 56 kHz

LSI oscillator frequency drift
DLSI(2) -10 - 4 %
0°C ≤TA ≤ 105°C
tsu(LSI)(3) LSI oscillator startup time - - 200 µs
IDD(LSI) (3) LSI oscillator power consumption - 400 510 nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.

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Multi-speed internal (MSI) RC oscillator

Table 31. MSI oscillator characteristics

Symbol Parameter Condition Typ Max Unit

MSI range 0 65.5 -

MSI range 1 131 -
kHz
MSI range 2 262 -
Frequency after factory calibration, done at
fMSI MSI range 3 524 -
VDD= 3.3 V and TA = 25 °C
MSI range 4 1.05 -
MSI range 5 2.1 - MHz
MSI range 6 4.2 -
ACCMSI Frequency error after factory calibration - ±0.5 - %
MSI oscillator frequency drift
DTEMP(MSI)(1) - ±3 - %
0 °C ≤TA ≤105 °C
MSI oscillator frequency drift
DVOLT(MSI)(1) - - 2.5 %/V
1.65 V ≤VDD ≤3.6 V, TA = 25 °C
MSI range 0 0.75 -
MSI range 1 1 -
MSI range 2 1.5 -
IDD(MSI)(2) MSI oscillator power consumption MSI range 3 2.5 - µA
MSI range 4 4.5 -
MSI range 5 8 -
MSI range 6 15 -
MSI range 0 30 -
MSI range 1 20 -
MSI range 2 15 -
MSI range 3 10 -
MSI range 4 6 -
tSU(MSI) MSI oscillator startup time µs
MSI range 5 5 -
MSI range 6,
Voltage range 1 3.5 -
and 2
MSI range 6,
5 -
Voltage range 3

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Table 31. MSI oscillator characteristics (continued)

Symbol Parameter Condition Typ Max Unit

MSI range 0 - 40
MSI range 1 - 20
MSI range 2 - 10
MSI range 3 - 4
MSI range 4 - 2.5
tSTAB(MSI)(2) MSI oscillator stabilization time µs
MSI range 5 - 2
MSI range 6,
Voltage range 1 - 2
and 2
MSI range 3,
- 3
Voltage range 3
Any range to
- 4
range 5
fOVER(MSI) MSI oscillator frequency overshoot MHz
Any range to
- 6
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.

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6.3.8 PLL characteristics

The parameters given in Table 32 are derived from tests performed under the conditions
summarized in Table 12.

Table 32. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max(1)

PLL input clock(2) 2 - 24 MHz

fPLL_IN
PLL input clock duty cycle 45 - 55 %
fPLL_OUT PLL output clock 2 - 32 MHz
PLL lock time
tLOCK PLL input = 16 MHz - 115 160 µs
PLL VCO = 96 MHz
Jitter Cycle-to-cycle jitter - - ± 600 ps
IDDA(PLL) Current consumption on VDDA - 220 450
µA
IDD(PLL) Current consumption on VDD - 120 150
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.

6.3.9 Memory characteristics

The characteristics are given at TA = -40 to 105 °C unless otherwise specified.

RAM memory

Table 33. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode(1) STOP mode (or RESET) 1.65 - - V

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).

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Flash memory and data EEPROM

Table 34. Flash memory and data EEPROM characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

Operating voltage
VDD - 1.65 - 3.6 V
Read / Write / Erase
Programming/ erasing Erasing - 3.28 3.94
tprog time for byte / word / ms
double word / half-page Programming - 3.28 3.94

Average current during

the whole programming / - 600 µA
erase operation
IDD Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
- 1.5 2.5 mA
programming / erase
operation
1. Guaranteed by design.

Table 35. Flash memory and data EEPROM endurance and retention
Value
Symbol Parameter Conditions Unit
Min(1) Typ Max

Cycling (erase / write)

10 - -
Program memory TA = -40°C to
NCYC(2) kcycles
Cycling (erase / write) 105 °C
300 - -
EEPROM data memory
Data retention (program memory) after
30 - -
10 kcycles at TA = 85 °C
TRET = +85 °C
Data retention (EEPROM data memory)
30 - -
after 300 kcycles at TA = 85 °C
(2)
tRET years
Data retention (program memory) after
10 - -
10 kcycles at TA = 105 °C
TRET = +105 °C
Data retention (EEPROM data memory)
10 - -
after 300 kcycles at TA = 105 °C
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.

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6.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 36. They are based on the EMS levels and classes
defined in application note AN1709.

Table 36. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, , TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 32 MHz 2B
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, , TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 32 MHz 4A
pins to induce a functional disturbance conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.

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To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 37. EMI characteristics

Max vs. frequency range
Monitored 4 MHz 16 MHz 32 MHz
Symbol Parameter Conditions Unit
frequency band
voltage voltage voltage
range 3 range 2 range 1

VDD = V, 0.1 to 30 MHz 3 -6 -5

TA = 25 °C, 30 to 130 MHz 18 4 -7 dBµV
SEMI Peak level package
compliant with IEC 130 MHz to 1GHz 15 5 -7
61967-2 SAE EMI Level 2.5 2 1 -

6.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard.

Table 38. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic
TA = +25 °C, conforming
VESD(HBM) discharge voltage 2 2000 V
to JESD22-A114
(human body model)
Electrostatic
TA = +25 °C, conforming
VESD(CDM) discharge voltage C4 500 V
to ANSI/ESD STM5.3.1.
(charge device model)
1. Guaranteed by characterization results.

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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 39. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II level A

6.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).
The test results are given in the Table 40.

Table 40. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on all 5 V tolerant (FT) pins -5 (1) NA(2)

IINJ Injected current on BOOT0 -0 NA(2) mA
(1)
Injected current on any other pin -5 +5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
2. Injection is not possible.

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6.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL
compliant.

Table 41. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

TC and FT I/O - - 0.3 VDD(1)(2)

VIL Input low level voltage
BOOT0 - - 0.14 VDD(2)
TC I/O 0.45 VDD+0.38(2) - -
VIH Input high level voltage FT I/O 0.39 VDD+0.59(2) - - V
BOOT0 0.15 VDD+0.56(2) - -

I/O Schmitt trigger voltage TC and FT I/O - 10% VDD(3) -

Vhys
hysteresis(2) BOOT0 - 0.01 -
VSS ≤VIN ≤VDD
- - ±50
I/Os with LCD
VSS ≤VIN ≤VDD
I/Os with analog - - ±50
switches
VSS ≤VIN ≤VDD
nA
I/Os with analog - - ±50
Ilkg (4)
Input leakage current switches and LCD
VSS ≤VIN ≤VDD
- - ±250
I/Os with USB
VSS ≤VIN ≤VDD
- - ±50
TC and FT I/Os
FT I/O
- - ±10 µA
VDD ≤VIN ≤5V
Weak pull-up equivalent
RPU VIN = VSS 25 45 65 kΩ
resistor(5)(1)
Weak pull-down equivalent
RPD VIN = VDD 25 45 65 kΩ
resistor(5)
CIO I/O pin capacitance - - 5 - pF
1. Guaranteed by test in production.
2. Guaranteed by design.
3. With a minimum of 200 mV.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA with the non-standard VOL/VOH specifications given in Table 42.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 10).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 10).

Output voltage levels

Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL
compliant.

Table 42. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

VOL(1)(2) Output low level voltage for an I/O pin IIO = 8 mA - 0.4
VOH (2)(3)
Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V VDD-0.4 -
VOL (3)(4) Output low level voltage for an I/O pin IIO = 4 mA - 0.45
V
VOH (3)(4) Output high level voltage for an I/O pin 1.65 V < VDD < 3.6 V V -0.45 -
DD

VOL(1)(4) Output low level voltage for an I/O pin IIO = 20 mA - 1.3
VOH (3)(4) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V VDD-1.3 -
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 10
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Guaranteed by test in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 10 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Guaranteed by characterization results.

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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 14 and
Table 43, respectively.
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 12.

Table 43. I/O AC characteristics(1)

OSPEEDRx
[1:0] bit Symbol Parameter Conditions Min Max(2) Unit
value(1)

CL = 50 pF, VDD = 2.7 V to 3.6 V - 400

fmax(IO)out Maximum frequency(3) kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 400
00
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 625
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 625
CL = 50 pF, VDD = 2.7 V to 3.6 V - 2
fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 1
01
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 125
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 250
CL = 50 pF, VDD = 2.7 V to 3.6 V - 10
Fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 2
10
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 25
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 125
CL = 30 pF, VDD = 2.7 V to 3.6 V - 50
Fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 8
11
tf(IO)out CL = 30 pF, VDD = 2.7 V to 3.6 V - 5
Output rise and fall time
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 30
ns
Pulse width of external
- tEXTIpw signals detected by the - 8 -
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 14.

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Figure 14. I/O AC characteristics definition

 

 

 

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6.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 44)
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 12.

Table 44. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

NRST input low level

VIL(NRST)(1) - - - 0.3 VDD
voltage
NRST input high
VIH(NRST)(1) - 0.39VDD+0.59 - -
level voltage
V
IOL = 2 mA
- -
NRST output low 2.7 V < VDD < 3.6 V
VOL(NRST)(1) 0.4
level voltage IOL = 1.5 mA
- -
1.65 V < VDD < 2.7 V
NRST Schmitt trigger
Vhys(NRST)(1) - - 10%VDD(2) - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 45 65 kΩ
equivalent resistor(3)
NRST input filtered
VF(NRST)(1) - - - 50 ns
pulse
NRST input not
VNF(NRST)(3) - 350 - - ns
filtered pulse
1. Guaranteed by design.
2. With a minimum of 200 mV.
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.

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Figure 15. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 44. Otherwise the reset will not be taken into account by the device.

6.3.15 TIM timer characteristics

The parameters given in the Table 45 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction
characteristics (output compare, input capture, external clock, PWM output).

Table 45. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 32 MHz 31.25 - ns

Timer external clock - 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz 0 16 MHz
ResTIM Timer resolution - 16 bit
16-bit counter clock - 1 65536 tTIMxCLK
period when internal clock
tCOUNTER
is selected (timer’s fTIMxCLK = 32 MHz 0.0312 2048 µs
prescaler disabled)
- - 65536 × 65536 tTIMxCLK
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz - 134.2 s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

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6.3.16 Communications interfaces

I2C interface characteristics
The device I2C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 46. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output ction characteristics (SDA and SCL).

Table 46. I2C characteristics

Standard mode
Fast mode I2C(1)(2)
I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max

tw(SCLL) SCL clock low time 4.7 - 1.3 -

µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time - 3450(3) - 900(3)
tr(SDA) ns
SDA and SCL rise time - 1000 - 300
tr(SCL)
tf(SDA)
SDA and SCL fall time - 300 - 300
tf(SCL)
th(STA) Start condition hold time 4.0 - 0.6 -
Repeated Start condition µs
tsu(STA) 4.7 - 0.6 -
setup time
tsu(STO) Stop condition setup time 4.0 - 0.6 - μs
Stop to Start condition time
tw(STO:STA) 4.7 - 1.3 - μs
(bus free)
Capacitive load for each bus
Cb - 400 - 400 pF
line
Pulse width of spikes that
tSP are suppressed by the 0 50(4) 0 50(4) ns
analog filter
1. Guaranteed by design.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).

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Figure 16. I2C bus AC waveforms and measurement circuit

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1. RS = series protection resistor.

2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

Table 47. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ

400 0x801B
300 0x8024
200 0x8035
100 0x00A0
50 0x0140
20 0x0320
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.

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SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the conditions summarized in Table 12.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 48. SPI characteristics(1)

Symbol Parameter Conditions Min Max(2) Unit

Master mode - 16
fSCK
SPI clock frequency Slave mode - 16 MHz
1/tc(SCK)
Slave transmitter - 12(3)
tr(SCK)(2)
SPI clock rise and fall time Capacitive load: C = 30 pF - 6 ns
tf(SCK)(2)
DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 %
tsu(NSS) NSS setup time Slave mode 4tHCLK -
th(NSS) NSS hold time Slave mode 2tHCLK -
tw(SCKH)(2)
SCK high and low time Master mode tSCK/2 − 5 tSCK/2 +3
tw(SCKL)(2)
tsu(MI)(2) Master mode 5 -
Data input setup time
tsu(SI)(2) Slave mode 6 -
(2)
th(MI) Master mode 5 - ns
Data input hold time
(2)
th(SI) Slave mode 5 -
ta(SO)(4) Data output access time Slave mode 0 3tHCLK
tv(SO) (2) Data output valid time Slave mode - 33
(2)
tv(MO) Data output valid time Master mode - 6.5
(2)
th(SO) Slave mode 17 -
Data output hold time
th(MO)(2) Master mode 0.5 -
1. The characteristics above are given for voltage range 1.
2. Guaranteed by characterization results.
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

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Electrical characteristics STM32L100RC

Figure 17. SPI timing diagram - slave mode and CPHA = 0

Figure 18. SPI timing diagram - slave mode and CPHA = 1(1)

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Figure 19. SPI timing diagram - master mode(1)

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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Electrical characteristics STM32L100RC

USB characteristics
The USB interface is USB-IF certified (full speed).

Table 49. USB startup time

Symbol Parameter Max Unit

tSTARTUP (1) USB transceiver startup time 1 µs

1. Guaranteed by design.

Table 50. USB DC electrical characteristics

Symbol Parameter Conditions Min.(1) Max.(1) Unit

Input levels

VDD USB operating voltage - 3.0 3.6 V

VDI(2) Differential input sensitivity I(USB_DP, USB_DM) 0.2 -
VCM(2) Differential common mode range Includes VDI range 0.8 2.5 V
VSE(2) Single ended receiver threshold - 1.3 2.0

Output levels

VOL(3) Static output level low RL of 1.5 kΩ to 3.6 V(4) - 0.3

V
(3) (4)
VOH Static output level high RL of 15 kΩ to VSS 2.8 3.6
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
4. RL is the load connected on the USB drivers.

Figure 20. USB timings: definition of data signal rise and fall time
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Table 51. USB: full speed electrical characteristics

Driver characteristics(1)

Symbol Parameter Conditions Min Max Unit

tr Rise time(2) CL = 50 pF 4 20 ns
tf Fall Time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V

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1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).

I2S characteristics

Table 52. I2S characteristics

Symbol Parameter Conditions Min Max Unit

fMCK I2S Main Clock Output 256 x 8K 256xFs (1) MHz

Master data: 32 bits - 64xFs
fCK I2S clock frequency MHz
Slave data: 32 bits - 64xFs
DCK I2S clock frequency duty cycle Slave receiver, 48KHz 30 70 %
tr(CK) I2S clock rise time 8
Capacitive load CL=30pF -
tf(CK) I2S clock fall time 8
tv(WS) WS valid time Master mode 4 24
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 15 -
th(WS) WS hold time Slave mode 0 -
tsu(SD_MR) Data input setup time Master receiver 8 -
tsu(SD_SR) Data input setup time Slave receiver 9 -
th(SD_MR) Master receiver 5 - ns
Data input hold time
th(SD_SR) Slave receiver 4 -
Slave transmitter
tv(SD_ST) Data output valid time - 64
(after enable edge)
Slave transmitter
th(SD_ST) Data output hold time 22 -
(after enable edge)
Master transmitter
tv(SD_MT) Data output valid time - 12
(after enable edge)
Master transmitter
th(SD_MT) Data output hold time 8 -
(after enable edge)
1. The maximum for 256xFs is 8 MHz

Note: Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.

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Figure 21. I2S slave timing diagram (Philips protocol)(1)

1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 22. I2S master timing diagram (Philips protocol)(1)

1. Guaranteed by characterization results.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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6.3.17 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 54 are guaranteed by design.

Table 53. ADC clock frequency

Symbol Parameter Conditions Min Max Unit

VREF+ = VDDA 16
VREF+ < VDDA
8
2.4 V ≤VDDA ≤3.6 V VREF+ > 2.4 V
Voltage
ADC clock VREF+ < VDDA
fADC range 1 & 2 0.480 4 MHz
frequency VREF+ ≤2.4 V
VREF+ = VDDA 8
1.8 V ≤VDDA ≤2.4 V
VREF+ < VDDA 4
Voltage range 3 4

Table 54. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Power supply - 1.8 - 3.6

VREF+ Positive reference voltage - 1.8(1) - VDDA V
VREF- Negative reference voltage - - VSSA -
IVDDA Current on the VDDA input pin - - 1000 1450
µA
Peak - 700
IVREF(2) Current on the VREF input pin 400
Average 450
VAIN Conversion voltage range(3) - 0(4) - VREF+ V
Direct channels - - 1
12-bit sampling rate Msps
Multiplexed channels - - 0.76
Direct channels - - 1.07
10-bit sampling rate Msps
Multiplexed channels - - 0.8
fS
Direct channels - - 1.23
8-bit sampling rate Msps
Multiplexed channels - - 0.89
Direct channels - - 1.45
6-bit sampling rate Msps
Multiplexed channels - - 1

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Table 54. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Direct channels
0.25 - -
2.4 V ≤VDDA ≤3.6 V
Multiplexed channels
0.56 - -
2.4 V ≤VDDA ≤3.6 V
µs
tS(5) Sampling time Direct channels
0.56 - -
1.8 V ≤VDDA ≤2.4 V
Multiplexed channels
1 - -
1.8 V ≤VDDA ≤2.4 V
- 4 - 384 1/fADC
fADC = 16 MHz 1 - 24.75 µs
Total conversion time
tCONV 4 to 384 (sampling phase) +12
(including sampling time) - 1/fADC
(successive approximation)

Internal sample and hold Direct channels - -

CADC 16 pF
capacitor Multiplexed channels - -

External trigger frequency 12-bit conversions - - Tconv+1 1/fADC

fTRIG
Regular sequencer 6/8/10-bit conversions - - Tconv 1/fADC

External trigger frequency 12-bit conversions - - Tconv+2 1/fADC

fTRIG
Injected sequencer 6/8/10-bit conversions - - Tconv+1 1/fADC
RAIN(6) Signal source impedance - - 50 kΩ

Injection trigger conversion fADC = 16 MHz 219 - 281 ns

tlat
latency - 3.5 - 4.5 1/fADC

Regular trigger conversion fADC = 16 MHz 156 - 219 ns

tlatr
latency - 2.5 - 3.5 1/fADC
tSTAB Power-up time - - - 3.5 µs
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage
reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 56: Maximum
source impedance RAIN max.
6. External impedance has another high value limitation when using short sampling time as defined in Table 56: Maximum
source impedance RAIN max.

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Table 55. ADC accuracy(1)(2)

Symbol Parameter Test conditions Min(3) Typ Max(3) Unit

ET Total unadjusted error - 4

EO Offset error 2.4 V ≤ VDDA ≤ 3.6 V - 1 2
2.4 V ≤ VREF+ ≤ 3.6 V
EG Gain error - 1.5 3.5 LSB
fADC = 8 MHz, RAIN = 50 Ω
ED Differential linearity error TA = -40 to 105 ° C - 1 2
EL Integral linearity error - 3
ENOB Effective number of bits 9.2 10 - bits
2.4 V ≤ VDDA ≤ 3.6 V
Signal-to-noise and VDDA = VREF+
SINAD 57.5 62 -
distortion ratio fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C dB
SNR Signal-to-noise ratio 57.5 62 -
Finput=10kHz
THD Total harmonic distortion - -70 -65
ENOB Effective number of bits 9.2 10 - bits
1.8 V ≤ VDDA ≤ 2.4 V
Signal-to-noise and VDDA = VREF+
SINAD 57.5 62 -
distortion ratio fADC = 8 MHz or 4 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C dB
SNR Signal-to-noise ratio 57.5 62 -
Finput=10kHz
THD Total harmonic distortion - -70 -65
ET Total unadjusted error - 4 6.5
EO Offset error 2.4 V ≤ VDDA ≤ 3.6 V - 2 4
1.8 V ≤ VREF+ ≤ 2.4 V
EG Gain error - 4 6 LSB
fADC = 4 MHz, RAIN = 50 Ω
ED Differential linearity error TA = -40 to 105 ° C - 1 2
EL Integral linearity error - 1.5 3
ET Total unadjusted error - 2 3
EO Offset error 1.8 V ≤ VDDA ≤ 2.4 V - 1 1.5
1.8 V ≤ VREF+ ≤ 2.4 V
EG Gain error - 1.5 2 LSB
fADC = 4 MHz, RAIN = 50 Ω
ED Differential linearity error TA = -40 to 105 ° C - 1 2
EL Integral linearity error - 1 1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as
this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Guaranteed by characterization results.

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Electrical characteristics STM32L100RC

Figure 23. ADC accuracy characteristics

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1. Refer to Table 56: Maximum source impedance RAIN max for the value of RAIN and Table 54: ADC
characteristics for the value of CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

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Figure 25. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion

Sampling (n cycles) Conversion (12 cycles)

ADC clock

Iref+

700µA

300µA

MS36686V1

Table 56. Maximum source impedance RAIN max(1)

RAIN max (kΩ)
Ts Ts (cycles)
Multiplexed channels Direct channels
(µs) fADC=16 MHz(2)
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V

0.25 Not allowed Not allowed 0.7 Not allowed 4

0.5625 0.8 Not allowed 2.0 1.0 9
1 2.0 0.8 4.0 3.0 16
1.5 3.0 1.8 6.0 4.5 24
3 6.8 4.0 15.0 10.0 48
6 15.0 10.0 30.0 20.0 96
12 32.0 25.0 50.0 40.0 192
24 50.0 50.0 50.0 50.0 384
1. Guaranteed by design.
2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced
with respect to the minimum sampling time Ts (µs),

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 7. The applicable
procedure depends on whether VREF+ is connected to VDDA or not. The 100 nF capacitors
should be ceramic (good quality). They should be placed as close as possible to the chip.

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Electrical characteristics STM32L100RC

6.3.18 DAC electrical specifications

Data guaranteed by design, unless otherwise specified.

Table 57. DAC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 - 3.6

Reference supply VREF+ must always be below V

VREF+ 1.8 - 3.6
voltage VDDA
VREF- Lower reference voltage - VSSA
Current consumption on No load, middle code (0x800) - 130 220
IDDVREF+(1) VREF+ supply
VREF+ = 3.3 V No load, worst code (0x000) - 220 350
µA
Current consumption on No load, middle code (0x800) - 210 320
IDDA(1) VDDA supply
VDDA = 3.3 V No load, worst code (0xF1C) - 320 520

Connected to
5 - -
DAC output VSSA
RL Resistive load kΩ
buffer ON Conected to
25 - -
VDDA
(2)
CL Capacitive load DAC output buffer ON - - 50 pF
RO Output impedance DAC output buffer OFF 12 16 20 kΩ

DAC output buffer ON 0.2 - VDDA – 0.2 V

Voltage on DAC_OUT
VDAC_OUT
output
VREF+ –
DAC output buffer OFF 0.5 - mV
1LSB

CL ≤ 50 pF, RL ≥ 5 kΩ
- 1.5 3
Differential non DAC output buffer ON
DNL(1)
linearity(3)
No RL, CL ≤ 50 pF
- 1.5 3
DAC output buffer OFF
CL ≤ 50 pF, RL ≥ 5 kΩ
- 2 4
DAC output buffer ON
INL(1) Integral non linearity(4)
No RL, CL ≤ 50 pF LSB
- 2 4
DAC output buffer OFF
CL ≤ 50 pF, RL ≥ 5 kΩ
- ±10 ±25
Offset error at code DAC output buffer ON
Offset(1)
0x800 (5) No RL, CL ≤ 50 pF
- ±5 ±8
DAC output buffer OFF
Offset error at code No RL, CL ≤ 50 pF
Offset1(1) - ±1.5 ±5
0x001(6) DAC output buffer OFF

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Table 57. DAC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

VDDA = 3.3V
VREF+ = 3.0V
-20 -10 0
TA = 0 to 50 ° C
Offset error temperature DAC output buffer OFF
dOffset/dT(1) µV/°C
coefficient (code 0x800) V = 3.3V
DDA
VREF+ = 3.0V
0 20 50
TA = 0 to 50 ° C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
- +0.1 / -0.2% +0.2 / -0.5%
DAC output buffer ON
Gain(1) Gain error(7) %
No RL, CL ≤ 50 pF
- +0 / -0.2% +0 / -0.4%
DAC output buffer OFF
VDDA = 3.3V
VREF+ = 3.0V
-10 -2 0
TA = 0 to 50 ° C
Gain error temperature DAC output buffer OFF
dGain/dT(1) µV/°C
coefficient VDDA = 3.3V
VREF+ = 3.0V
-40 -8 0
TA = 0 to 50 ° C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
- 12 30
DAC output buffer ON
TUE(1) Total unadjusted error LSB
No RL, CL ≤ 50 pF
- 8 12
DAC output buffer OFF
Settling time (full scale:
for a 12-bit code
transition between the
tSETTLING lowest and the highest CL ≤ 50 pF, RL ≥ 5 kΩ - 7 12 µs
input codes till
DAC_OUT reaches final
value ±1LSB
Max frequency for a
correct DAC_OUT
change (95% of final
Update rate CL ≤ 50 pF, RL ≥ 5 kΩ - - 1 Msps
value) with 1 LSB
variation in the input
code
Wakeup time from off
state (setting the ENx bit
tWAKEUP CL ≤ 50 pF, RL ≥ 5 kΩ - 9 15 µs
in the DAC Control
(8)
register)
VDDA supply rejection
PSRR+ ratio (static DC CL ≤ 50 pF, RL ≥ 5 kΩ - -60 -35 dB
measurement)
1. Data based on characterization results.
2. Connected between DAC_OUT and VSSA.
3. Difference between two consecutive codes - 1 LSB.

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Electrical characteristics STM32L100RC

4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Figure 26. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.

6.3.19 Operational amplifier characteristics

Table 58. Operational amplifier characteristics

Symbol Parameter Condition(1) Min(2) Typ Max(2) Unit

CMIR Common mode input range - 0 - VDD

Maximum
- - - ±15
calibration range
VIOFFSET Input offset voltage mV
After offset
- - - ±1.5
calibration

Input offset voltage Normal mode - - - ±40 µV/°C

ΔVIOFFSET
drift Low-power mode - - - ±80
Dedicated input - - 1
IIB Input current bias General purpose 75 °C nA
- - 10
input
Normal mode - - - 500
ILOAD Drive current µA
Low-power mode - - - 100
Normal mode No load, - 100 220
IDD Consumption µA
Low-power mode quiescent mode - 30 60

Common mode Normal mode - - -85 -

CMRR dB
rejection ration Low-power mode - - -90 -

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Table 58. Operational amplifier characteristics (continued)

Symbol Parameter Condition(1) Min(2) Typ Max(2) Unit

Power supply Normal mode - -85 -

PSRR DC dB
rejection ratio Low-power mode - -90 -
Normal mode 400 1000 3000
VDD>2.4 V
Low-power mode 150 300 800
GBW Bandwidth kHZ
Normal mode 200 500 2200
VDD<2.4 V
Low-power mode 70 150 800
VDD>2.4 V
Normal mode (between 0.1 V and - 700 -
VDD-0.1 V)
SR Slew rate Low-power mode VDD>2.4 V - 100 - V/ms

Normal mode - 300 -

VDD<2.4 V
Low-power mode - 50 -
Normal mode 55 100 -
AO Open loop gain dB
Low-power mode 65 110 -
Normal mode 4 - -
RL Resistive load VDD<2.4 V kΩ
Low-power mode 20 - -
CL Capacitive load - - - 50 pF
VDD-
High saturation Normal mode - -
VOHSAT 100
voltage
Low-power mode ILOAD = max or VDD-50 - - mV
RL = min
Low saturation Normal mode - - 100
VOLSAT
voltage Low-power mode - - 50
ϕm Phase margin - - 60 - °
GM Gain margin - - -12 - dB
Offset trim time: during calibration,
tOFFTRIM minimum time needed between two - - 1 - ms
steps to have 1 mV accuracy
CL ≤50 pf,
Normal mode - 10 -
RL ≥ 4 kΩ
tWAKEUP Wakeup time µs
CL ≤50 pf,
Low-power mode - 30 -
RL ≥ 20 kΩ
1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when VDD is below 2 V. Otherwise to the full
ambient temperature range (-40 °C to 85 °C, -40 °C to 105 °C).
2. Guaranteed by characterization results.

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6.3.20 Comparator

Table 59. Comparator 1 characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

VDDA Analog supply voltage - 1.65 3.6 V

R400K R400K value - - 400 -
kΩ
R10K R10K value - - 10 -
Comparator 1 input
VIN - 0.6 - VDDA V
voltage range
tSTART Comparator startup time - - 7 10
µs
(2)
td Propagation delay - - 3 10
Voffset Comparator offset - - ±3 ±10 mV
VDDA = 3.6 V
Comparator offset
VIN+ = 0 V
dVoffset/dt variation in worst voltage 0 1.5 10 mV/1000 h
VIN- = VREFINT
stress conditions
TA = 25 ° C
ICOMP1 Current consumption(3) - - 160 260 nA
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.

Table 60. Comparator 2 characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

VDDA Analog supply voltage - 1.65 - 3.6 V

VIN Comparator 2 input voltage range - 0 - VDDA V
Fast mode - 15 20
tSTART Comparator startup time
Slow mode - 20 25
1.65 V ≤VDDA ≤2.7 V - 1.8 3.5
td slow Propagation delay(2) in slow mode µs
2.7 V ≤VDDA ≤3.6 V - 2.5 6
1.65 V ≤VDDA ≤2.7 V - 0.8 2
td fast Propagation delay(2) in fast mode
2.7 V ≤VDDA ≤3.6 V - 1.2 4
Voffset Comparator offset error - ±4 ±20 mV
VDDA = 3.3V
TA = 0 to 50 ° C
dThreshold/ Threshold voltage temperature V- =VREFINT, ppm
- 15 100
dt coefficient 3/4 VREFINT, /°C
1/2 VREFINT,
1/4 VREFINT.
Fast mode - 3.5 5
ICOMP2 Current consumption(3) µA
Slow mode - 0.5 2
1. Guaranteed by characterization results.

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2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.

6.3.21 LCD controller

The device embeds a built-in step-up converter to provide a constant LCD reference voltage
independently from the VDD voltage. An external capacitor Cext must be connected to the
VLCD pin to decouple this converter.

Table 61. LCD controller characteristics

Symbol Parameter Min Typ Max Unit

VLCD LCD external voltage - - 3.6

VLCD0 LCD internal reference voltage 0 - 2.6 -
VLCD1 LCD internal reference voltage 1 - 2.73 -
VLCD2 LCD internal reference voltage 2 - 2.86 -
VLCD3 LCD internal reference voltage 3 - 2.98 - V
VLCD4 LCD internal reference voltage 4 - 3.12 -
VLCD5 LCD internal reference voltage 5 - 3.26 -
VLCD6 LCD internal reference voltage 6 - 3.4 -
VLCD7 LCD internal reference voltage 7 - 3.55 -
Cext VLCD external capacitance 0.1 - 2 µF
Supply current at VDD = 2.2 V - 3.3 -
ILCD(1) µA
Supply current at VDD = 3.0 V - 3.1 -
RHtot(2) Low drive resistive network overall value 5.28 6.6 7.92 MΩ
RL(2) High drive resistive network total value 192 240 288 kΩ
V44 Segment/Common highest level voltage - - VLCD V
V34 Segment/Common 3/4 level voltage - 3/4 VLCD -
V23 Segment/Common 2/3 level voltage - 2/3 VLCD -
V12 Segment/Common 1/2 level voltage - 1/2 VLCD -
V
V13 Segment/Common 1/3 level voltage - 1/3 VLCD -
V14 Segment/Common 1/4 level voltage - 1/4 VLCD -
V0 Segment/Common lowest level voltage 0 - -
Segment/Common level voltage error
ΔVxx(3) - - ± 50 mV
TA = -40 to 105 ° C
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design.
3. Guaranteed by characterization results.

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Package information STM32L100RC

7 Package information

In order to meet environmental requirements, ST offers this device in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

7.1 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat

package information
Figure 27. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline

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1. Drawing is not to scale.

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STM32L100RC

Table 62. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 11.800 12.000 12.200 0.4646 0.4724 0.4803
D1 9.800 10.000 10.200 0.3858 0.3937 0.4016
D3 - 7.500 - - 0.2953 -
E 11.800 12.000 12.200 0.4646 0.4724 0.4803
E1 9.800 10.000 10.200 0.3858 0.3937 0.4016
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
K 0.0 3.5 7.0 0.0 3.5 7.0
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 28. LQFP64 Recommended footprint

 


  






 


 





AIC

1. Dimensions are in millimeters.

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Package information STM32L100RC

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 29. LQFP64 device marking example

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1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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7.2 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Ʃ (VOL × IOL) + Ʃ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 63. Thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient
ΘJA 46 °C/W
LQFP64 - 10 x 10 mm / 0.5 mm pitch

Figure 30. Thermal resistance suffix 6




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Package information STM32L100RC

Figure 31. Thermal resistance suffix 7




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7.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

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STM32L100RC

8 Ordering information

Table 64. STM32L100RC ordering information scheme

Example: STM32 L 100 R C T 6 TR

Device family
STM32 = ARM-based 32-bit microcontroller

Product type
L = Low power

Device subfamily
100: Device with LCD

Pin count
R = 64 pins

Flash memory size

C = 256 Kbytes of Flash memory

Package
T = LQFP

Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105°C

Packing
TR = tape and reel
No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

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Revision history STM32L100RC

9 Revision history

Table 65. Document revision history

Date Revision Changes

25-Jul-2013 1 Initial release.

Updated electrical characteristics
Updated the conditions in Table 24: Low-power mode wakeup timings.
25-Jun-2014 2
Removed ambiguity of “ambient temperature” in the electrical
characteristics description.
Updated communication interfaces section including I2S characteristics.
Updated DMIPS features in cover page and description section.
Updated Table 7: STM32L100RC pin definitions with additional functions
12-Sep-2014 3 column.
Updated Table 18: Current consumption in Sleep mode Flash ON, OFF
mode.
Updated table: ADC Maximum source impedance, RAIN max.
Updated Section 7: Package information with new package device
09-Mar-2015 4 marking.
Updated Figure 4: Memory map.

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Table 65. Document revision history (continued)

Date Revision Changes

Updated Table 41: I/O static characteristics pull-up and pull-down values.
Updated Table 44: NRST pin characteristics pull-up values.
Updated Section 7: Package information adding information about other
optional marking or inset/upset marks.
Updated note 1 below all the package device marking figures.
Updated Section 7: Package information replacing “Marking of
engineering samples” by “device marking”.
Updated all the notes, removing ‘not tested in production’.
Updated Nested vectored interrupt controller (NVIC) in Section 3.2:
ARM® Cortex®-M3 core with MPU about process state automatically
saved.
Updated Table 2: Functionalities depending on the operating power
supply range removing I/O operation column and adding note about
GPIO speed.
Updated Table 40: I/O current injection susceptibility note by ‘injection is
not possible’.
28-Aug-2017 5
Updated Figure 15: Recommended NRST pin protection note about the
0.1uF capacitor.
Updated cover page putting eight SPIs in the peripheral communication
interface list.
Updated Table 4: Functionalities depending on the working mode (from
Run/active down to standby) LSI and LSE functionalities putting “Y” in
Standby mode.
Removed note 1 below Figure 2: Clock tree.
Updated Table 9: Voltage characteristics adding note about VREF- pin.
Updated Table 38: ESD absolute maximum ratings CDM class.
Updated Table 57: DAC characteristics resistive load.
Updated Section 3.1: Low-power modes Low-power run mode (MSI) RC
oscillator clock.
Updated Table 4: Functionalities depending on the working mode (from
Run/active down to standby) disabling I2C functionality in Low-power
Run and Low-power Sleep modes.

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 STM32L100RC

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